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707 lines
19 KiB
707 lines
19 KiB
/* |
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* Copyright (c) 2010 Broadcom Corporation |
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* |
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* Permission to use, copy, modify, and/or distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION |
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN |
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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* |
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* File contents: support functions for PCI/PCIe |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/delay.h> |
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#include <defs.h> |
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#include <chipcommon.h> |
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#include <brcmu_utils.h> |
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#include <brcm_hw_ids.h> |
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#include <soc.h> |
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#include "types.h" |
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#include "pub.h" |
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#include "pmu.h" |
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#include "aiutils.h" |
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/* slow_clk_ctl */ |
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/* slow clock source mask */ |
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#define SCC_SS_MASK 0x00000007 |
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/* source of slow clock is LPO */ |
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#define SCC_SS_LPO 0x00000000 |
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/* source of slow clock is crystal */ |
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#define SCC_SS_XTAL 0x00000001 |
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/* source of slow clock is PCI */ |
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#define SCC_SS_PCI 0x00000002 |
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/* LPOFreqSel, 1: 160Khz, 0: 32KHz */ |
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#define SCC_LF 0x00000200 |
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/* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */ |
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#define SCC_LP 0x00000400 |
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/* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */ |
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#define SCC_FS 0x00000800 |
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/* IgnorePllOffReq, 1/0: |
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* power logic ignores/honors PLL clock disable requests from core |
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*/ |
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#define SCC_IP 0x00001000 |
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/* XtalControlEn, 1/0: |
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* power logic does/doesn't disable crystal when appropriate |
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*/ |
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#define SCC_XC 0x00002000 |
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/* XtalPU (RO), 1/0: crystal running/disabled */ |
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#define SCC_XP 0x00004000 |
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/* ClockDivider (SlowClk = 1/(4+divisor)) */ |
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#define SCC_CD_MASK 0xffff0000 |
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#define SCC_CD_SHIFT 16 |
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/* system_clk_ctl */ |
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/* ILPen: Enable Idle Low Power */ |
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#define SYCC_IE 0x00000001 |
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/* ALPen: Enable Active Low Power */ |
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#define SYCC_AE 0x00000002 |
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/* ForcePLLOn */ |
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#define SYCC_FP 0x00000004 |
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/* Force ALP (or HT if ALPen is not set */ |
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#define SYCC_AR 0x00000008 |
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/* Force HT */ |
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#define SYCC_HR 0x00000010 |
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/* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ |
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#define SYCC_CD_MASK 0xffff0000 |
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#define SYCC_CD_SHIFT 16 |
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#define CST4329_SPROM_OTP_SEL_MASK 0x00000003 |
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/* OTP is powered up, use def. CIS, no SPROM */ |
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#define CST4329_DEFCIS_SEL 0 |
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/* OTP is powered up, SPROM is present */ |
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#define CST4329_SPROM_SEL 1 |
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/* OTP is powered up, no SPROM */ |
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#define CST4329_OTP_SEL 2 |
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/* OTP is powered down, SPROM is present */ |
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#define CST4329_OTP_PWRDN 3 |
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#define CST4329_SPI_SDIO_MODE_MASK 0x00000004 |
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#define CST4329_SPI_SDIO_MODE_SHIFT 2 |
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/* 43224 chip-specific ChipControl register bits */ |
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#define CCTRL43224_GPIO_TOGGLE 0x8000 |
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/* 12 mA drive strength */ |
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#define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 |
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/* 12 mA drive strength for later 43224s */ |
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#define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 |
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/* 43236 Chip specific ChipStatus register bits */ |
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#define CST43236_SFLASH_MASK 0x00000040 |
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#define CST43236_OTP_MASK 0x00000080 |
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#define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ |
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#define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ |
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#define CST43236_BOOT_MASK 0x00001800 |
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#define CST43236_BOOT_SHIFT 11 |
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#define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ |
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#define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ |
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#define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ |
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#define CST43236_BOOT_FROM_INVALID 3 |
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/* 4331 chip-specific ChipControl register bits */ |
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/* 0 disable */ |
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#define CCTRL4331_BT_COEXIST (1<<0) |
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/* 0 SECI is disabled (JTAG functional) */ |
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#define CCTRL4331_SECI (1<<1) |
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/* 0 disable */ |
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#define CCTRL4331_EXT_LNA (1<<2) |
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/* sprom/gpio13-15 mux */ |
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#define CCTRL4331_SPROM_GPIO13_15 (1<<3) |
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/* 0 ext pa disable, 1 ext pa enabled */ |
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#define CCTRL4331_EXTPA_EN (1<<4) |
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/* set drive out GPIO_CLK on sprom_cs pin */ |
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#define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) |
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/* use sprom_cs pin as PCIE mdio interface */ |
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#define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) |
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/* aband extpa will be at gpio2/5 and sprom_dout */ |
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#define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) |
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/* override core control on pipe_AuxClkEnable */ |
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#define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) |
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/* override core control on pipe_AuxPowerDown */ |
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#define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) |
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/* pcie_auxclkenable */ |
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#define CCTRL4331_PCIE_AUXCLKEN (1<<10) |
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/* pcie_pipe_pllpowerdown */ |
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#define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) |
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/* enable bt_shd0 at gpio4 */ |
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#define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) |
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/* enable bt_shd1 at gpio5 */ |
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#define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) |
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/* 4331 Chip specific ChipStatus register bits */ |
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/* crystal frequency 20/40Mhz */ |
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#define CST4331_XTAL_FREQ 0x00000001 |
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#define CST4331_SPROM_PRESENT 0x00000002 |
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#define CST4331_OTP_PRESENT 0x00000004 |
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#define CST4331_LDO_RF 0x00000008 |
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#define CST4331_LDO_PAR 0x00000010 |
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/* 4319 chip-specific ChipStatus register bits */ |
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#define CST4319_SPI_CPULESSUSB 0x00000001 |
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#define CST4319_SPI_CLK_POL 0x00000002 |
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#define CST4319_SPI_CLK_PH 0x00000008 |
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/* gpio [7:6], SDIO CIS selection */ |
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#define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 |
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#define CST4319_SPROM_OTP_SEL_SHIFT 6 |
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/* use default CIS, OTP is powered up */ |
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#define CST4319_DEFCIS_SEL 0x00000000 |
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/* use SPROM, OTP is powered up */ |
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#define CST4319_SPROM_SEL 0x00000040 |
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/* use OTP, OTP is powered up */ |
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#define CST4319_OTP_SEL 0x00000080 |
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/* use SPROM, OTP is powered down */ |
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#define CST4319_OTP_PWRDN 0x000000c0 |
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/* gpio [8], sdio/usb mode */ |
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#define CST4319_SDIO_USB_MODE 0x00000100 |
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#define CST4319_REMAP_SEL_MASK 0x00000600 |
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#define CST4319_ILPDIV_EN 0x00000800 |
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#define CST4319_XTAL_PD_POL 0x00001000 |
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#define CST4319_LPO_SEL 0x00002000 |
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#define CST4319_RES_INIT_MODE 0x0000c000 |
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/* PALDO is configured with external PNP */ |
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#define CST4319_PALDO_EXTPNP 0x00010000 |
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#define CST4319_CBUCK_MODE_MASK 0x00060000 |
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#define CST4319_CBUCK_MODE_BURST 0x00020000 |
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#define CST4319_CBUCK_MODE_LPBURST 0x00060000 |
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#define CST4319_RCAL_VALID 0x01000000 |
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#define CST4319_RCAL_VALUE_MASK 0x3e000000 |
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#define CST4319_RCAL_VALUE_SHIFT 25 |
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/* 4336 chip-specific ChipStatus register bits */ |
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#define CST4336_SPI_MODE_MASK 0x00000001 |
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#define CST4336_SPROM_PRESENT 0x00000002 |
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#define CST4336_OTP_PRESENT 0x00000004 |
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#define CST4336_ARMREMAP_0 0x00000008 |
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#define CST4336_ILPDIV_EN_MASK 0x00000010 |
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#define CST4336_ILPDIV_EN_SHIFT 4 |
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#define CST4336_XTAL_PD_POL_MASK 0x00000020 |
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#define CST4336_XTAL_PD_POL_SHIFT 5 |
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#define CST4336_LPO_SEL_MASK 0x00000040 |
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#define CST4336_LPO_SEL_SHIFT 6 |
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#define CST4336_RES_INIT_MODE_MASK 0x00000180 |
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#define CST4336_RES_INIT_MODE_SHIFT 7 |
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#define CST4336_CBUCK_MODE_MASK 0x00000600 |
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#define CST4336_CBUCK_MODE_SHIFT 9 |
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/* 4313 chip-specific ChipStatus register bits */ |
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#define CST4313_SPROM_PRESENT 1 |
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#define CST4313_OTP_PRESENT 2 |
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#define CST4313_SPROM_OTP_SEL_MASK 0x00000002 |
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#define CST4313_SPROM_OTP_SEL_SHIFT 0 |
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/* 4313 Chip specific ChipControl register bits */ |
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/* 12 mA drive strengh for later 4313 */ |
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#define CCTRL_4313_12MA_LED_DRIVE 0x00000007 |
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/* Manufacturer Ids */ |
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#define MFGID_ARM 0x43b |
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#define MFGID_BRCM 0x4bf |
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#define MFGID_MIPS 0x4a7 |
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/* Enumeration ROM registers */ |
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#define ER_EROMENTRY 0x000 |
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#define ER_REMAPCONTROL 0xe00 |
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#define ER_REMAPSELECT 0xe04 |
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#define ER_MASTERSELECT 0xe10 |
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#define ER_ITCR 0xf00 |
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#define ER_ITIP 0xf04 |
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/* Erom entries */ |
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#define ER_TAG 0xe |
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#define ER_TAG1 0x6 |
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#define ER_VALID 1 |
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#define ER_CI 0 |
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#define ER_MP 2 |
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#define ER_ADD 4 |
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#define ER_END 0xe |
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#define ER_BAD 0xffffffff |
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/* EROM CompIdentA */ |
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#define CIA_MFG_MASK 0xfff00000 |
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#define CIA_MFG_SHIFT 20 |
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#define CIA_CID_MASK 0x000fff00 |
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#define CIA_CID_SHIFT 8 |
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#define CIA_CCL_MASK 0x000000f0 |
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#define CIA_CCL_SHIFT 4 |
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/* EROM CompIdentB */ |
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#define CIB_REV_MASK 0xff000000 |
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#define CIB_REV_SHIFT 24 |
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#define CIB_NSW_MASK 0x00f80000 |
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#define CIB_NSW_SHIFT 19 |
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#define CIB_NMW_MASK 0x0007c000 |
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#define CIB_NMW_SHIFT 14 |
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#define CIB_NSP_MASK 0x00003e00 |
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#define CIB_NSP_SHIFT 9 |
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#define CIB_NMP_MASK 0x000001f0 |
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#define CIB_NMP_SHIFT 4 |
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/* EROM AddrDesc */ |
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#define AD_ADDR_MASK 0xfffff000 |
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#define AD_SP_MASK 0x00000f00 |
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#define AD_SP_SHIFT 8 |
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#define AD_ST_MASK 0x000000c0 |
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#define AD_ST_SHIFT 6 |
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#define AD_ST_SLAVE 0x00000000 |
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#define AD_ST_BRIDGE 0x00000040 |
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#define AD_ST_SWRAP 0x00000080 |
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#define AD_ST_MWRAP 0x000000c0 |
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#define AD_SZ_MASK 0x00000030 |
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#define AD_SZ_SHIFT 4 |
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#define AD_SZ_4K 0x00000000 |
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#define AD_SZ_8K 0x00000010 |
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#define AD_SZ_16K 0x00000020 |
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#define AD_SZ_SZD 0x00000030 |
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#define AD_AG32 0x00000008 |
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#define AD_ADDR_ALIGN 0x00000fff |
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#define AD_SZ_BASE 0x00001000 /* 4KB */ |
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/* EROM SizeDesc */ |
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#define SD_SZ_MASK 0xfffff000 |
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#define SD_SG32 0x00000008 |
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#define SD_SZ_ALIGN 0x00000fff |
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/* PCI config space bit 4 for 4306c0 slow clock source */ |
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#define PCI_CFG_GPIO_SCS 0x10 |
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/* PCI config space GPIO 14 for Xtal power-up */ |
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#define PCI_CFG_GPIO_XTAL 0x40 |
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/* PCI config space GPIO 15 for PLL power-down */ |
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#define PCI_CFG_GPIO_PLL 0x80 |
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/* power control defines */ |
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#define PLL_DELAY 150 /* us pll on delay */ |
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#define FREF_DELAY 200 /* us fref change delay */ |
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#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */ |
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/* resetctrl */ |
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#define AIRC_RESET 1 |
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#define NOREV -1 /* Invalid rev */ |
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/* GPIO Based LED powersave defines */ |
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#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */ |
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#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */ |
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/* When Srom support present, fields in sromcontrol */ |
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#define SRC_START 0x80000000 |
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#define SRC_BUSY 0x80000000 |
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#define SRC_OPCODE 0x60000000 |
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#define SRC_OP_READ 0x00000000 |
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#define SRC_OP_WRITE 0x20000000 |
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#define SRC_OP_WRDIS 0x40000000 |
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#define SRC_OP_WREN 0x60000000 |
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#define SRC_OTPSEL 0x00000010 |
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#define SRC_LOCK 0x00000008 |
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#define SRC_SIZE_MASK 0x00000006 |
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#define SRC_SIZE_1K 0x00000000 |
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#define SRC_SIZE_4K 0x00000002 |
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#define SRC_SIZE_16K 0x00000004 |
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#define SRC_SIZE_SHIFT 1 |
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#define SRC_PRESENT 0x00000001 |
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/* External PA enable mask */ |
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#define GPIO_CTRL_EPA_EN_MASK 0x40 |
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#define DEFAULT_GPIOTIMERVAL \ |
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((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME) |
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#define BADIDX (SI_MAXCORES + 1) |
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#define IS_SIM(chippkg) \ |
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((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) |
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#define GOODCOREADDR(x, b) \ |
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(((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \ |
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IS_ALIGNED((x), SI_CORE_SIZE)) |
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struct aidmp { |
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u32 oobselina30; /* 0x000 */ |
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u32 oobselina74; /* 0x004 */ |
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u32 PAD[6]; |
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u32 oobselinb30; /* 0x020 */ |
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u32 oobselinb74; /* 0x024 */ |
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u32 PAD[6]; |
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u32 oobselinc30; /* 0x040 */ |
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u32 oobselinc74; /* 0x044 */ |
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u32 PAD[6]; |
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u32 oobselind30; /* 0x060 */ |
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u32 oobselind74; /* 0x064 */ |
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u32 PAD[38]; |
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u32 oobselouta30; /* 0x100 */ |
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u32 oobselouta74; /* 0x104 */ |
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u32 PAD[6]; |
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u32 oobseloutb30; /* 0x120 */ |
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u32 oobseloutb74; /* 0x124 */ |
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u32 PAD[6]; |
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u32 oobseloutc30; /* 0x140 */ |
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u32 oobseloutc74; /* 0x144 */ |
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u32 PAD[6]; |
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u32 oobseloutd30; /* 0x160 */ |
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u32 oobseloutd74; /* 0x164 */ |
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u32 PAD[38]; |
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u32 oobsynca; /* 0x200 */ |
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u32 oobseloutaen; /* 0x204 */ |
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u32 PAD[6]; |
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u32 oobsyncb; /* 0x220 */ |
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u32 oobseloutben; /* 0x224 */ |
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u32 PAD[6]; |
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u32 oobsyncc; /* 0x240 */ |
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u32 oobseloutcen; /* 0x244 */ |
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u32 PAD[6]; |
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u32 oobsyncd; /* 0x260 */ |
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u32 oobseloutden; /* 0x264 */ |
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u32 PAD[38]; |
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u32 oobaextwidth; /* 0x300 */ |
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u32 oobainwidth; /* 0x304 */ |
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u32 oobaoutwidth; /* 0x308 */ |
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u32 PAD[5]; |
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u32 oobbextwidth; /* 0x320 */ |
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u32 oobbinwidth; /* 0x324 */ |
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u32 oobboutwidth; /* 0x328 */ |
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u32 PAD[5]; |
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u32 oobcextwidth; /* 0x340 */ |
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u32 oobcinwidth; /* 0x344 */ |
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u32 oobcoutwidth; /* 0x348 */ |
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u32 PAD[5]; |
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u32 oobdextwidth; /* 0x360 */ |
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u32 oobdinwidth; /* 0x364 */ |
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u32 oobdoutwidth; /* 0x368 */ |
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u32 PAD[37]; |
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u32 ioctrlset; /* 0x400 */ |
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u32 ioctrlclear; /* 0x404 */ |
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u32 ioctrl; /* 0x408 */ |
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u32 PAD[61]; |
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u32 iostatus; /* 0x500 */ |
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u32 PAD[127]; |
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u32 ioctrlwidth; /* 0x700 */ |
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u32 iostatuswidth; /* 0x704 */ |
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u32 PAD[62]; |
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u32 resetctrl; /* 0x800 */ |
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u32 resetstatus; /* 0x804 */ |
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u32 resetreadid; /* 0x808 */ |
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u32 resetwriteid; /* 0x80c */ |
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u32 PAD[60]; |
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u32 errlogctrl; /* 0x900 */ |
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u32 errlogdone; /* 0x904 */ |
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u32 errlogstatus; /* 0x908 */ |
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u32 errlogaddrlo; /* 0x90c */ |
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u32 errlogaddrhi; /* 0x910 */ |
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u32 errlogid; /* 0x914 */ |
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u32 errloguser; /* 0x918 */ |
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u32 errlogflags; /* 0x91c */ |
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u32 PAD[56]; |
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u32 intstatus; /* 0xa00 */ |
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u32 PAD[127]; |
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u32 config; /* 0xe00 */ |
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u32 PAD[63]; |
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u32 itcr; /* 0xf00 */ |
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u32 PAD[3]; |
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u32 itipooba; /* 0xf10 */ |
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u32 itipoobb; /* 0xf14 */ |
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u32 itipoobc; /* 0xf18 */ |
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u32 itipoobd; /* 0xf1c */ |
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u32 PAD[4]; |
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u32 itipoobaout; /* 0xf30 */ |
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u32 itipoobbout; /* 0xf34 */ |
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u32 itipoobcout; /* 0xf38 */ |
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u32 itipoobdout; /* 0xf3c */ |
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u32 PAD[4]; |
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u32 itopooba; /* 0xf50 */ |
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u32 itopoobb; /* 0xf54 */ |
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u32 itopoobc; /* 0xf58 */ |
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u32 itopoobd; /* 0xf5c */ |
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u32 PAD[4]; |
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u32 itopoobain; /* 0xf70 */ |
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u32 itopoobbin; /* 0xf74 */ |
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u32 itopoobcin; /* 0xf78 */ |
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u32 itopoobdin; /* 0xf7c */ |
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u32 PAD[4]; |
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u32 itopreset; /* 0xf90 */ |
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u32 PAD[15]; |
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u32 peripherialid4; /* 0xfd0 */ |
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u32 peripherialid5; /* 0xfd4 */ |
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u32 peripherialid6; /* 0xfd8 */ |
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u32 peripherialid7; /* 0xfdc */ |
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u32 peripherialid0; /* 0xfe0 */ |
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u32 peripherialid1; /* 0xfe4 */ |
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u32 peripherialid2; /* 0xfe8 */ |
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u32 peripherialid3; /* 0xfec */ |
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u32 componentid0; /* 0xff0 */ |
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u32 componentid1; /* 0xff4 */ |
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u32 componentid2; /* 0xff8 */ |
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u32 componentid3; /* 0xffc */ |
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}; |
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static bool |
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ai_buscore_setup(struct si_info *sii, struct bcma_device *cc) |
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{ |
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/* no cores found, bail out */ |
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if (cc->bus->nr_cores == 0) |
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return false; |
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/* get chipcommon rev */ |
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sii->pub.ccrev = cc->id.rev; |
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/* get chipcommon chipstatus */ |
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sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus)); |
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/* get chipcommon capabilites */ |
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sii->pub.cccaps = bcma_read32(cc, CHIPCREGOFFS(capabilities)); |
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/* get pmu rev and caps */ |
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if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) { |
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sii->pub.pmucaps = bcma_read32(cc, |
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CHIPCREGOFFS(pmucapabilities)); |
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sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK; |
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} |
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return true; |
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} |
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static struct si_info *ai_doattach(struct si_info *sii, |
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struct bcma_bus *pbus) |
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{ |
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struct si_pub *sih = &sii->pub; |
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struct bcma_device *cc; |
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sii->icbus = pbus; |
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sii->pcibus = pbus->host_pci; |
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/* switch to Chipcommon core */ |
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cc = pbus->drv_cc.core; |
|
|
|
sih->chip = pbus->chipinfo.id; |
|
sih->chiprev = pbus->chipinfo.rev; |
|
sih->chippkg = pbus->chipinfo.pkg; |
|
sih->boardvendor = pbus->boardinfo.vendor; |
|
sih->boardtype = pbus->boardinfo.type; |
|
|
|
if (!ai_buscore_setup(sii, cc)) |
|
goto exit; |
|
|
|
/* === NVRAM, clock is ready === */ |
|
bcma_write32(cc, CHIPCREGOFFS(gpiopullup), 0); |
|
bcma_write32(cc, CHIPCREGOFFS(gpiopulldown), 0); |
|
|
|
/* PMU specific initializations */ |
|
if (ai_get_cccaps(sih) & CC_CAP_PMU) { |
|
(void)si_pmu_measure_alpclk(sih); |
|
} |
|
|
|
return sii; |
|
|
|
exit: |
|
|
|
return NULL; |
|
} |
|
|
|
/* |
|
* Allocate a si handle and do the attach. |
|
*/ |
|
struct si_pub * |
|
ai_attach(struct bcma_bus *pbus) |
|
{ |
|
struct si_info *sii; |
|
|
|
/* alloc struct si_info */ |
|
sii = kzalloc(sizeof(struct si_info), GFP_ATOMIC); |
|
if (sii == NULL) |
|
return NULL; |
|
|
|
if (ai_doattach(sii, pbus) == NULL) { |
|
kfree(sii); |
|
return NULL; |
|
} |
|
|
|
return (struct si_pub *) sii; |
|
} |
|
|
|
/* may be called with core in reset */ |
|
void ai_detach(struct si_pub *sih) |
|
{ |
|
struct si_info *sii; |
|
|
|
sii = container_of(sih, struct si_info, pub); |
|
|
|
kfree(sii); |
|
} |
|
|
|
/* |
|
* read/modify chipcommon core register. |
|
*/ |
|
uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val) |
|
{ |
|
struct bcma_device *cc; |
|
u32 w; |
|
struct si_info *sii; |
|
|
|
sii = container_of(sih, struct si_info, pub); |
|
cc = sii->icbus->drv_cc.core; |
|
|
|
/* mask and set */ |
|
if (mask || val) |
|
bcma_maskset32(cc, regoff, ~mask, val); |
|
|
|
/* readback */ |
|
w = bcma_read32(cc, regoff); |
|
|
|
return w; |
|
} |
|
|
|
/* return the slow clock source - LPO, XTAL, or PCI */ |
|
static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc) |
|
{ |
|
return SCC_SS_XTAL; |
|
} |
|
|
|
/* |
|
* return the ILP (slowclock) min or max frequency |
|
* precondition: we've established the chip has dynamic clk control |
|
*/ |
|
static uint ai_slowclk_freq(struct si_pub *sih, bool max_freq, |
|
struct bcma_device *cc) |
|
{ |
|
uint div; |
|
|
|
/* Chipc rev 10 is InstaClock */ |
|
div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl)); |
|
div = 4 * ((div >> SYCC_CD_SHIFT) + 1); |
|
return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div); |
|
} |
|
|
|
static void |
|
ai_clkctl_setdelay(struct si_pub *sih, struct bcma_device *cc) |
|
{ |
|
uint slowmaxfreq, pll_delay, slowclk; |
|
uint pll_on_delay, fref_sel_delay; |
|
|
|
pll_delay = PLL_DELAY; |
|
|
|
/* |
|
* If the slow clock is not sourced by the xtal then |
|
* add the xtal_on_delay since the xtal will also be |
|
* powered down by dynamic clk control logic. |
|
*/ |
|
|
|
slowclk = ai_slowclk_src(sih, cc); |
|
if (slowclk != SCC_SS_XTAL) |
|
pll_delay += XTAL_ON_DELAY; |
|
|
|
/* Starting with 4318 it is ILP that is used for the delays */ |
|
slowmaxfreq = |
|
ai_slowclk_freq(sih, false, cc); |
|
|
|
pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000; |
|
fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000; |
|
|
|
bcma_write32(cc, CHIPCREGOFFS(pll_on_delay), pll_on_delay); |
|
bcma_write32(cc, CHIPCREGOFFS(fref_sel_delay), fref_sel_delay); |
|
} |
|
|
|
/* initialize power control delay registers */ |
|
void ai_clkctl_init(struct si_pub *sih) |
|
{ |
|
struct si_info *sii = container_of(sih, struct si_info, pub); |
|
struct bcma_device *cc; |
|
|
|
if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL)) |
|
return; |
|
|
|
cc = sii->icbus->drv_cc.core; |
|
if (cc == NULL) |
|
return; |
|
|
|
/* set all Instaclk chip ILP to 1 MHz */ |
|
bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK, |
|
(ILP_DIV_1MHZ << SYCC_CD_SHIFT)); |
|
|
|
ai_clkctl_setdelay(sih, cc); |
|
} |
|
|
|
/* |
|
* return the value suitable for writing to the |
|
* dot11 core FAST_PWRUP_DELAY register |
|
*/ |
|
u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih) |
|
{ |
|
struct si_info *sii; |
|
struct bcma_device *cc; |
|
uint slowminfreq; |
|
u16 fpdelay; |
|
|
|
sii = container_of(sih, struct si_info, pub); |
|
if (ai_get_cccaps(sih) & CC_CAP_PMU) { |
|
fpdelay = si_pmu_fast_pwrup_delay(sih); |
|
return fpdelay; |
|
} |
|
|
|
if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL)) |
|
return 0; |
|
|
|
fpdelay = 0; |
|
cc = sii->icbus->drv_cc.core; |
|
if (cc) { |
|
slowminfreq = ai_slowclk_freq(sih, false, cc); |
|
fpdelay = (((bcma_read32(cc, CHIPCREGOFFS(pll_on_delay)) + 2) |
|
* 1000000) + (slowminfreq - 1)) / slowminfreq; |
|
} |
|
return fpdelay; |
|
} |
|
|
|
/* |
|
* clock control policy function throught chipcommon |
|
* |
|
* set dynamic clk control mode (forceslow, forcefast, dynamic) |
|
* returns true if we are forcing fast clock |
|
* this is a wrapper over the next internal function |
|
* to allow flexible policy settings for outside caller |
|
*/ |
|
bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode) |
|
{ |
|
struct si_info *sii; |
|
struct bcma_device *cc; |
|
|
|
sii = container_of(sih, struct si_info, pub); |
|
|
|
cc = sii->icbus->drv_cc.core; |
|
bcma_core_set_clockmode(cc, mode); |
|
return mode == BCMA_CLKMODE_FAST; |
|
} |
|
|
|
/* Enable BT-COEX & Ex-PA for 4313 */ |
|
void ai_epa_4313war(struct si_pub *sih) |
|
{ |
|
struct si_info *sii = container_of(sih, struct si_info, pub); |
|
struct bcma_device *cc; |
|
|
|
cc = sii->icbus->drv_cc.core; |
|
|
|
/* EPA Fix */ |
|
bcma_set32(cc, CHIPCREGOFFS(gpiocontrol), GPIO_CTRL_EPA_EN_MASK); |
|
} |
|
|
|
/* check if the device is removed */ |
|
bool ai_deviceremoved(struct si_pub *sih) |
|
{ |
|
u32 w = 0; |
|
struct si_info *sii; |
|
|
|
sii = container_of(sih, struct si_info, pub); |
|
|
|
if (sii->icbus->hosttype != BCMA_HOSTTYPE_PCI) |
|
return false; |
|
|
|
pci_read_config_dword(sii->pcibus, PCI_VENDOR_ID, &w); |
|
if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM) |
|
return true; |
|
|
|
return false; |
|
}
|
|
|