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382 lines
11 KiB
382 lines
11 KiB
// SPDX-License-Identifier: ISC |
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/* |
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* Copyright (c) 2010 Broadcom Corporation |
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*/ |
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#ifndef BRCMFMAC_SDIO_H |
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#define BRCMFMAC_SDIO_H |
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#include <linux/skbuff.h> |
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#include <linux/firmware.h> |
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#include "firmware.h" |
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#define SDIOD_FBR_SIZE 0x100 |
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/* io_en */ |
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#define SDIO_FUNC_ENABLE_1 0x02 |
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#define SDIO_FUNC_ENABLE_2 0x04 |
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/* io_rdys */ |
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#define SDIO_FUNC_READY_1 0x02 |
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#define SDIO_FUNC_READY_2 0x04 |
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/* intr_status */ |
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#define INTR_STATUS_FUNC1 0x2 |
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#define INTR_STATUS_FUNC2 0x4 |
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/* mask of register map */ |
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#define REG_F0_REG_MASK 0x7FF |
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#define REG_F1_MISC_MASK 0x1FFFF |
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/* function 0 vendor specific CCCR registers */ |
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#define SDIO_CCCR_BRCM_CARDCAP 0xf0 |
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#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT BIT(1) |
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#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT BIT(2) |
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#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC BIT(3) |
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/* Interrupt enable bits for each function */ |
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#define SDIO_CCCR_IEN_FUNC0 BIT(0) |
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#define SDIO_CCCR_IEN_FUNC1 BIT(1) |
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#define SDIO_CCCR_IEN_FUNC2 BIT(2) |
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#define SDIO_CCCR_BRCM_CARDCTRL 0xf1 |
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#define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET BIT(1) |
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#define SDIO_CCCR_BRCM_SEPINT 0xf2 |
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#define SDIO_CCCR_BRCM_SEPINT_MASK BIT(0) |
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#define SDIO_CCCR_BRCM_SEPINT_OE BIT(1) |
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#define SDIO_CCCR_BRCM_SEPINT_ACT_HI BIT(2) |
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/* function 1 miscellaneous registers */ |
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/* sprom command and status */ |
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#define SBSDIO_SPROM_CS 0x10000 |
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/* sprom info register */ |
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#define SBSDIO_SPROM_INFO 0x10001 |
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/* sprom indirect access data byte 0 */ |
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#define SBSDIO_SPROM_DATA_LOW 0x10002 |
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/* sprom indirect access data byte 1 */ |
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#define SBSDIO_SPROM_DATA_HIGH 0x10003 |
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/* sprom indirect access addr byte 0 */ |
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#define SBSDIO_SPROM_ADDR_LOW 0x10004 |
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/* gpio select */ |
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#define SBSDIO_GPIO_SELECT 0x10005 |
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/* gpio output */ |
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#define SBSDIO_GPIO_OUT 0x10006 |
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/* gpio enable */ |
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#define SBSDIO_GPIO_EN 0x10007 |
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/* rev < 7, watermark for sdio device TX path */ |
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#define SBSDIO_WATERMARK 0x10008 |
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/* control busy signal generation */ |
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#define SBSDIO_DEVICE_CTL 0x10009 |
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/* SB Address Window Low (b15) */ |
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#define SBSDIO_FUNC1_SBADDRLOW 0x1000A |
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/* SB Address Window Mid (b23:b16) */ |
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#define SBSDIO_FUNC1_SBADDRMID 0x1000B |
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/* SB Address Window High (b31:b24) */ |
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#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C |
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/* Frame Control (frame term/abort) */ |
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#define SBSDIO_FUNC1_FRAMECTRL 0x1000D |
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/* ChipClockCSR (ALP/HT ctl/status) */ |
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#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E |
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/* SdioPullUp (on cmd, d0-d2) */ |
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#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F |
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/* Write Frame Byte Count Low */ |
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#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 |
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/* Write Frame Byte Count High */ |
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#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A |
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/* Read Frame Byte Count Low */ |
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#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B |
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/* Read Frame Byte Count High */ |
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#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C |
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/* MesBusyCtl (rev 11) */ |
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#define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D |
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/* Watermark for sdio device RX path */ |
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#define SBSDIO_MESBUSY_RXFIFO_WM_MASK 0x7F |
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#define SBSDIO_MESBUSY_RXFIFO_WM_SHIFT 0 |
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/* Enable busy capability for MES access */ |
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#define SBSDIO_MESBUSYCTRL_ENAB 0x80 |
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#define SBSDIO_MESBUSYCTRL_ENAB_SHIFT 7 |
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/* Sdio Core Rev 12 */ |
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#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E |
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#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1 |
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#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0 |
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#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2 |
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#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1 |
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#define SBSDIO_FUNC1_SLEEPCSR 0x1001F |
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#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1 |
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#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0 |
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#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1 |
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#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2 |
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#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1 |
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#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */ |
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#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */ |
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/* function 1 OCP space */ |
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/* sb offset addr is <= 15 bits, 32k */ |
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#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF |
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#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000 |
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/* with b15, maps to 32-bit SB access */ |
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#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 |
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/* Address bits from SBADDR regs */ |
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#define SBSDIO_SBWINDOW_MASK 0xffff8000 |
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#define SDIOH_READ 0 /* Read request */ |
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#define SDIOH_WRITE 1 /* Write request */ |
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#define SDIOH_DATA_FIX 0 /* Fixed addressing */ |
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#define SDIOH_DATA_INC 1 /* Incremental addressing */ |
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/* internal return code */ |
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#define SUCCESS 0 |
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#define ERROR 1 |
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/* Packet alignment for most efficient SDIO (can change based on platform) */ |
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#define BRCMF_SDALIGN (1 << 6) |
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/* watchdog polling interval */ |
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#define BRCMF_WD_POLL msecs_to_jiffies(10) |
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/** |
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* enum brcmf_sdiod_state - the state of the bus. |
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* |
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* @BRCMF_SDIOD_DOWN: Device can be accessed, no DPC. |
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* @BRCMF_SDIOD_DATA: Ready for data transfers, DPC enabled. |
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* @BRCMF_SDIOD_NOMEDIUM: No medium access to dongle possible. |
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*/ |
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enum brcmf_sdiod_state { |
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BRCMF_SDIOD_DOWN, |
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BRCMF_SDIOD_DATA, |
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BRCMF_SDIOD_NOMEDIUM |
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}; |
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struct brcmf_sdreg { |
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int func; |
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int offset; |
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int value; |
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}; |
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struct brcmf_sdio; |
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struct brcmf_sdiod_freezer; |
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struct brcmf_sdio_dev { |
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struct sdio_func *func1; |
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struct sdio_func *func2; |
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u32 sbwad; /* Save backplane window address */ |
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struct brcmf_core *cc_core; /* chipcommon core info struct */ |
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struct brcmf_sdio *bus; |
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struct device *dev; |
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struct brcmf_bus *bus_if; |
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struct brcmf_mp_device *settings; |
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bool oob_irq_requested; |
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bool sd_irq_requested; |
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bool irq_en; /* irq enable flags */ |
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spinlock_t irq_en_lock; |
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bool sg_support; |
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uint max_request_size; |
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ushort max_segment_count; |
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uint max_segment_size; |
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uint txglomsz; |
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struct sg_table sgtable; |
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char fw_name[BRCMF_FW_NAME_LEN]; |
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char nvram_name[BRCMF_FW_NAME_LEN]; |
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bool wowl_enabled; |
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enum brcmf_sdiod_state state; |
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struct brcmf_sdiod_freezer *freezer; |
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}; |
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/* sdio core registers */ |
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struct sdpcmd_regs { |
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u32 corecontrol; /* 0x00, rev8 */ |
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u32 corestatus; /* rev8 */ |
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u32 PAD[1]; |
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u32 biststatus; /* rev8 */ |
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/* PCMCIA access */ |
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u16 pcmciamesportaladdr; /* 0x010, rev8 */ |
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u16 PAD[1]; |
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u16 pcmciamesportalmask; /* rev8 */ |
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u16 PAD[1]; |
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u16 pcmciawrframebc; /* rev8 */ |
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u16 PAD[1]; |
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u16 pcmciaunderflowtimer; /* rev8 */ |
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u16 PAD[1]; |
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/* interrupt */ |
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u32 intstatus; /* 0x020, rev8 */ |
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u32 hostintmask; /* rev8 */ |
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u32 intmask; /* rev8 */ |
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u32 sbintstatus; /* rev8 */ |
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u32 sbintmask; /* rev8 */ |
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u32 funcintmask; /* rev4 */ |
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u32 PAD[2]; |
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u32 tosbmailbox; /* 0x040, rev8 */ |
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u32 tohostmailbox; /* rev8 */ |
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u32 tosbmailboxdata; /* rev8 */ |
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u32 tohostmailboxdata; /* rev8 */ |
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/* synchronized access to registers in SDIO clock domain */ |
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u32 sdioaccess; /* 0x050, rev8 */ |
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u32 PAD[3]; |
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/* PCMCIA frame control */ |
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u8 pcmciaframectrl; /* 0x060, rev8 */ |
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u8 PAD[3]; |
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u8 pcmciawatermark; /* rev8 */ |
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u8 PAD[155]; |
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/* interrupt batching control */ |
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u32 intrcvlazy; /* 0x100, rev8 */ |
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u32 PAD[3]; |
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/* counters */ |
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u32 cmd52rd; /* 0x110, rev8 */ |
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u32 cmd52wr; /* rev8 */ |
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u32 cmd53rd; /* rev8 */ |
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u32 cmd53wr; /* rev8 */ |
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u32 abort; /* rev8 */ |
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u32 datacrcerror; /* rev8 */ |
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u32 rdoutofsync; /* rev8 */ |
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u32 wroutofsync; /* rev8 */ |
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u32 writebusy; /* rev8 */ |
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u32 readwait; /* rev8 */ |
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u32 readterm; /* rev8 */ |
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u32 writeterm; /* rev8 */ |
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u32 PAD[40]; |
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u32 clockctlstatus; /* rev8 */ |
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u32 PAD[7]; |
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u32 PAD[128]; /* DMA engines */ |
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/* SDIO/PCMCIA CIS region */ |
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char cis[512]; /* 0x400-0x5ff, rev6 */ |
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/* PCMCIA function control registers */ |
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char pcmciafcr[256]; /* 0x600-6ff, rev6 */ |
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u16 PAD[55]; |
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/* PCMCIA backplane access */ |
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u16 backplanecsr; /* 0x76E, rev6 */ |
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u16 backplaneaddr0; /* rev6 */ |
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u16 backplaneaddr1; /* rev6 */ |
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u16 backplaneaddr2; /* rev6 */ |
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u16 backplaneaddr3; /* rev6 */ |
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u16 backplanedata0; /* rev6 */ |
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u16 backplanedata1; /* rev6 */ |
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u16 backplanedata2; /* rev6 */ |
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u16 backplanedata3; /* rev6 */ |
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u16 PAD[31]; |
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/* sprom "size" & "blank" info */ |
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u16 spromstatus; /* 0x7BE, rev2 */ |
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u32 PAD[464]; |
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u16 PAD[0x80]; |
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}; |
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/* Register/deregister interrupt handler. */ |
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int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev); |
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void brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev); |
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/* SDIO device register access interface */ |
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/* Accessors for SDIO Function 0 */ |
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#define brcmf_sdiod_func0_rb(sdiodev, addr, r) \ |
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sdio_f0_readb((sdiodev)->func1, (addr), (r)) |
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#define brcmf_sdiod_func0_wb(sdiodev, addr, v, ret) \ |
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sdio_f0_writeb((sdiodev)->func1, (v), (addr), (ret)) |
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/* Accessors for SDIO Function 1 */ |
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#define brcmf_sdiod_readb(sdiodev, addr, r) \ |
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sdio_readb((sdiodev)->func1, (addr), (r)) |
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#define brcmf_sdiod_writeb(sdiodev, addr, v, ret) \ |
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sdio_writeb((sdiodev)->func1, (v), (addr), (ret)) |
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u32 brcmf_sdiod_readl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret); |
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void brcmf_sdiod_writel(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data, |
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int *ret); |
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/* Buffer transfer to/from device (client) core via cmd53. |
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* fn: function number |
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* flags: backplane width, address increment, sync/async |
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* buf: pointer to memory data buffer |
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* nbytes: number of bytes to transfer to/from buf |
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* pkt: pointer to packet associated with buf (if any) |
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* complete: callback function for command completion (async only) |
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* handle: handle for completion callback (first arg in callback) |
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* Returns 0 or error code. |
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* NOTE: Async operation is not currently supported. |
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*/ |
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int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev, |
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struct sk_buff_head *pktq); |
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int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes); |
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int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt); |
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int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes); |
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int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev, |
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struct sk_buff_head *pktq, uint totlen); |
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/* Flags bits */ |
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/* Four-byte target (backplane) width (vs. two-byte) */ |
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#define SDIO_REQ_4BYTE 0x1 |
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/* Fixed address (FIFO) (vs. incrementing address) */ |
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#define SDIO_REQ_FIXED 0x2 |
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/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only). |
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* rw: read or write (0/1) |
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* addr: direct SDIO address |
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* buf: pointer to memory data buffer |
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* nbytes: number of bytes to transfer to/from buf |
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* Returns 0 or error code. |
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*/ |
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int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address, |
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u8 *data, uint size); |
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/* Issue an abort to the specified function */ |
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int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, struct sdio_func *func); |
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void brcmf_sdiod_sgtable_alloc(struct brcmf_sdio_dev *sdiodev); |
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void brcmf_sdiod_change_state(struct brcmf_sdio_dev *sdiodev, |
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enum brcmf_sdiod_state state); |
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#ifdef CONFIG_PM_SLEEP |
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bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev); |
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void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev); |
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void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev); |
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void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev); |
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#else |
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static inline bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev) |
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{ |
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return false; |
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} |
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static inline void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev) |
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{ |
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} |
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static inline void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev) |
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{ |
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} |
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static inline void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev) |
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{ |
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} |
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#endif /* CONFIG_PM_SLEEP */ |
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int brcmf_sdiod_probe(struct brcmf_sdio_dev *sdiodev); |
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int brcmf_sdiod_remove(struct brcmf_sdio_dev *sdiodev); |
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struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev); |
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void brcmf_sdio_remove(struct brcmf_sdio *bus); |
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void brcmf_sdio_isr(struct brcmf_sdio *bus, bool in_isr); |
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void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active); |
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void brcmf_sdio_wowl_config(struct device *dev, bool enabled); |
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int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep); |
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void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus); |
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#endif /* BRCMFMAC_SDIO_H */
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