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1048 lines
28 KiB
1048 lines
28 KiB
/* |
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* Copyright (c) 2008-2011 Atheros Communications Inc. |
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* |
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* Permission to use, copy, modify, and/or distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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*/ |
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|
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#include "hw.h" |
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#include "hw-ops.h" |
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#include <linux/export.h> |
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|
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static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, |
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struct ath9k_tx_queue_info *qi) |
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{ |
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ath_dbg(ath9k_hw_common(ah), INTERRUPT, |
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"tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", |
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ah->txok_interrupt_mask, ah->txerr_interrupt_mask, |
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ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, |
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ah->txurn_interrupt_mask); |
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ENABLE_REGWRITE_BUFFER(ah); |
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REG_WRITE(ah, AR_IMR_S0, |
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SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) |
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| SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); |
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REG_WRITE(ah, AR_IMR_S1, |
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SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) |
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| SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); |
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ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN; |
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ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN); |
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REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); |
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|
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REGWRITE_BUFFER_FLUSH(ah); |
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} |
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|
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u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) |
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{ |
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return REG_READ(ah, AR_QTXDP(q)); |
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} |
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EXPORT_SYMBOL(ath9k_hw_gettxbuf); |
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|
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void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp) |
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{ |
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REG_WRITE(ah, AR_QTXDP(q), txdp); |
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} |
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EXPORT_SYMBOL(ath9k_hw_puttxbuf); |
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|
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void ath9k_hw_txstart(struct ath_hw *ah, u32 q) |
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{ |
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ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q); |
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REG_WRITE(ah, AR_Q_TXE, 1 << q); |
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} |
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EXPORT_SYMBOL(ath9k_hw_txstart); |
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|
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u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) |
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{ |
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u32 npend; |
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|
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npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; |
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if (npend == 0) { |
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|
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if (REG_READ(ah, AR_Q_TXE) & (1 << q)) |
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npend = 1; |
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} |
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return npend; |
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} |
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EXPORT_SYMBOL(ath9k_hw_numtxpending); |
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|
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/** |
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* ath9k_hw_updatetxtriglevel - adjusts the frame trigger level |
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* |
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* @ah: atheros hardware struct |
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* @bIncTrigLevel: whether or not the frame trigger level should be updated |
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* |
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* The frame trigger level specifies the minimum number of bytes, |
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* in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO |
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* before the PCU will initiate sending the frame on the air. This can |
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* mean we initiate transmit before a full frame is on the PCU TX FIFO. |
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* Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs |
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* first) |
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* |
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* Caution must be taken to ensure to set the frame trigger level based |
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* on the DMA request size. For example if the DMA request size is set to |
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* 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because |
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* there need to be enough space in the tx FIFO for the requested transfer |
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* size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set |
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* the threshold to a value beyond 6, then the transmit will hang. |
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* |
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* Current dual stream devices have a PCU TX FIFO size of 8 KB. |
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* Current single stream devices have a PCU TX FIFO size of 4 KB, however, |
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* there is a hardware issue which forces us to use 2 KB instead so the |
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* frame trigger level must not exceed 2 KB for these chipsets. |
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*/ |
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bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) |
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{ |
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u32 txcfg, curLevel, newLevel; |
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|
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if (ah->tx_trig_level >= ah->config.max_txtrig_level) |
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return false; |
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ath9k_hw_disable_interrupts(ah); |
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txcfg = REG_READ(ah, AR_TXCFG); |
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curLevel = MS(txcfg, AR_FTRIG); |
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newLevel = curLevel; |
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if (bIncTrigLevel) { |
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if (curLevel < ah->config.max_txtrig_level) |
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newLevel++; |
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} else if (curLevel > MIN_TX_FIFO_THRESHOLD) |
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newLevel--; |
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if (newLevel != curLevel) |
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REG_WRITE(ah, AR_TXCFG, |
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(txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG)); |
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ath9k_hw_enable_interrupts(ah); |
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ah->tx_trig_level = newLevel; |
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return newLevel != curLevel; |
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} |
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EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel); |
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void ath9k_hw_abort_tx_dma(struct ath_hw *ah) |
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{ |
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int maxdelay = 1000; |
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int i, q; |
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|
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if (ah->curchan) { |
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if (IS_CHAN_HALF_RATE(ah->curchan)) |
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maxdelay *= 2; |
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else if (IS_CHAN_QUARTER_RATE(ah->curchan)) |
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maxdelay *= 4; |
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} |
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REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); |
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REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); |
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REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); |
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REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); |
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for (q = 0; q < AR_NUM_QCU; q++) { |
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for (i = 0; i < maxdelay; i++) { |
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if (i) |
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udelay(5); |
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if (!ath9k_hw_numtxpending(ah, q)) |
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break; |
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} |
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} |
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REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); |
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REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); |
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REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); |
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REG_WRITE(ah, AR_Q_TXD, 0); |
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} |
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EXPORT_SYMBOL(ath9k_hw_abort_tx_dma); |
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bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q) |
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{ |
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#define ATH9K_TX_STOP_DMA_TIMEOUT 1000 /* usec */ |
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#define ATH9K_TIME_QUANTUM 100 /* usec */ |
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int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; |
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int wait; |
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REG_WRITE(ah, AR_Q_TXD, 1 << q); |
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for (wait = wait_time; wait != 0; wait--) { |
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if (wait != wait_time) |
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udelay(ATH9K_TIME_QUANTUM); |
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if (ath9k_hw_numtxpending(ah, q) == 0) |
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break; |
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} |
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REG_WRITE(ah, AR_Q_TXD, 0); |
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return wait != 0; |
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#undef ATH9K_TX_STOP_DMA_TIMEOUT |
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#undef ATH9K_TIME_QUANTUM |
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} |
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EXPORT_SYMBOL(ath9k_hw_stop_dma_queue); |
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bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, |
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const struct ath9k_tx_queue_info *qinfo) |
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{ |
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u32 cw; |
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struct ath_common *common = ath9k_hw_common(ah); |
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struct ath9k_tx_queue_info *qi; |
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|
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qi = &ah->txq[q]; |
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if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
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ath_dbg(common, QUEUE, |
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"Set TXQ properties, inactive queue: %u\n", q); |
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return false; |
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} |
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ath_dbg(common, QUEUE, "Set queue properties for: %u\n", q); |
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|
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qi->tqi_ver = qinfo->tqi_ver; |
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qi->tqi_subtype = qinfo->tqi_subtype; |
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qi->tqi_qflags = qinfo->tqi_qflags; |
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qi->tqi_priority = qinfo->tqi_priority; |
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if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT) |
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qi->tqi_aifs = min(qinfo->tqi_aifs, 255U); |
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else |
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qi->tqi_aifs = INIT_AIFS; |
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if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) { |
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cw = min(qinfo->tqi_cwmin, 1024U); |
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qi->tqi_cwmin = 1; |
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while (qi->tqi_cwmin < cw) |
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qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1; |
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} else |
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qi->tqi_cwmin = qinfo->tqi_cwmin; |
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if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) { |
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cw = min(qinfo->tqi_cwmax, 1024U); |
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qi->tqi_cwmax = 1; |
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while (qi->tqi_cwmax < cw) |
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qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1; |
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} else |
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qi->tqi_cwmax = INIT_CWMAX; |
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if (qinfo->tqi_shretry != 0) |
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qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U); |
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else |
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qi->tqi_shretry = INIT_SH_RETRY; |
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if (qinfo->tqi_lgretry != 0) |
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qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U); |
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else |
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qi->tqi_lgretry = INIT_LG_RETRY; |
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qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod; |
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qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit; |
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qi->tqi_burstTime = qinfo->tqi_burstTime; |
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qi->tqi_readyTime = qinfo->tqi_readyTime; |
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|
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switch (qinfo->tqi_subtype) { |
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case ATH9K_WME_UPSD: |
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if (qi->tqi_type == ATH9K_TX_QUEUE_DATA) |
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qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS; |
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break; |
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default: |
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break; |
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} |
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return true; |
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} |
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EXPORT_SYMBOL(ath9k_hw_set_txq_props); |
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bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, |
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struct ath9k_tx_queue_info *qinfo) |
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{ |
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struct ath_common *common = ath9k_hw_common(ah); |
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struct ath9k_tx_queue_info *qi; |
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|
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qi = &ah->txq[q]; |
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if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
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ath_dbg(common, QUEUE, |
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"Get TXQ properties, inactive queue: %u\n", q); |
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return false; |
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} |
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qinfo->tqi_qflags = qi->tqi_qflags; |
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qinfo->tqi_ver = qi->tqi_ver; |
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qinfo->tqi_subtype = qi->tqi_subtype; |
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qinfo->tqi_qflags = qi->tqi_qflags; |
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qinfo->tqi_priority = qi->tqi_priority; |
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qinfo->tqi_aifs = qi->tqi_aifs; |
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qinfo->tqi_cwmin = qi->tqi_cwmin; |
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qinfo->tqi_cwmax = qi->tqi_cwmax; |
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qinfo->tqi_shretry = qi->tqi_shretry; |
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qinfo->tqi_lgretry = qi->tqi_lgretry; |
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qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod; |
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qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit; |
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qinfo->tqi_burstTime = qi->tqi_burstTime; |
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qinfo->tqi_readyTime = qi->tqi_readyTime; |
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return true; |
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} |
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EXPORT_SYMBOL(ath9k_hw_get_txq_props); |
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int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, |
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const struct ath9k_tx_queue_info *qinfo) |
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{ |
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struct ath_common *common = ath9k_hw_common(ah); |
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struct ath9k_tx_queue_info *qi; |
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int q; |
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switch (type) { |
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case ATH9K_TX_QUEUE_BEACON: |
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q = ATH9K_NUM_TX_QUEUES - 1; |
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break; |
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case ATH9K_TX_QUEUE_CAB: |
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q = ATH9K_NUM_TX_QUEUES - 2; |
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break; |
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case ATH9K_TX_QUEUE_PSPOLL: |
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q = 1; |
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break; |
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case ATH9K_TX_QUEUE_UAPSD: |
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q = ATH9K_NUM_TX_QUEUES - 3; |
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break; |
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case ATH9K_TX_QUEUE_DATA: |
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q = qinfo->tqi_subtype; |
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break; |
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default: |
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ath_err(common, "Invalid TX queue type: %u\n", type); |
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return -1; |
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} |
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ath_dbg(common, QUEUE, "Setup TX queue: %u\n", q); |
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qi = &ah->txq[q]; |
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if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { |
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ath_err(common, "TX queue: %u already active\n", q); |
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return -1; |
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} |
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memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); |
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qi->tqi_type = type; |
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qi->tqi_physCompBuf = qinfo->tqi_physCompBuf; |
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(void) ath9k_hw_set_txq_props(ah, q, qinfo); |
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|
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return q; |
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} |
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EXPORT_SYMBOL(ath9k_hw_setuptxqueue); |
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static void ath9k_hw_clear_queue_interrupts(struct ath_hw *ah, u32 q) |
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{ |
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ah->txok_interrupt_mask &= ~(1 << q); |
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ah->txerr_interrupt_mask &= ~(1 << q); |
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ah->txdesc_interrupt_mask &= ~(1 << q); |
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ah->txeol_interrupt_mask &= ~(1 << q); |
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ah->txurn_interrupt_mask &= ~(1 << q); |
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} |
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bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) |
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{ |
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struct ath_common *common = ath9k_hw_common(ah); |
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struct ath9k_tx_queue_info *qi; |
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|
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qi = &ah->txq[q]; |
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if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
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ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q); |
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return false; |
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} |
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ath_dbg(common, QUEUE, "Release TX queue: %u\n", q); |
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qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; |
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ath9k_hw_clear_queue_interrupts(ah, q); |
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ath9k_hw_set_txq_interrupts(ah, qi); |
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|
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return true; |
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} |
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EXPORT_SYMBOL(ath9k_hw_releasetxqueue); |
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bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) |
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{ |
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struct ath_common *common = ath9k_hw_common(ah); |
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struct ath9k_tx_queue_info *qi; |
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u32 cwMin, chanCwMin, value; |
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|
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qi = &ah->txq[q]; |
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if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { |
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ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q); |
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return true; |
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} |
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|
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ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q); |
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|
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if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { |
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chanCwMin = INIT_CWMIN; |
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|
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for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1); |
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} else |
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cwMin = qi->tqi_cwmin; |
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|
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ENABLE_REGWRITE_BUFFER(ah); |
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|
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REG_WRITE(ah, AR_DLCL_IFS(q), |
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SM(cwMin, AR_D_LCL_IFS_CWMIN) | |
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SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | |
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SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); |
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|
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REG_WRITE(ah, AR_DRETRY_LIMIT(q), |
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SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) | |
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SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) | |
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SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)); |
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|
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REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ); |
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|
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if (AR_SREV_9340(ah) && !AR_SREV_9340_13_OR_LATER(ah)) |
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REG_WRITE(ah, AR_DMISC(q), |
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AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1); |
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else |
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REG_WRITE(ah, AR_DMISC(q), |
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AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2); |
|
|
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if (qi->tqi_cbrPeriod) { |
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REG_WRITE(ah, AR_QCBRCFG(q), |
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SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) | |
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SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH)); |
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REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR | |
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(qi->tqi_cbrOverflowLimit ? |
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AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0)); |
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} |
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if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) { |
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REG_WRITE(ah, AR_QRDYTIMECFG(q), |
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SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) | |
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AR_Q_RDYTIMECFG_EN); |
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} |
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|
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REG_WRITE(ah, AR_DCHNTIME(q), |
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SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | |
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(qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); |
|
|
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if (qi->tqi_burstTime |
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&& (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) |
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REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY); |
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|
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if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) |
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REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); |
|
|
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REGWRITE_BUFFER_FLUSH(ah); |
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|
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if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) |
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REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN); |
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|
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switch (qi->tqi_type) { |
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case ATH9K_TX_QUEUE_BEACON: |
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ENABLE_REGWRITE_BUFFER(ah); |
|
|
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REG_SET_BIT(ah, AR_QMISC(q), |
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AR_Q_MISC_FSP_DBA_GATED |
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| AR_Q_MISC_BEACON_USE |
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| AR_Q_MISC_CBR_INCR_DIS1); |
|
|
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REG_SET_BIT(ah, AR_DMISC(q), |
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(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << |
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AR_D_MISC_ARB_LOCKOUT_CNTRL_S) |
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| AR_D_MISC_BEACON_USE |
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| AR_D_MISC_POST_FR_BKOFF_DIS); |
|
|
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REGWRITE_BUFFER_FLUSH(ah); |
|
|
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/* |
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* cwmin and cwmax should be 0 for beacon queue |
|
* but not for IBSS as we would create an imbalance |
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* on beaconing fairness for participating nodes. |
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*/ |
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if (AR_SREV_9300_20_OR_LATER(ah) && |
|
ah->opmode != NL80211_IFTYPE_ADHOC) { |
|
REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN) |
|
| SM(0, AR_D_LCL_IFS_CWMAX) |
|
| SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); |
|
} |
|
break; |
|
case ATH9K_TX_QUEUE_CAB: |
|
ENABLE_REGWRITE_BUFFER(ah); |
|
|
|
REG_SET_BIT(ah, AR_QMISC(q), |
|
AR_Q_MISC_FSP_DBA_GATED |
|
| AR_Q_MISC_CBR_INCR_DIS1 |
|
| AR_Q_MISC_CBR_INCR_DIS0); |
|
value = (qi->tqi_readyTime - |
|
(ah->config.sw_beacon_response_time - |
|
ah->config.dma_beacon_response_time)) * 1024; |
|
REG_WRITE(ah, AR_QRDYTIMECFG(q), |
|
value | AR_Q_RDYTIMECFG_EN); |
|
REG_SET_BIT(ah, AR_DMISC(q), |
|
(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << |
|
AR_D_MISC_ARB_LOCKOUT_CNTRL_S)); |
|
|
|
REGWRITE_BUFFER_FLUSH(ah); |
|
|
|
break; |
|
case ATH9K_TX_QUEUE_PSPOLL: |
|
REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1); |
|
break; |
|
case ATH9K_TX_QUEUE_UAPSD: |
|
REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); |
|
break; |
|
default: |
|
break; |
|
} |
|
|
|
if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) { |
|
REG_SET_BIT(ah, AR_DMISC(q), |
|
SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, |
|
AR_D_MISC_ARB_LOCKOUT_CNTRL) | |
|
AR_D_MISC_POST_FR_BKOFF_DIS); |
|
} |
|
|
|
if (AR_SREV_9300_20_OR_LATER(ah)) |
|
REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN); |
|
|
|
ath9k_hw_clear_queue_interrupts(ah, q); |
|
if (qi->tqi_qflags & TXQ_FLAG_TXINT_ENABLE) { |
|
ah->txok_interrupt_mask |= 1 << q; |
|
ah->txerr_interrupt_mask |= 1 << q; |
|
} |
|
if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) |
|
ah->txdesc_interrupt_mask |= 1 << q; |
|
if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) |
|
ah->txeol_interrupt_mask |= 1 << q; |
|
if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) |
|
ah->txurn_interrupt_mask |= 1 << q; |
|
ath9k_hw_set_txq_interrupts(ah, qi); |
|
|
|
return true; |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_resettxqueue); |
|
|
|
int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, |
|
struct ath_rx_status *rs) |
|
{ |
|
struct ar5416_desc ads; |
|
struct ar5416_desc *adsp = AR5416DESC(ds); |
|
u32 phyerr; |
|
|
|
if ((adsp->ds_rxstatus8 & AR_RxDone) == 0) |
|
return -EINPROGRESS; |
|
|
|
ads.u.rx = adsp->u.rx; |
|
|
|
rs->rs_status = 0; |
|
rs->rs_flags = 0; |
|
rs->enc_flags = 0; |
|
rs->bw = RATE_INFO_BW_20; |
|
|
|
rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen; |
|
rs->rs_tstamp = ads.AR_RcvTimestamp; |
|
|
|
if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) { |
|
rs->rs_rssi = ATH9K_RSSI_BAD; |
|
rs->rs_rssi_ctl[0] = ATH9K_RSSI_BAD; |
|
rs->rs_rssi_ctl[1] = ATH9K_RSSI_BAD; |
|
rs->rs_rssi_ctl[2] = ATH9K_RSSI_BAD; |
|
rs->rs_rssi_ext[0] = ATH9K_RSSI_BAD; |
|
rs->rs_rssi_ext[1] = ATH9K_RSSI_BAD; |
|
rs->rs_rssi_ext[2] = ATH9K_RSSI_BAD; |
|
} else { |
|
rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined); |
|
rs->rs_rssi_ctl[0] = MS(ads.ds_rxstatus0, |
|
AR_RxRSSIAnt00); |
|
rs->rs_rssi_ctl[1] = MS(ads.ds_rxstatus0, |
|
AR_RxRSSIAnt01); |
|
rs->rs_rssi_ctl[2] = MS(ads.ds_rxstatus0, |
|
AR_RxRSSIAnt02); |
|
rs->rs_rssi_ext[0] = MS(ads.ds_rxstatus4, |
|
AR_RxRSSIAnt10); |
|
rs->rs_rssi_ext[1] = MS(ads.ds_rxstatus4, |
|
AR_RxRSSIAnt11); |
|
rs->rs_rssi_ext[2] = MS(ads.ds_rxstatus4, |
|
AR_RxRSSIAnt12); |
|
} |
|
if (ads.ds_rxstatus8 & AR_RxKeyIdxValid) |
|
rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx); |
|
else |
|
rs->rs_keyix = ATH9K_RXKEYIX_INVALID; |
|
|
|
rs->rs_rate = MS(ads.ds_rxstatus0, AR_RxRate); |
|
rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0; |
|
|
|
rs->rs_firstaggr = (ads.ds_rxstatus8 & AR_RxFirstAggr) ? 1 : 0; |
|
rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0; |
|
rs->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; |
|
rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna); |
|
|
|
/* directly mapped flags for ieee80211_rx_status */ |
|
rs->enc_flags |= |
|
(ads.ds_rxstatus3 & AR_GI) ? RX_ENC_FLAG_SHORT_GI : 0; |
|
rs->bw = (ads.ds_rxstatus3 & AR_2040) ? RATE_INFO_BW_40 : |
|
RATE_INFO_BW_20; |
|
if (AR_SREV_9280_20_OR_LATER(ah)) |
|
rs->enc_flags |= |
|
(ads.ds_rxstatus3 & AR_STBC) ? |
|
/* we can only Nss=1 STBC */ |
|
(1 << RX_ENC_FLAG_STBC_SHIFT) : 0; |
|
|
|
if (ads.ds_rxstatus8 & AR_PreDelimCRCErr) |
|
rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE; |
|
if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) |
|
rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST; |
|
if (ads.ds_rxstatus8 & AR_DecryptBusyErr) |
|
rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY; |
|
|
|
if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) { |
|
/* |
|
* Treat these errors as mutually exclusive to avoid spurious |
|
* extra error reports from the hardware. If a CRC error is |
|
* reported, then decryption and MIC errors are irrelevant, |
|
* the frame is going to be dropped either way |
|
*/ |
|
if (ads.ds_rxstatus8 & AR_PHYErr) { |
|
rs->rs_status |= ATH9K_RXERR_PHY; |
|
phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode); |
|
rs->rs_phyerr = phyerr; |
|
} else if (ads.ds_rxstatus8 & AR_CRCErr) |
|
rs->rs_status |= ATH9K_RXERR_CRC; |
|
else if (ads.ds_rxstatus8 & AR_DecryptCRCErr) |
|
rs->rs_status |= ATH9K_RXERR_DECRYPT; |
|
else if (ads.ds_rxstatus8 & AR_MichaelErr) |
|
rs->rs_status |= ATH9K_RXERR_MIC; |
|
} else { |
|
if (ads.ds_rxstatus8 & |
|
(AR_CRCErr | AR_PHYErr | AR_DecryptCRCErr | AR_MichaelErr)) |
|
rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC; |
|
|
|
/* Only up to MCS16 supported, everything above is invalid */ |
|
if (rs->rs_rate >= 0x90) |
|
rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC; |
|
} |
|
|
|
if (ads.ds_rxstatus8 & AR_KeyMiss) |
|
rs->rs_status |= ATH9K_RXERR_KEYMISS; |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_rxprocdesc); |
|
|
|
/* |
|
* This can stop or re-enables RX. |
|
* |
|
* If bool is set this will kill any frame which is currently being |
|
* transferred between the MAC and baseband and also prevent any new |
|
* frames from getting started. |
|
*/ |
|
bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) |
|
{ |
|
u32 reg; |
|
|
|
if (set) { |
|
REG_SET_BIT(ah, AR_DIAG_SW, |
|
(AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); |
|
|
|
if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, |
|
0, AH_WAIT_TIMEOUT)) { |
|
REG_CLR_BIT(ah, AR_DIAG_SW, |
|
(AR_DIAG_RX_DIS | |
|
AR_DIAG_RX_ABORT)); |
|
|
|
reg = REG_READ(ah, AR_OBS_BUS_1); |
|
ath_err(ath9k_hw_common(ah), |
|
"RX failed to go idle in 10 ms RXSM=0x%x\n", |
|
reg); |
|
|
|
return false; |
|
} |
|
} else { |
|
REG_CLR_BIT(ah, AR_DIAG_SW, |
|
(AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); |
|
} |
|
|
|
return true; |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_setrxabort); |
|
|
|
void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp) |
|
{ |
|
REG_WRITE(ah, AR_RXDP, rxdp); |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_putrxbuf); |
|
|
|
void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning) |
|
{ |
|
ath9k_enable_mib_counters(ah); |
|
|
|
ath9k_ani_reset(ah, is_scanning); |
|
|
|
REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_startpcureceive); |
|
|
|
void ath9k_hw_abortpcurecv(struct ath_hw *ah) |
|
{ |
|
REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS); |
|
|
|
ath9k_hw_disable_mib_counters(ah); |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_abortpcurecv); |
|
|
|
bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset) |
|
{ |
|
#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */ |
|
struct ath_common *common = ath9k_hw_common(ah); |
|
u32 mac_status, last_mac_status = 0; |
|
int i; |
|
|
|
/* Enable access to the DMA observation bus */ |
|
REG_WRITE(ah, AR_MACMISC, |
|
((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | |
|
(AR_MACMISC_MISC_OBS_BUS_1 << |
|
AR_MACMISC_MISC_OBS_BUS_MSB_S))); |
|
|
|
REG_WRITE(ah, AR_CR, AR_CR_RXD); |
|
|
|
/* Wait for rx enable bit to go low */ |
|
for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) { |
|
if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) |
|
break; |
|
|
|
if (!AR_SREV_9300_20_OR_LATER(ah)) { |
|
mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; |
|
if (mac_status == 0x1c0 && mac_status == last_mac_status) { |
|
*reset = true; |
|
break; |
|
} |
|
|
|
last_mac_status = mac_status; |
|
} |
|
|
|
udelay(AH_TIME_QUANTUM); |
|
} |
|
|
|
if (i == 0) { |
|
ath_err(common, |
|
"DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n", |
|
AH_RX_STOP_DMA_TIMEOUT / 1000, |
|
REG_READ(ah, AR_CR), |
|
REG_READ(ah, AR_DIAG_SW), |
|
REG_READ(ah, AR_DMADBG_7)); |
|
return false; |
|
} else { |
|
return true; |
|
} |
|
|
|
#undef AH_RX_STOP_DMA_TIMEOUT |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_stopdmarecv); |
|
|
|
int ath9k_hw_beaconq_setup(struct ath_hw *ah) |
|
{ |
|
struct ath9k_tx_queue_info qi; |
|
|
|
memset(&qi, 0, sizeof(qi)); |
|
qi.tqi_aifs = 1; |
|
qi.tqi_cwmin = 0; |
|
qi.tqi_cwmax = 0; |
|
|
|
if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
|
qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; |
|
|
|
return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi); |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_beaconq_setup); |
|
|
|
bool ath9k_hw_intrpend(struct ath_hw *ah) |
|
{ |
|
u32 host_isr; |
|
|
|
if (AR_SREV_9100(ah)) |
|
return true; |
|
|
|
host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); |
|
|
|
if (((host_isr & AR_INTR_MAC_IRQ) || |
|
(host_isr & AR_INTR_ASYNC_MASK_MCI)) && |
|
(host_isr != AR_INTR_SPURIOUS)) |
|
return true; |
|
|
|
host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); |
|
if ((host_isr & AR_INTR_SYNC_DEFAULT) |
|
&& (host_isr != AR_INTR_SPURIOUS)) |
|
return true; |
|
|
|
return false; |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_intrpend); |
|
|
|
void ath9k_hw_kill_interrupts(struct ath_hw *ah) |
|
{ |
|
struct ath_common *common = ath9k_hw_common(ah); |
|
|
|
ath_dbg(common, INTERRUPT, "disable IER\n"); |
|
REG_WRITE(ah, AR_IER, AR_IER_DISABLE); |
|
(void) REG_READ(ah, AR_IER); |
|
if (!AR_SREV_9100(ah)) { |
|
REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); |
|
(void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); |
|
|
|
REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
|
(void) REG_READ(ah, AR_INTR_SYNC_ENABLE); |
|
} |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_kill_interrupts); |
|
|
|
void ath9k_hw_disable_interrupts(struct ath_hw *ah) |
|
{ |
|
if (!(ah->imask & ATH9K_INT_GLOBAL)) |
|
atomic_set(&ah->intr_ref_cnt, -1); |
|
else |
|
atomic_dec(&ah->intr_ref_cnt); |
|
|
|
ath9k_hw_kill_interrupts(ah); |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_disable_interrupts); |
|
|
|
static void __ath9k_hw_enable_interrupts(struct ath_hw *ah) |
|
{ |
|
struct ath_common *common = ath9k_hw_common(ah); |
|
u32 sync_default = AR_INTR_SYNC_DEFAULT; |
|
u32 async_mask; |
|
|
|
if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || |
|
AR_SREV_9561(ah)) |
|
sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; |
|
|
|
async_mask = AR_INTR_MAC_IRQ; |
|
|
|
if (ah->imask & ATH9K_INT_MCI) |
|
async_mask |= AR_INTR_ASYNC_MASK_MCI; |
|
|
|
ath_dbg(common, INTERRUPT, "enable IER\n"); |
|
REG_WRITE(ah, AR_IER, AR_IER_ENABLE); |
|
if (!AR_SREV_9100(ah)) { |
|
REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask); |
|
REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask); |
|
|
|
REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); |
|
REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default); |
|
} |
|
ath_dbg(common, INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", |
|
REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); |
|
|
|
if (ah->msi_enabled) { |
|
u32 _msi_reg = 0; |
|
u32 i = 0; |
|
u32 msi_pend_addr_mask = AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64; |
|
|
|
ath_dbg(ath9k_hw_common(ah), INTERRUPT, |
|
"Enabling MSI, msi_mask=0x%X\n", ah->msi_mask); |
|
|
|
REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, ah->msi_mask); |
|
REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, ah->msi_mask); |
|
ath_dbg(ath9k_hw_common(ah), INTERRUPT, |
|
"AR_INTR_PRIO_ASYNC_ENABLE=0x%X, AR_INTR_PRIO_ASYNC_MASK=0x%X\n", |
|
REG_READ(ah, AR_INTR_PRIO_ASYNC_ENABLE), |
|
REG_READ(ah, AR_INTR_PRIO_ASYNC_MASK)); |
|
|
|
if (ah->msi_reg == 0) |
|
ah->msi_reg = REG_READ(ah, AR_PCIE_MSI); |
|
|
|
ath_dbg(ath9k_hw_common(ah), INTERRUPT, |
|
"AR_PCIE_MSI=0x%X, ah->msi_reg = 0x%X\n", |
|
AR_PCIE_MSI, ah->msi_reg); |
|
|
|
i = 0; |
|
do { |
|
REG_WRITE(ah, AR_PCIE_MSI, |
|
(ah->msi_reg | AR_PCIE_MSI_ENABLE) |
|
& msi_pend_addr_mask); |
|
_msi_reg = REG_READ(ah, AR_PCIE_MSI); |
|
i++; |
|
} while ((_msi_reg & AR_PCIE_MSI_ENABLE) == 0 && i < 200); |
|
|
|
if (i >= 200) |
|
ath_err(ath9k_hw_common(ah), |
|
"%s: _msi_reg = 0x%X\n", |
|
__func__, _msi_reg); |
|
} |
|
} |
|
|
|
void ath9k_hw_resume_interrupts(struct ath_hw *ah) |
|
{ |
|
struct ath_common *common = ath9k_hw_common(ah); |
|
|
|
if (!(ah->imask & ATH9K_INT_GLOBAL)) |
|
return; |
|
|
|
if (atomic_read(&ah->intr_ref_cnt) != 0) { |
|
ath_dbg(common, INTERRUPT, "Do not enable IER ref count %d\n", |
|
atomic_read(&ah->intr_ref_cnt)); |
|
return; |
|
} |
|
|
|
__ath9k_hw_enable_interrupts(ah); |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_resume_interrupts); |
|
|
|
void ath9k_hw_enable_interrupts(struct ath_hw *ah) |
|
{ |
|
struct ath_common *common = ath9k_hw_common(ah); |
|
|
|
if (!(ah->imask & ATH9K_INT_GLOBAL)) |
|
return; |
|
|
|
if (!atomic_inc_and_test(&ah->intr_ref_cnt)) { |
|
ath_dbg(common, INTERRUPT, "Do not enable IER ref count %d\n", |
|
atomic_read(&ah->intr_ref_cnt)); |
|
return; |
|
} |
|
|
|
__ath9k_hw_enable_interrupts(ah); |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_enable_interrupts); |
|
|
|
void ath9k_hw_set_interrupts(struct ath_hw *ah) |
|
{ |
|
enum ath9k_int ints = ah->imask; |
|
u32 mask, mask2; |
|
struct ath9k_hw_capabilities *pCap = &ah->caps; |
|
struct ath_common *common = ath9k_hw_common(ah); |
|
|
|
if (!(ints & ATH9K_INT_GLOBAL)) |
|
ath9k_hw_disable_interrupts(ah); |
|
|
|
if (ah->msi_enabled) { |
|
ath_dbg(common, INTERRUPT, "Clearing AR_INTR_PRIO_ASYNC_ENABLE\n"); |
|
|
|
REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); |
|
REG_READ(ah, AR_INTR_PRIO_ASYNC_ENABLE); |
|
} |
|
|
|
ath_dbg(common, INTERRUPT, "New interrupt mask 0x%x\n", ints); |
|
|
|
mask = ints & ATH9K_INT_COMMON; |
|
mask2 = 0; |
|
|
|
ah->msi_mask = 0; |
|
if (ints & ATH9K_INT_TX) { |
|
ah->msi_mask |= AR_INTR_PRIO_TX; |
|
if (ah->config.tx_intr_mitigation) |
|
mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM; |
|
else { |
|
if (ah->txok_interrupt_mask) |
|
mask |= AR_IMR_TXOK; |
|
if (ah->txdesc_interrupt_mask) |
|
mask |= AR_IMR_TXDESC; |
|
} |
|
if (ah->txerr_interrupt_mask) |
|
mask |= AR_IMR_TXERR; |
|
if (ah->txeol_interrupt_mask) |
|
mask |= AR_IMR_TXEOL; |
|
} |
|
if (ints & ATH9K_INT_RX) { |
|
ah->msi_mask |= AR_INTR_PRIO_RXLP | AR_INTR_PRIO_RXHP; |
|
if (AR_SREV_9300_20_OR_LATER(ah)) { |
|
mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP; |
|
if (ah->config.rx_intr_mitigation) { |
|
mask &= ~AR_IMR_RXOK_LP; |
|
mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; |
|
} else { |
|
mask |= AR_IMR_RXOK_LP; |
|
} |
|
} else { |
|
if (ah->config.rx_intr_mitigation) |
|
mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; |
|
else |
|
mask |= AR_IMR_RXOK | AR_IMR_RXDESC; |
|
} |
|
if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
|
mask |= AR_IMR_GENTMR; |
|
} |
|
|
|
if (ints & ATH9K_INT_GENTIMER) |
|
mask |= AR_IMR_GENTMR; |
|
|
|
if (ints & (ATH9K_INT_BMISC)) { |
|
mask |= AR_IMR_BCNMISC; |
|
if (ints & ATH9K_INT_TIM) |
|
mask2 |= AR_IMR_S2_TIM; |
|
if (ints & ATH9K_INT_DTIM) |
|
mask2 |= AR_IMR_S2_DTIM; |
|
if (ints & ATH9K_INT_DTIMSYNC) |
|
mask2 |= AR_IMR_S2_DTIMSYNC; |
|
if (ints & ATH9K_INT_CABEND) |
|
mask2 |= AR_IMR_S2_CABEND; |
|
if (ints & ATH9K_INT_TSFOOR) |
|
mask2 |= AR_IMR_S2_TSFOOR; |
|
} |
|
|
|
if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { |
|
mask |= AR_IMR_BCNMISC; |
|
if (ints & ATH9K_INT_GTT) |
|
mask2 |= AR_IMR_S2_GTT; |
|
if (ints & ATH9K_INT_CST) |
|
mask2 |= AR_IMR_S2_CST; |
|
} |
|
|
|
if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) { |
|
if (ints & ATH9K_INT_BB_WATCHDOG) { |
|
mask |= AR_IMR_BCNMISC; |
|
mask2 |= AR_IMR_S2_BB_WATCHDOG; |
|
} |
|
} |
|
|
|
ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask); |
|
REG_WRITE(ah, AR_IMR, mask); |
|
ah->imrs2_reg &= ~(AR_IMR_S2_TIM | |
|
AR_IMR_S2_DTIM | |
|
AR_IMR_S2_DTIMSYNC | |
|
AR_IMR_S2_CABEND | |
|
AR_IMR_S2_CABTO | |
|
AR_IMR_S2_TSFOOR | |
|
AR_IMR_S2_GTT | |
|
AR_IMR_S2_CST); |
|
|
|
if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) { |
|
if (ints & ATH9K_INT_BB_WATCHDOG) |
|
ah->imrs2_reg &= ~AR_IMR_S2_BB_WATCHDOG; |
|
} |
|
|
|
ah->imrs2_reg |= mask2; |
|
REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); |
|
|
|
if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
|
if (ints & ATH9K_INT_TIM_TIMER) |
|
REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); |
|
else |
|
REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); |
|
} |
|
|
|
return; |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_set_interrupts); |
|
|
|
#define ATH9K_HW_MAX_DCU 10 |
|
#define ATH9K_HW_SLICE_PER_DCU 16 |
|
#define ATH9K_HW_BIT_IN_SLICE 16 |
|
void ath9k_hw_set_tx_filter(struct ath_hw *ah, u8 destidx, bool set) |
|
{ |
|
int dcu_idx; |
|
u32 filter; |
|
|
|
for (dcu_idx = 0; dcu_idx < 10; dcu_idx++) { |
|
filter = SM(set, AR_D_TXBLK_WRITE_COMMAND); |
|
filter |= SM(dcu_idx, AR_D_TXBLK_WRITE_DCU); |
|
filter |= SM((destidx / ATH9K_HW_SLICE_PER_DCU), |
|
AR_D_TXBLK_WRITE_SLICE); |
|
filter |= BIT(destidx % ATH9K_HW_BIT_IN_SLICE); |
|
ath_dbg(ath9k_hw_common(ah), PS, |
|
"DCU%d staid %d set %d txfilter %08x\n", |
|
dcu_idx, destidx, set, filter); |
|
REG_WRITE(ah, AR_D_TXBLK_BASE, filter); |
|
} |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_set_tx_filter);
|
|
|