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64 lines
2.5 KiB
64 lines
2.5 KiB
/* |
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* Copyright (c) 2010-2011 Atheros Communications Inc. |
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* Copyright (c) 2011-2012 Qualcomm Atheros Inc. |
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* |
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* Permission to use, copy, modify, and/or distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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*/ |
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#ifndef INITVALS_9565_1P1_H |
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#define INITVALS_9565_1P1_H |
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/* AR9565 1.1 */ |
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#define ar9565_1p1_mac_core ar9565_1p0_mac_core |
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#define ar9565_1p1_mac_postamble ar9565_1p0_mac_postamble |
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#define ar9565_1p1_baseband_core ar9565_1p0_baseband_core |
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#define ar9565_1p1_baseband_postamble ar9565_1p0_baseband_postamble |
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#define ar9565_1p1_radio_core ar9565_1p0_radio_core |
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#define ar9565_1p1_soc_preamble ar9565_1p0_soc_preamble |
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#define ar9565_1p1_soc_postamble ar9565_1p0_soc_postamble |
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#define ar9565_1p1_Common_rx_gain_table ar9565_1p0_Common_rx_gain_table |
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#define ar9565_1p1_Modes_lowest_ob_db_tx_gain_table ar9565_1p0_Modes_lowest_ob_db_tx_gain_table |
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#define ar9565_1p1_pciephy_clkreq_disable_L1 ar9565_1p0_pciephy_clkreq_disable_L1 |
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#define ar9565_1p1_modes_fast_clock ar9565_1p0_modes_fast_clock |
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#define ar9565_1p1_common_wo_xlna_rx_gain_table ar9565_1p0_common_wo_xlna_rx_gain_table |
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#define ar9565_1p1_modes_low_ob_db_tx_gain_table ar9565_1p0_modes_low_ob_db_tx_gain_table |
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#define ar9565_1p1_modes_high_ob_db_tx_gain_table ar9565_1p0_modes_high_ob_db_tx_gain_table |
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#define ar9565_1p1_modes_high_power_tx_gain_table ar9565_1p0_modes_high_power_tx_gain_table |
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#define ar9565_1p1_baseband_core_txfir_coeff_japan_2484 ar9565_1p0_baseband_core_txfir_coeff_japan_2484 |
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static const u32 ar9565_1p1_radio_postamble[][5] = { |
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/* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ |
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{0x0001609c, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524, 0x0b8ee524}, |
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{0x000160ac, 0xa4646c08, 0xa4646c08, 0x24645808, 0x24645808}, |
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{0x000160b0, 0x01d67f70, 0x01d67f70, 0x01d67f70, 0x01d67f70}, |
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{0x0001610c, 0x40000000, 0x40000000, 0x40000000, 0x40000000}, |
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{0x00016140, 0x10804008, 0x10804008, 0x50804008, 0x50804008}, |
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}; |
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#endif /* INITVALS_9565_1P1_H */
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