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619 lines
17 KiB
619 lines
17 KiB
/* |
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* Copyright (c) 2010-2011 Atheros Communications Inc. |
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* |
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* Permission to use, copy, modify, and/or distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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*/ |
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#include <linux/export.h> |
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#include "hw.h" |
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#include "ar9003_mac.h" |
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#include "ar9003_mci.h" |
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|
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static void ar9003_hw_rx_enable(struct ath_hw *hw) |
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{ |
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REG_WRITE(hw, AR_CR, 0); |
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} |
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|
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static void |
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ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i) |
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{ |
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struct ar9003_txc *ads = ds; |
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int checksum = 0; |
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u32 val, ctl12, ctl17; |
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u8 desc_len; |
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desc_len = ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x18 : 0x17); |
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val = (ATHEROS_VENDOR_ID << AR_DescId_S) | |
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(1 << AR_TxRxDesc_S) | |
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(1 << AR_CtrlStat_S) | |
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(i->qcu << AR_TxQcuNum_S) | desc_len; |
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checksum += val; |
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WRITE_ONCE(ads->info, val); |
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|
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checksum += i->link; |
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WRITE_ONCE(ads->link, i->link); |
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|
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checksum += i->buf_addr[0]; |
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WRITE_ONCE(ads->data0, i->buf_addr[0]); |
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checksum += i->buf_addr[1]; |
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WRITE_ONCE(ads->data1, i->buf_addr[1]); |
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checksum += i->buf_addr[2]; |
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WRITE_ONCE(ads->data2, i->buf_addr[2]); |
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checksum += i->buf_addr[3]; |
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WRITE_ONCE(ads->data3, i->buf_addr[3]); |
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|
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checksum += (val = (i->buf_len[0] << AR_BufLen_S) & AR_BufLen); |
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WRITE_ONCE(ads->ctl3, val); |
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checksum += (val = (i->buf_len[1] << AR_BufLen_S) & AR_BufLen); |
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WRITE_ONCE(ads->ctl5, val); |
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checksum += (val = (i->buf_len[2] << AR_BufLen_S) & AR_BufLen); |
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WRITE_ONCE(ads->ctl7, val); |
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checksum += (val = (i->buf_len[3] << AR_BufLen_S) & AR_BufLen); |
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WRITE_ONCE(ads->ctl9, val); |
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|
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checksum = (u16) (((checksum & 0xffff) + (checksum >> 16)) & 0xffff); |
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WRITE_ONCE(ads->ctl10, checksum); |
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|
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if (i->is_first || i->is_last) { |
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WRITE_ONCE(ads->ctl13, set11nTries(i->rates, 0) |
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| set11nTries(i->rates, 1) |
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| set11nTries(i->rates, 2) |
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| set11nTries(i->rates, 3) |
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| (i->dur_update ? AR_DurUpdateEna : 0) |
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| SM(0, AR_BurstDur)); |
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|
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WRITE_ONCE(ads->ctl14, set11nRate(i->rates, 0) |
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| set11nRate(i->rates, 1) |
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| set11nRate(i->rates, 2) |
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| set11nRate(i->rates, 3)); |
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} else { |
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WRITE_ONCE(ads->ctl13, 0); |
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WRITE_ONCE(ads->ctl14, 0); |
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} |
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|
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ads->ctl20 = 0; |
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ads->ctl21 = 0; |
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ads->ctl22 = 0; |
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ads->ctl23 = 0; |
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|
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ctl17 = SM(i->keytype, AR_EncrType); |
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if (!i->is_first) { |
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WRITE_ONCE(ads->ctl11, 0); |
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WRITE_ONCE(ads->ctl12, i->is_last ? 0 : AR_TxMore); |
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WRITE_ONCE(ads->ctl15, 0); |
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WRITE_ONCE(ads->ctl16, 0); |
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WRITE_ONCE(ads->ctl17, ctl17); |
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WRITE_ONCE(ads->ctl18, 0); |
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WRITE_ONCE(ads->ctl19, 0); |
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return; |
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} |
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WRITE_ONCE(ads->ctl11, (i->pkt_len & AR_FrameLen) |
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| (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0) |
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| SM(i->txpower[0], AR_XmitPower0) |
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| (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0) |
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| (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0) |
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| (i->flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0) |
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| (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) |
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| (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable : |
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(i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0))); |
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|
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ctl12 = (i->keyix != ATH9K_TXKEYIX_INVALID ? |
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SM(i->keyix, AR_DestIdx) : 0) |
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| SM(i->type, AR_FrameType) |
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| (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0) |
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| (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) |
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| (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); |
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|
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ctl17 |= (i->flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0); |
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switch (i->aggr) { |
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case AGGR_BUF_FIRST: |
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ctl17 |= SM(i->aggr_len, AR_AggrLen); |
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fallthrough; |
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case AGGR_BUF_MIDDLE: |
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ctl12 |= AR_IsAggr | AR_MoreAggr; |
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ctl17 |= SM(i->ndelim, AR_PadDelim); |
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break; |
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case AGGR_BUF_LAST: |
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ctl12 |= AR_IsAggr; |
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break; |
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case AGGR_BUF_NONE: |
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break; |
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} |
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val = (i->flags & ATH9K_TXDESC_PAPRD) >> ATH9K_TXDESC_PAPRD_S; |
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ctl12 |= SM(val, AR_PAPRDChainMask); |
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|
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WRITE_ONCE(ads->ctl12, ctl12); |
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WRITE_ONCE(ads->ctl17, ctl17); |
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WRITE_ONCE(ads->ctl15, set11nPktDurRTSCTS(i->rates, 0) |
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| set11nPktDurRTSCTS(i->rates, 1)); |
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WRITE_ONCE(ads->ctl16, set11nPktDurRTSCTS(i->rates, 2) |
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| set11nPktDurRTSCTS(i->rates, 3)); |
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WRITE_ONCE(ads->ctl18, set11nRateFlags(i->rates, 0) |
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| set11nRateFlags(i->rates, 1) |
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| set11nRateFlags(i->rates, 2) |
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| set11nRateFlags(i->rates, 3) |
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| SM(i->rtscts_rate, AR_RTSCTSRate)); |
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WRITE_ONCE(ads->ctl19, AR_Not_Sounding); |
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WRITE_ONCE(ads->ctl20, SM(i->txpower[1], AR_XmitPower1)); |
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WRITE_ONCE(ads->ctl21, SM(i->txpower[2], AR_XmitPower2)); |
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WRITE_ONCE(ads->ctl22, SM(i->txpower[3], AR_XmitPower3)); |
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} |
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static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads) |
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{ |
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int checksum; |
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|
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checksum = ads->info + ads->link |
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+ ads->data0 + ads->ctl3 |
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+ ads->data1 + ads->ctl5 |
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+ ads->data2 + ads->ctl7 |
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+ ads->data3 + ads->ctl9; |
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return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum; |
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} |
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static void ar9003_hw_set_desc_link(void *ds, u32 ds_link) |
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{ |
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struct ar9003_txc *ads = ds; |
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|
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ads->link = ds_link; |
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ads->ctl10 &= ~AR_TxPtrChkSum; |
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ads->ctl10 |= ar9003_calc_ptr_chksum(ads); |
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} |
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static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked, |
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u32 *sync_cause_p) |
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{ |
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u32 isr = 0; |
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u32 mask2 = 0; |
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struct ath9k_hw_capabilities *pCap = &ah->caps; |
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struct ath_common *common = ath9k_hw_common(ah); |
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u32 sync_cause = 0, async_cause, async_mask = AR_INTR_MAC_IRQ; |
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bool fatal_int; |
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|
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if (ath9k_hw_mci_is_enabled(ah)) |
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async_mask |= AR_INTR_ASYNC_MASK_MCI; |
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|
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async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE); |
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|
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if (async_cause & async_mask) { |
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if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) |
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== AR_RTC_STATUS_ON) |
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isr = REG_READ(ah, AR_ISR); |
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} |
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sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; |
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*masked = 0; |
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|
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if (!isr && !sync_cause && !async_cause) |
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return false; |
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|
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if (isr) { |
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if (isr & AR_ISR_BCNMISC) { |
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u32 isr2; |
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isr2 = REG_READ(ah, AR_ISR_S2); |
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mask2 |= ((isr2 & AR_ISR_S2_TIM) >> |
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MAP_ISR_S2_TIM); |
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mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> |
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MAP_ISR_S2_DTIM); |
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mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> |
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MAP_ISR_S2_DTIMSYNC); |
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mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> |
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MAP_ISR_S2_CABEND); |
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mask2 |= ((isr2 & AR_ISR_S2_GTT) << |
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MAP_ISR_S2_GTT); |
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mask2 |= ((isr2 & AR_ISR_S2_CST) << |
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MAP_ISR_S2_CST); |
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mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> |
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MAP_ISR_S2_TSFOOR); |
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mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >> |
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MAP_ISR_S2_BB_WATCHDOG); |
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|
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { |
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REG_WRITE(ah, AR_ISR_S2, isr2); |
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isr &= ~AR_ISR_BCNMISC; |
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} |
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} |
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if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) |
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isr = REG_READ(ah, AR_ISR_RAC); |
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|
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if (isr == 0xffffffff) { |
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*masked = 0; |
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return false; |
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} |
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*masked = isr & ATH9K_INT_COMMON; |
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|
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if (ah->config.rx_intr_mitigation) |
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if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) |
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*masked |= ATH9K_INT_RXLP; |
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if (ah->config.tx_intr_mitigation) |
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if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) |
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*masked |= ATH9K_INT_TX; |
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if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR)) |
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*masked |= ATH9K_INT_RXLP; |
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if (isr & AR_ISR_HP_RXOK) |
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*masked |= ATH9K_INT_RXHP; |
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if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) { |
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*masked |= ATH9K_INT_TX; |
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { |
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u32 s0, s1; |
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s0 = REG_READ(ah, AR_ISR_S0); |
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REG_WRITE(ah, AR_ISR_S0, s0); |
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s1 = REG_READ(ah, AR_ISR_S1); |
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REG_WRITE(ah, AR_ISR_S1, s1); |
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isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR | |
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AR_ISR_TXEOL); |
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} |
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} |
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if (isr & AR_ISR_GENTMR) { |
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u32 s5; |
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if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED) |
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s5 = REG_READ(ah, AR_ISR_S5_S); |
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else |
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s5 = REG_READ(ah, AR_ISR_S5); |
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ah->intr_gen_timer_trigger = |
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MS(s5, AR_ISR_S5_GENTIMER_TRIG); |
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ah->intr_gen_timer_thresh = |
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MS(s5, AR_ISR_S5_GENTIMER_THRESH); |
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|
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if (ah->intr_gen_timer_trigger) |
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*masked |= ATH9K_INT_GENTIMER; |
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|
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { |
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REG_WRITE(ah, AR_ISR_S5, s5); |
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isr &= ~AR_ISR_GENTMR; |
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} |
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|
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} |
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*masked |= mask2; |
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|
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if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) { |
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REG_WRITE(ah, AR_ISR, isr); |
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|
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(void) REG_READ(ah, AR_ISR); |
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} |
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|
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if (*masked & ATH9K_INT_BB_WATCHDOG) |
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ar9003_hw_bb_watchdog_read(ah); |
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} |
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|
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if (async_cause & AR_INTR_ASYNC_MASK_MCI) |
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ar9003_mci_get_isr(ah, masked); |
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|
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if (sync_cause) { |
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if (sync_cause_p) |
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*sync_cause_p = sync_cause; |
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fatal_int = |
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(sync_cause & |
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(AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) |
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? true : false; |
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|
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if (fatal_int) { |
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if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { |
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ath_dbg(common, ANY, |
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"received PCI FATAL interrupt\n"); |
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} |
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if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { |
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ath_dbg(common, ANY, |
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"received PCI PERR interrupt\n"); |
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} |
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*masked |= ATH9K_INT_FATAL; |
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} |
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|
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if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { |
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REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); |
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REG_WRITE(ah, AR_RC, 0); |
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*masked |= ATH9K_INT_FATAL; |
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} |
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|
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if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) |
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ath_dbg(common, INTERRUPT, |
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"AR_INTR_SYNC_LOCAL_TIMEOUT\n"); |
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|
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REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); |
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(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); |
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|
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} |
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return true; |
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} |
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|
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static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, |
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struct ath_tx_status *ts) |
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{ |
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struct ar9003_txs *ads; |
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u32 status; |
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|
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ads = &ah->ts_ring[ah->ts_tail]; |
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|
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status = READ_ONCE(ads->status8); |
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if ((status & AR_TxDone) == 0) |
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return -EINPROGRESS; |
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|
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ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size; |
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|
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if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || |
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(MS(ads->ds_info, AR_TxRxDesc) != 1)) { |
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ath_dbg(ath9k_hw_common(ah), XMIT, |
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"Tx Descriptor error %x\n", ads->ds_info); |
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memset(ads, 0, sizeof(*ads)); |
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return -EIO; |
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} |
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|
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ts->ts_rateindex = MS(status, AR_FinalTxIdx); |
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ts->ts_seqnum = MS(status, AR_SeqNum); |
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ts->tid = MS(status, AR_TxTid); |
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|
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ts->qid = MS(ads->ds_info, AR_TxQcuNum); |
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ts->desc_id = MS(ads->status1, AR_TxDescId); |
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ts->ts_tstamp = ads->status4; |
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ts->ts_status = 0; |
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ts->ts_flags = 0; |
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|
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if (status & AR_TxOpExceeded) |
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ts->ts_status |= ATH9K_TXERR_XTXOP; |
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status = READ_ONCE(ads->status2); |
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ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00); |
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ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01); |
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ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02); |
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if (status & AR_TxBaStatus) { |
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ts->ts_flags |= ATH9K_TX_BA; |
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ts->ba_low = ads->status5; |
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ts->ba_high = ads->status6; |
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} |
|
|
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status = READ_ONCE(ads->status3); |
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if (status & AR_ExcessiveRetries) |
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ts->ts_status |= ATH9K_TXERR_XRETRY; |
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if (status & AR_Filtered) |
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ts->ts_status |= ATH9K_TXERR_FILT; |
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if (status & AR_FIFOUnderrun) { |
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ts->ts_status |= ATH9K_TXERR_FIFO; |
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ath9k_hw_updatetxtriglevel(ah, true); |
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} |
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if (status & AR_TxTimerExpired) |
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ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED; |
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if (status & AR_DescCfgErr) |
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ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR; |
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if (status & AR_TxDataUnderrun) { |
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ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN; |
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ath9k_hw_updatetxtriglevel(ah, true); |
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} |
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if (status & AR_TxDelimUnderrun) { |
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ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN; |
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ath9k_hw_updatetxtriglevel(ah, true); |
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} |
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ts->ts_shortretry = MS(status, AR_RTSFailCnt); |
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ts->ts_longretry = MS(status, AR_DataFailCnt); |
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ts->ts_virtcol = MS(status, AR_VirtRetryCnt); |
|
|
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status = READ_ONCE(ads->status7); |
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ts->ts_rssi = MS(status, AR_TxRSSICombined); |
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ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10); |
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ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11); |
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ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12); |
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|
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memset(ads, 0, sizeof(*ads)); |
|
|
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return 0; |
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} |
|
|
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static int ar9003_hw_get_duration(struct ath_hw *ah, const void *ds, int index) |
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{ |
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const struct ar9003_txc *adc = ds; |
|
|
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switch (index) { |
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case 0: |
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return MS(READ_ONCE(adc->ctl15), AR_PacketDur0); |
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case 1: |
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return MS(READ_ONCE(adc->ctl15), AR_PacketDur1); |
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case 2: |
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return MS(READ_ONCE(adc->ctl16), AR_PacketDur2); |
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case 3: |
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return MS(READ_ONCE(adc->ctl16), AR_PacketDur3); |
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default: |
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return 0; |
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} |
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} |
|
|
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void ar9003_hw_attach_mac_ops(struct ath_hw *hw) |
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{ |
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struct ath_hw_ops *ops = ath9k_hw_ops(hw); |
|
|
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ops->rx_enable = ar9003_hw_rx_enable; |
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ops->set_desc_link = ar9003_hw_set_desc_link; |
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ops->get_isr = ar9003_hw_get_isr; |
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ops->set_txdesc = ar9003_set_txdesc; |
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ops->proc_txdesc = ar9003_hw_proc_txdesc; |
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ops->get_duration = ar9003_hw_get_duration; |
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} |
|
|
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void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size) |
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{ |
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REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK); |
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} |
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EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize); |
|
|
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void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp, |
|
enum ath9k_rx_qtype qtype) |
|
{ |
|
if (qtype == ATH9K_RX_QUEUE_HP) |
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REG_WRITE(ah, AR_HP_RXDP, rxdp); |
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else |
|
REG_WRITE(ah, AR_LP_RXDP, rxdp); |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma); |
|
|
|
int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, |
|
void *buf_addr) |
|
{ |
|
struct ar9003_rxs *rxsp = buf_addr; |
|
unsigned int phyerr; |
|
|
|
if ((rxsp->status11 & AR_RxDone) == 0) |
|
return -EINPROGRESS; |
|
|
|
if (MS(rxsp->ds_info, AR_DescId) != 0x168c) |
|
return -EINVAL; |
|
|
|
if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0) |
|
return -EINPROGRESS; |
|
|
|
rxs->rs_status = 0; |
|
rxs->rs_flags = 0; |
|
rxs->enc_flags = 0; |
|
rxs->bw = RATE_INFO_BW_20; |
|
|
|
rxs->rs_datalen = rxsp->status2 & AR_DataLen; |
|
rxs->rs_tstamp = rxsp->status3; |
|
|
|
/* XXX: Keycache */ |
|
rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined); |
|
rxs->rs_rssi_ctl[0] = MS(rxsp->status1, AR_RxRSSIAnt00); |
|
rxs->rs_rssi_ctl[1] = MS(rxsp->status1, AR_RxRSSIAnt01); |
|
rxs->rs_rssi_ctl[2] = MS(rxsp->status1, AR_RxRSSIAnt02); |
|
rxs->rs_rssi_ext[0] = MS(rxsp->status5, AR_RxRSSIAnt10); |
|
rxs->rs_rssi_ext[1] = MS(rxsp->status5, AR_RxRSSIAnt11); |
|
rxs->rs_rssi_ext[2] = MS(rxsp->status5, AR_RxRSSIAnt12); |
|
|
|
if (rxsp->status11 & AR_RxKeyIdxValid) |
|
rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx); |
|
else |
|
rxs->rs_keyix = ATH9K_RXKEYIX_INVALID; |
|
|
|
rxs->rs_rate = MS(rxsp->status1, AR_RxRate); |
|
rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0; |
|
|
|
rxs->rs_firstaggr = (rxsp->status11 & AR_RxFirstAggr) ? 1 : 0; |
|
rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0; |
|
rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0; |
|
rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7); |
|
rxs->enc_flags |= (rxsp->status4 & AR_GI) ? RX_ENC_FLAG_SHORT_GI : 0; |
|
rxs->enc_flags |= |
|
(rxsp->status4 & AR_STBC) ? (1 << RX_ENC_FLAG_STBC_SHIFT) : 0; |
|
rxs->bw = (rxsp->status4 & AR_2040) ? RATE_INFO_BW_40 : RATE_INFO_BW_20; |
|
|
|
rxs->evm0 = rxsp->status6; |
|
rxs->evm1 = rxsp->status7; |
|
rxs->evm2 = rxsp->status8; |
|
rxs->evm3 = rxsp->status9; |
|
rxs->evm4 = (rxsp->status10 & 0xffff); |
|
|
|
if (rxsp->status11 & AR_PreDelimCRCErr) |
|
rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE; |
|
|
|
if (rxsp->status11 & AR_PostDelimCRCErr) |
|
rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST; |
|
|
|
if (rxsp->status11 & AR_DecryptBusyErr) |
|
rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY; |
|
|
|
if ((rxsp->status11 & AR_RxFrameOK) == 0) { |
|
/* |
|
* AR_CRCErr will bet set to true if we're on the last |
|
* subframe and the AR_PostDelimCRCErr is caught. |
|
* In a way this also gives us a guarantee that when |
|
* (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot |
|
* possibly be reviewing the last subframe. AR_CRCErr |
|
* is the CRC of the actual data. |
|
*/ |
|
if (rxsp->status11 & AR_CRCErr) |
|
rxs->rs_status |= ATH9K_RXERR_CRC; |
|
else if (rxsp->status11 & AR_DecryptCRCErr) |
|
rxs->rs_status |= ATH9K_RXERR_DECRYPT; |
|
else if (rxsp->status11 & AR_MichaelErr) |
|
rxs->rs_status |= ATH9K_RXERR_MIC; |
|
if (rxsp->status11 & AR_PHYErr) { |
|
phyerr = MS(rxsp->status11, AR_PHYErrCode); |
|
/* |
|
* If we reach a point here where AR_PostDelimCRCErr is |
|
* true it implies we're *not* on the last subframe. In |
|
* in that case that we know already that the CRC of |
|
* the frame was OK, and MAC would send an ACK for that |
|
* subframe, even if we did get a phy error of type |
|
* ATH9K_PHYERR_OFDM_RESTART. This is only applicable |
|
* to frame that are prior to the last subframe. |
|
* The AR_PostDelimCRCErr is the CRC for the MPDU |
|
* delimiter, which contains the 4 reserved bits, |
|
* the MPDU length (12 bits), and follows the MPDU |
|
* delimiter for an A-MPDU subframe (0x4E = 'N' ASCII). |
|
*/ |
|
if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) && |
|
(rxsp->status11 & AR_PostDelimCRCErr)) { |
|
rxs->rs_phyerr = 0; |
|
} else { |
|
rxs->rs_status |= ATH9K_RXERR_PHY; |
|
rxs->rs_phyerr = phyerr; |
|
} |
|
} |
|
} |
|
|
|
if (rxsp->status11 & AR_KeyMiss) |
|
rxs->rs_status |= ATH9K_RXERR_KEYMISS; |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma); |
|
|
|
void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah) |
|
{ |
|
ah->ts_tail = 0; |
|
|
|
memset((void *) ah->ts_ring, 0, |
|
ah->ts_size * sizeof(struct ar9003_txs)); |
|
|
|
ath_dbg(ath9k_hw_common(ah), XMIT, |
|
"TS Start 0x%x End 0x%x Virt %p, Size %d\n", |
|
ah->ts_paddr_start, ah->ts_paddr_end, |
|
ah->ts_ring, ah->ts_size); |
|
|
|
REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start); |
|
REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end); |
|
} |
|
|
|
void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start, |
|
u32 ts_paddr_start, |
|
u16 size) |
|
{ |
|
|
|
ah->ts_paddr_start = ts_paddr_start; |
|
ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs)); |
|
ah->ts_size = size; |
|
ah->ts_ring = ts_start; |
|
|
|
ath9k_hw_reset_txstatus_ring(ah); |
|
} |
|
EXPORT_SYMBOL(ath9k_hw_setup_statusring);
|
|
|