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454 lines
13 KiB
454 lines
13 KiB
/* |
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* Copyright (c) 2008-2011 Atheros Communications Inc. |
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* |
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* Permission to use, copy, modify, and/or distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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*/ |
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#include <linux/moduleparam.h> |
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#include "hw.h" |
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#include "ar5008_initvals.h" |
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#include "ar9001_initvals.h" |
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#include "ar9002_initvals.h" |
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#include "ar9002_phy.h" |
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|
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/* General hardware code for the A5008/AR9001/AR9002 hadware families */ |
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static int ar9002_hw_init_mode_regs(struct ath_hw *ah) |
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{ |
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if (AR_SREV_9271(ah)) { |
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INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271); |
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INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271); |
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INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg); |
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return 0; |
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} |
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INIT_INI_ARRAY(&ah->iniPcieSerdes, |
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ar9280PciePhy_clkreq_always_on_L1_9280); |
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if (AR_SREV_9287_11_OR_LATER(ah)) { |
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INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1); |
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INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1); |
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} else if (AR_SREV_9285_12_OR_LATER(ah)) { |
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INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2); |
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INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2); |
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} else if (AR_SREV_9280_20_OR_LATER(ah)) { |
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INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2); |
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INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2); |
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INIT_INI_ARRAY(&ah->iniModesFastClock, |
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ar9280Modes_fast_clock_9280_2); |
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} else if (AR_SREV_9160_10_OR_LATER(ah)) { |
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INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160); |
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INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160); |
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if (AR_SREV_9160_11(ah)) { |
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INIT_INI_ARRAY(&ah->iniAddac, |
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ar5416Addac_9160_1_1); |
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} else { |
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INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160); |
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} |
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} else if (AR_SREV_9100_OR_LATER(ah)) { |
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INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100); |
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INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100); |
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INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100); |
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} else { |
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INIT_INI_ARRAY(&ah->iniModes, ar5416Modes); |
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INIT_INI_ARRAY(&ah->iniCommon, ar5416Common); |
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INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac); |
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} |
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if (!AR_SREV_9280_20_OR_LATER(ah)) { |
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/* Common for AR5416, AR913x, AR9160 */ |
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INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain); |
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/* Common for AR913x, AR9160 */ |
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if (!AR_SREV_5416(ah)) |
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INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC_9100); |
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else |
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INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC); |
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} |
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/* iniAddac needs to be modified for these chips */ |
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if (AR_SREV_9160(ah) || !AR_SREV_5416_22_OR_LATER(ah)) { |
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struct ar5416IniArray *addac = &ah->iniAddac; |
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u32 size = sizeof(u32) * addac->ia_rows * addac->ia_columns; |
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u32 *data; |
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data = devm_kzalloc(ah->dev, size, GFP_KERNEL); |
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if (!data) |
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return -ENOMEM; |
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memcpy(data, addac->ia_array, size); |
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addac->ia_array = data; |
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if (!AR_SREV_5416_22_OR_LATER(ah)) { |
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/* override CLKDRV value */ |
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INI_RA(addac, 31,1) = 0; |
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} |
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} |
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if (AR_SREV_9287_11_OR_LATER(ah)) { |
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INIT_INI_ARRAY(&ah->iniCckfirNormal, |
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ar9287Common_normal_cck_fir_coeff_9287_1_1); |
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INIT_INI_ARRAY(&ah->iniCckfirJapan2484, |
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ar9287Common_japan_2484_cck_fir_coeff_9287_1_1); |
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} |
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return 0; |
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} |
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static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah) |
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{ |
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u32 rxgain_type; |
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if (ah->eep_ops->get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_17) { |
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rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); |
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if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) |
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INIT_INI_ARRAY(&ah->iniModesRxGain, |
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ar9280Modes_backoff_13db_rxgain_9280_2); |
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else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) |
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INIT_INI_ARRAY(&ah->iniModesRxGain, |
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ar9280Modes_backoff_23db_rxgain_9280_2); |
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else |
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INIT_INI_ARRAY(&ah->iniModesRxGain, |
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ar9280Modes_original_rxgain_9280_2); |
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} else { |
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INIT_INI_ARRAY(&ah->iniModesRxGain, |
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ar9280Modes_original_rxgain_9280_2); |
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} |
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} |
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static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type) |
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{ |
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if (ah->eep_ops->get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_19) { |
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if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) |
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INIT_INI_ARRAY(&ah->iniModesTxGain, |
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ar9280Modes_high_power_tx_gain_9280_2); |
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else |
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INIT_INI_ARRAY(&ah->iniModesTxGain, |
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ar9280Modes_original_tx_gain_9280_2); |
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} else { |
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INIT_INI_ARRAY(&ah->iniModesTxGain, |
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ar9280Modes_original_tx_gain_9280_2); |
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} |
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} |
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static void ar9271_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type) |
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{ |
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if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) |
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INIT_INI_ARRAY(&ah->iniModesTxGain, |
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ar9271Modes_high_power_tx_gain_9271); |
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else |
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INIT_INI_ARRAY(&ah->iniModesTxGain, |
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ar9271Modes_normal_power_tx_gain_9271); |
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} |
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static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah) |
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{ |
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u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); |
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if (AR_SREV_9287_11_OR_LATER(ah)) |
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INIT_INI_ARRAY(&ah->iniModesRxGain, |
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ar9287Modes_rx_gain_9287_1_1); |
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else if (AR_SREV_9280_20(ah)) |
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ar9280_20_hw_init_rxgain_ini(ah); |
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if (AR_SREV_9271(ah)) { |
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ar9271_hw_init_txgain_ini(ah, txgain_type); |
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} else if (AR_SREV_9287_11_OR_LATER(ah)) { |
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INIT_INI_ARRAY(&ah->iniModesTxGain, |
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ar9287Modes_tx_gain_9287_1_1); |
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} else if (AR_SREV_9280_20(ah)) { |
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ar9280_20_hw_init_txgain_ini(ah, txgain_type); |
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} else if (AR_SREV_9285_12_OR_LATER(ah)) { |
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/* txgain table */ |
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if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { |
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if (AR_SREV_9285E_20(ah)) { |
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INIT_INI_ARRAY(&ah->iniModesTxGain, |
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ar9285Modes_XE2_0_high_power); |
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} else { |
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INIT_INI_ARRAY(&ah->iniModesTxGain, |
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ar9285Modes_high_power_tx_gain_9285_1_2); |
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} |
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} else { |
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if (AR_SREV_9285E_20(ah)) { |
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INIT_INI_ARRAY(&ah->iniModesTxGain, |
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ar9285Modes_XE2_0_normal_power); |
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} else { |
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INIT_INI_ARRAY(&ah->iniModesTxGain, |
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ar9285Modes_original_tx_gain_9285_1_2); |
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} |
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} |
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} |
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} |
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/* |
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* Helper for ASPM support. |
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* |
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* Disable PLL when in L0s as well as receiver clock when in L1. |
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* This power saving option must be enabled through the SerDes. |
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* |
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* Programming the SerDes must go through the same 288 bit serial shift |
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* register as the other analog registers. Hence the 9 writes. |
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*/ |
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static void ar9002_hw_configpcipowersave(struct ath_hw *ah, |
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bool power_off) |
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{ |
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u8 i; |
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u32 val; |
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/* Nothing to do on restore for 11N */ |
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if (!power_off /* !restore */) { |
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if (AR_SREV_9280_20_OR_LATER(ah)) { |
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/* |
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* AR9280 2.0 or later chips use SerDes values from the |
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* initvals.h initialized depending on chipset during |
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* __ath9k_hw_init() |
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*/ |
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for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { |
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REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), |
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INI_RA(&ah->iniPcieSerdes, i, 1)); |
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} |
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} else { |
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ENABLE_REGWRITE_BUFFER(ah); |
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REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
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REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
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/* RX shut off when elecidle is asserted */ |
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REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); |
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REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); |
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REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); |
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/* |
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* Ignore ah->ah_config.pcie_clock_req setting for |
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* pre-AR9280 11n |
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*/ |
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REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); |
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REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
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REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
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REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); |
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/* Load the new settings */ |
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REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
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REGWRITE_BUFFER_FLUSH(ah); |
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} |
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udelay(1000); |
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} |
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if (power_off) { |
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/* clear bit 19 to disable L1 */ |
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REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
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val = REG_READ(ah, AR_WA); |
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/* |
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* Set PCIe workaround bits |
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* In AR9280 and AR9285, bit 14 in WA register (disable L1) |
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* should only be set when device enters D3 and be |
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* cleared when device comes back to D0. |
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*/ |
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if (ah->config.pcie_waen) { |
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if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) |
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val |= AR_WA_D3_L1_DISABLE; |
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} else { |
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if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) { |
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if (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE) |
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val |= AR_WA_D3_L1_DISABLE; |
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} else if (AR_SREV_9280(ah)) { |
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if (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE) |
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val |= AR_WA_D3_L1_DISABLE; |
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} |
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} |
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if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) { |
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/* |
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* Disable bit 6 and 7 before entering D3 to |
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* prevent system hang. |
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*/ |
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val &= ~(AR_WA_BIT6 | AR_WA_BIT7); |
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} |
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if (AR_SREV_9280(ah)) |
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val |= AR_WA_BIT22; |
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if (AR_SREV_9285E_20(ah)) |
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val |= AR_WA_BIT23; |
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REG_WRITE(ah, AR_WA, val); |
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} else { |
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if (ah->config.pcie_waen) { |
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val = ah->config.pcie_waen; |
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val &= (~AR_WA_D3_L1_DISABLE); |
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} else { |
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if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) { |
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val = AR9285_WA_DEFAULT; |
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val &= (~AR_WA_D3_L1_DISABLE); |
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} else if (AR_SREV_9280(ah)) { |
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/* |
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* For AR9280 chips, bit 22 of 0x4004 |
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* needs to be set. |
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*/ |
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val = AR9280_WA_DEFAULT; |
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val &= (~AR_WA_D3_L1_DISABLE); |
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} else { |
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val = AR_WA_DEFAULT; |
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} |
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} |
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/* WAR for ASPM system hang */ |
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if (AR_SREV_9285(ah) || AR_SREV_9287(ah)) |
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val |= (AR_WA_BIT6 | AR_WA_BIT7); |
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if (AR_SREV_9285E_20(ah)) |
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val |= AR_WA_BIT23; |
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REG_WRITE(ah, AR_WA, val); |
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/* set bit 19 to allow forcing of pcie core into L1 state */ |
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REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); |
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} |
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} |
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static int ar9002_hw_get_radiorev(struct ath_hw *ah) |
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{ |
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u32 val; |
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int i; |
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ENABLE_REGWRITE_BUFFER(ah); |
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REG_WRITE(ah, AR_PHY(0x36), 0x00007058); |
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for (i = 0; i < 8; i++) |
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REG_WRITE(ah, AR_PHY(0x20), 0x00010000); |
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REGWRITE_BUFFER_FLUSH(ah); |
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val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; |
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val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); |
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return ath9k_hw_reverse_bits(val, 8); |
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} |
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int ar9002_hw_rf_claim(struct ath_hw *ah) |
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{ |
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u32 val; |
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REG_WRITE(ah, AR_PHY(0), 0x00000007); |
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val = ar9002_hw_get_radiorev(ah); |
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switch (val & AR_RADIO_SREV_MAJOR) { |
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case 0: |
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val = AR_RAD5133_SREV_MAJOR; |
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break; |
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case AR_RAD5133_SREV_MAJOR: |
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case AR_RAD5122_SREV_MAJOR: |
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case AR_RAD2133_SREV_MAJOR: |
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case AR_RAD2122_SREV_MAJOR: |
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break; |
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default: |
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ath_err(ath9k_hw_common(ah), |
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"Radio Chip Rev 0x%02X not supported\n", |
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val & AR_RADIO_SREV_MAJOR); |
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return -EOPNOTSUPP; |
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} |
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ah->hw_version.analog5GhzRev = val; |
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return 0; |
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} |
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void ar9002_hw_enable_async_fifo(struct ath_hw *ah) |
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{ |
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if (AR_SREV_9287_13_OR_LATER(ah)) { |
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REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, |
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AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL); |
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REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); |
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REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, |
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AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); |
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REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, |
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AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET); |
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} |
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} |
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static void ar9002_hw_init_hang_checks(struct ath_hw *ah) |
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{ |
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if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { |
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ah->config.hw_hang_checks |= HW_BB_RIFS_HANG; |
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ah->config.hw_hang_checks |= HW_BB_DFS_HANG; |
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} |
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if (AR_SREV_9280(ah)) |
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ah->config.hw_hang_checks |= HW_BB_RX_CLEAR_STUCK_HANG; |
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if (AR_SREV_5416(ah) || AR_SREV_9100(ah) || AR_SREV_9160(ah)) |
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ah->config.hw_hang_checks |= HW_MAC_HANG; |
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} |
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/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */ |
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int ar9002_hw_attach_ops(struct ath_hw *ah) |
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{ |
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
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struct ath_hw_ops *ops = ath9k_hw_ops(ah); |
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int ret; |
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ret = ar9002_hw_init_mode_regs(ah); |
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if (ret) |
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return ret; |
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priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs; |
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priv_ops->init_hang_checks = ar9002_hw_init_hang_checks; |
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ops->config_pci_powersave = ar9002_hw_configpcipowersave; |
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ret = ar5008_hw_attach_phy_ops(ah); |
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if (ret) |
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return ret; |
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if (AR_SREV_9280_20_OR_LATER(ah)) |
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ar9002_hw_attach_phy_ops(ah); |
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ar9002_hw_attach_calib_ops(ah); |
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ar9002_hw_attach_mac_ops(ah); |
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return 0; |
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} |
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void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan) |
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{ |
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u32 modesIndex; |
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int i; |
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|
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if (IS_CHAN_5GHZ(chan)) |
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modesIndex = IS_CHAN_HT40(chan) ? 2 : 1; |
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else |
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modesIndex = IS_CHAN_HT40(chan) ? 3 : 4; |
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ENABLE_REGWRITE_BUFFER(ah); |
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for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) { |
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u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0); |
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u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex); |
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u32 val_orig; |
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|
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if (reg == AR_PHY_CCK_DETECT) { |
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val_orig = REG_READ(ah, reg); |
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val &= AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK; |
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val_orig &= ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK; |
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REG_WRITE(ah, reg, val|val_orig); |
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} else |
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REG_WRITE(ah, reg, val); |
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} |
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REGWRITE_BUFFER_FLUSH(ah); |
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}
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