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513 lines
15 KiB
513 lines
15 KiB
/* |
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* Copyright (c) 2008-2011 Atheros Communications Inc. |
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* |
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* Permission to use, copy, modify, and/or distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/export.h> |
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#include "hw.h" |
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#include "hw-ops.h" |
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struct ani_ofdm_level_entry { |
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int spur_immunity_level; |
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int fir_step_level; |
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int ofdm_weak_signal_on; |
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}; |
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|
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/* values here are relative to the INI */ |
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|
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/* |
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* Legend: |
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* |
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* SI: Spur immunity |
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* FS: FIR Step |
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* WS: OFDM / CCK Weak Signal detection |
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* MRC-CCK: Maximal Ratio Combining for CCK |
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*/ |
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static const struct ani_ofdm_level_entry ofdm_level_table[] = { |
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/* SI FS WS */ |
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{ 0, 0, 1 }, /* lvl 0 */ |
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{ 1, 1, 1 }, /* lvl 1 */ |
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{ 2, 2, 1 }, /* lvl 2 */ |
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{ 3, 2, 1 }, /* lvl 3 (default) */ |
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{ 4, 3, 1 }, /* lvl 4 */ |
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{ 5, 4, 1 }, /* lvl 5 */ |
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{ 6, 5, 1 }, /* lvl 6 */ |
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{ 7, 6, 1 }, /* lvl 7 */ |
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{ 7, 7, 1 }, /* lvl 8 */ |
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{ 7, 8, 0 } /* lvl 9 */ |
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}; |
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#define ATH9K_ANI_OFDM_NUM_LEVEL \ |
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ARRAY_SIZE(ofdm_level_table) |
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#define ATH9K_ANI_OFDM_MAX_LEVEL \ |
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(ATH9K_ANI_OFDM_NUM_LEVEL-1) |
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#define ATH9K_ANI_OFDM_DEF_LEVEL \ |
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3 /* default level - matches the INI settings */ |
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|
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/* |
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* MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm. |
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* With OFDM for single stream you just add up all antenna inputs, you're |
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* only interested in what you get after FFT. Signal alignment is also not |
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* required for OFDM because any phase difference adds up in the frequency |
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* domain. |
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* |
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* MRC requires extra work for use with CCK. You need to align the antenna |
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* signals from the different antenna before you can add the signals together. |
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* You need alignment of signals as CCK is in time domain, so addition can cancel |
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* your signal completely if phase is 180 degrees (think of adding sine waves). |
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* You also need to remove noise before the addition and this is where ANI |
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* MRC CCK comes into play. One of the antenna inputs may be stronger but |
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* lower SNR, so just adding after alignment can be dangerous. |
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* |
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* Regardless of alignment in time, the antenna signals add constructively after |
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* FFT and improve your reception. For more information: |
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* |
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* https://en.wikipedia.org/wiki/Maximal-ratio_combining |
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*/ |
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struct ani_cck_level_entry { |
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int fir_step_level; |
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int mrc_cck_on; |
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}; |
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static const struct ani_cck_level_entry cck_level_table[] = { |
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/* FS MRC-CCK */ |
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{ 0, 1 }, /* lvl 0 */ |
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{ 1, 1 }, /* lvl 1 */ |
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{ 2, 1 }, /* lvl 2 (default) */ |
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{ 3, 1 }, /* lvl 3 */ |
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{ 4, 0 }, /* lvl 4 */ |
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{ 5, 0 }, /* lvl 5 */ |
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{ 6, 0 }, /* lvl 6 */ |
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{ 7, 0 }, /* lvl 7 (only for high rssi) */ |
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{ 8, 0 } /* lvl 8 (only for high rssi) */ |
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}; |
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#define ATH9K_ANI_CCK_NUM_LEVEL \ |
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ARRAY_SIZE(cck_level_table) |
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#define ATH9K_ANI_CCK_MAX_LEVEL \ |
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(ATH9K_ANI_CCK_NUM_LEVEL-1) |
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#define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \ |
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(ATH9K_ANI_CCK_NUM_LEVEL-3) |
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#define ATH9K_ANI_CCK_DEF_LEVEL \ |
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2 /* default level - matches the INI settings */ |
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static void ath9k_hw_update_mibstats(struct ath_hw *ah, |
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struct ath9k_mib_stats *stats) |
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{ |
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u32 addr[5] = {AR_RTS_OK, AR_RTS_FAIL, AR_ACK_FAIL, |
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AR_FCS_FAIL, AR_BEACON_CNT}; |
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u32 data[5]; |
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REG_READ_MULTI(ah, &addr[0], &data[0], 5); |
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/* AR_RTS_OK */ |
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stats->rts_good += data[0]; |
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/* AR_RTS_FAIL */ |
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stats->rts_bad += data[1]; |
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/* AR_ACK_FAIL */ |
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stats->ackrcv_bad += data[2]; |
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/* AR_FCS_FAIL */ |
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stats->fcs_bad += data[3]; |
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/* AR_BEACON_CNT */ |
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stats->beacons += data[4]; |
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} |
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static void ath9k_ani_restart(struct ath_hw *ah) |
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{ |
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struct ar5416AniState *aniState = &ah->ani; |
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aniState->listenTime = 0; |
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ENABLE_REGWRITE_BUFFER(ah); |
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REG_WRITE(ah, AR_PHY_ERR_1, 0); |
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REG_WRITE(ah, AR_PHY_ERR_2, 0); |
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REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); |
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REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); |
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REGWRITE_BUFFER_FLUSH(ah); |
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ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
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aniState->ofdmPhyErrCount = 0; |
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aniState->cckPhyErrCount = 0; |
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} |
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/* Adjust the OFDM Noise Immunity Level */ |
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static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel, |
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bool scan) |
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{ |
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struct ar5416AniState *aniState = &ah->ani; |
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struct ath_common *common = ath9k_hw_common(ah); |
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const struct ani_ofdm_level_entry *entry_ofdm; |
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const struct ani_cck_level_entry *entry_cck; |
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bool weak_sig; |
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ath_dbg(common, ANI, "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", |
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aniState->ofdmNoiseImmunityLevel, |
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immunityLevel, BEACON_RSSI(ah), |
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ATH9K_ANI_RSSI_THR_LOW, |
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ATH9K_ANI_RSSI_THR_HIGH); |
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if (AR_SREV_9100(ah) && immunityLevel < ATH9K_ANI_OFDM_DEF_LEVEL) |
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immunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL; |
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if (!scan) |
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aniState->ofdmNoiseImmunityLevel = immunityLevel; |
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entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; |
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entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; |
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if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level) |
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ath9k_hw_ani_control(ah, |
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ATH9K_ANI_SPUR_IMMUNITY_LEVEL, |
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entry_ofdm->spur_immunity_level); |
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if (aniState->firstepLevel != entry_ofdm->fir_step_level && |
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entry_ofdm->fir_step_level >= entry_cck->fir_step_level) |
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ath9k_hw_ani_control(ah, |
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ATH9K_ANI_FIRSTEP_LEVEL, |
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entry_ofdm->fir_step_level); |
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weak_sig = entry_ofdm->ofdm_weak_signal_on; |
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if (ah->opmode == NL80211_IFTYPE_STATION && |
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BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_HIGH) |
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weak_sig = true; |
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/* |
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* Newer chipsets are better at dealing with high PHY error counts - |
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* keep weak signal detection enabled when no RSSI threshold is |
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* available to determine if it is needed (mode != STA) |
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*/ |
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else if (AR_SREV_9300_20_OR_LATER(ah) && |
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ah->opmode != NL80211_IFTYPE_STATION) |
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weak_sig = true; |
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/* Older chipsets are more sensitive to high PHY error counts */ |
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else if (!AR_SREV_9300_20_OR_LATER(ah) && |
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aniState->ofdmNoiseImmunityLevel >= 8) |
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weak_sig = false; |
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if (aniState->ofdmWeakSigDetect != weak_sig) |
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ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION, |
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weak_sig); |
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if (!AR_SREV_9300_20_OR_LATER(ah)) |
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return; |
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if (aniState->ofdmNoiseImmunityLevel >= ATH9K_ANI_OFDM_DEF_LEVEL) { |
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ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH; |
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ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_ABOVE_INI; |
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} else { |
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ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_BELOW_INI; |
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ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW; |
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} |
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} |
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static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) |
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{ |
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struct ar5416AniState *aniState = &ah->ani; |
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if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL) |
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ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1, false); |
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} |
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/* |
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* Set the ANI settings to match an CCK level. |
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*/ |
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static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel, |
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bool scan) |
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{ |
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struct ar5416AniState *aniState = &ah->ani; |
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struct ath_common *common = ath9k_hw_common(ah); |
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const struct ani_ofdm_level_entry *entry_ofdm; |
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const struct ani_cck_level_entry *entry_cck; |
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ath_dbg(common, ANI, "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n", |
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aniState->cckNoiseImmunityLevel, immunityLevel, |
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BEACON_RSSI(ah), ATH9K_ANI_RSSI_THR_LOW, |
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ATH9K_ANI_RSSI_THR_HIGH); |
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if (AR_SREV_9100(ah) && immunityLevel < ATH9K_ANI_CCK_DEF_LEVEL) |
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immunityLevel = ATH9K_ANI_CCK_DEF_LEVEL; |
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if (ah->opmode == NL80211_IFTYPE_STATION && |
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BEACON_RSSI(ah) <= ATH9K_ANI_RSSI_THR_LOW && |
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immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI) |
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immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI; |
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if (!scan) |
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aniState->cckNoiseImmunityLevel = immunityLevel; |
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entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel]; |
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entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel]; |
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if (aniState->firstepLevel != entry_cck->fir_step_level && |
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entry_cck->fir_step_level >= entry_ofdm->fir_step_level) |
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ath9k_hw_ani_control(ah, |
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ATH9K_ANI_FIRSTEP_LEVEL, |
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entry_cck->fir_step_level); |
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/* Skip MRC CCK for pre AR9003 families */ |
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if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah) || |
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AR_SREV_9565(ah) || AR_SREV_9561(ah)) |
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return; |
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if (aniState->mrcCCK != entry_cck->mrc_cck_on) |
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ath9k_hw_ani_control(ah, |
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ATH9K_ANI_MRC_CCK, |
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entry_cck->mrc_cck_on); |
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} |
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static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah) |
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{ |
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struct ar5416AniState *aniState = &ah->ani; |
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if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL) |
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ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1, |
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false); |
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} |
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/* |
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* only lower either OFDM or CCK errors per turn |
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* we lower the other one next time |
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*/ |
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static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah) |
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{ |
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struct ar5416AniState *aniState = &ah->ani; |
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|
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/* lower OFDM noise immunity */ |
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if (aniState->ofdmNoiseImmunityLevel > 0 && |
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(aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) { |
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ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1, |
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false); |
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return; |
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} |
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/* lower CCK noise immunity */ |
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if (aniState->cckNoiseImmunityLevel > 0) |
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ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1, |
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false); |
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} |
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/* |
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* Restore the ANI parameters in the HAL and reset the statistics. |
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* This routine should be called for every hardware reset and for |
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* every channel change. |
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*/ |
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void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning) |
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{ |
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struct ar5416AniState *aniState = &ah->ani; |
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struct ath9k_channel *chan = ah->curchan; |
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struct ath_common *common = ath9k_hw_common(ah); |
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int ofdm_nil, cck_nil; |
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if (!chan) |
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return; |
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BUG_ON(aniState == NULL); |
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ah->stats.ast_ani_reset++; |
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ofdm_nil = max_t(int, ATH9K_ANI_OFDM_DEF_LEVEL, |
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aniState->ofdmNoiseImmunityLevel); |
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cck_nil = max_t(int, ATH9K_ANI_CCK_DEF_LEVEL, |
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aniState->cckNoiseImmunityLevel); |
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if (is_scanning || |
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(ah->opmode != NL80211_IFTYPE_STATION && |
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ah->opmode != NL80211_IFTYPE_ADHOC)) { |
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/* |
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* If we're scanning or in AP mode, the defaults (ini) |
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* should be in place. For an AP we assume the historical |
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* levels for this channel are probably outdated so start |
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* from defaults instead. |
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*/ |
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if (aniState->ofdmNoiseImmunityLevel != |
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ATH9K_ANI_OFDM_DEF_LEVEL || |
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aniState->cckNoiseImmunityLevel != |
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ATH9K_ANI_CCK_DEF_LEVEL) { |
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ath_dbg(common, ANI, |
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"Restore defaults: opmode %u chan %d Mhz is_scanning=%d ofdm:%d cck:%d\n", |
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ah->opmode, |
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chan->channel, |
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is_scanning, |
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aniState->ofdmNoiseImmunityLevel, |
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aniState->cckNoiseImmunityLevel); |
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ofdm_nil = ATH9K_ANI_OFDM_DEF_LEVEL; |
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cck_nil = ATH9K_ANI_CCK_DEF_LEVEL; |
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} |
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} else { |
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/* |
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* restore historical levels for this channel |
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*/ |
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ath_dbg(common, ANI, |
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"Restore history: opmode %u chan %d Mhz is_scanning=%d ofdm:%d cck:%d\n", |
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ah->opmode, |
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chan->channel, |
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is_scanning, |
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aniState->ofdmNoiseImmunityLevel, |
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aniState->cckNoiseImmunityLevel); |
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} |
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ath9k_hw_set_ofdm_nil(ah, ofdm_nil, is_scanning); |
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ath9k_hw_set_cck_nil(ah, cck_nil, is_scanning); |
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ath9k_ani_restart(ah); |
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} |
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static bool ath9k_hw_ani_read_counters(struct ath_hw *ah) |
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{ |
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struct ath_common *common = ath9k_hw_common(ah); |
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struct ar5416AniState *aniState = &ah->ani; |
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u32 phyCnt1, phyCnt2; |
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int32_t listenTime; |
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ath_hw_cycle_counters_update(common); |
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listenTime = ath_hw_get_listen_time(common); |
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if (listenTime <= 0) { |
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ah->stats.ast_ani_lneg_or_lzero++; |
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ath9k_ani_restart(ah); |
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return false; |
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} |
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aniState->listenTime += listenTime; |
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ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
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phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); |
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phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); |
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ah->stats.ast_ani_ofdmerrs += phyCnt1 - aniState->ofdmPhyErrCount; |
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aniState->ofdmPhyErrCount = phyCnt1; |
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ah->stats.ast_ani_cckerrs += phyCnt2 - aniState->cckPhyErrCount; |
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aniState->cckPhyErrCount = phyCnt2; |
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return true; |
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} |
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void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan) |
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{ |
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struct ar5416AniState *aniState = &ah->ani; |
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struct ath_common *common = ath9k_hw_common(ah); |
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u32 ofdmPhyErrRate, cckPhyErrRate; |
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|
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if (!ath9k_hw_ani_read_counters(ah)) |
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return; |
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ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 / |
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aniState->listenTime; |
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cckPhyErrRate = aniState->cckPhyErrCount * 1000 / |
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aniState->listenTime; |
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ath_dbg(common, ANI, |
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"listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n", |
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aniState->listenTime, |
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aniState->ofdmNoiseImmunityLevel, |
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ofdmPhyErrRate, aniState->cckNoiseImmunityLevel, |
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cckPhyErrRate, aniState->ofdmsTurn); |
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|
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if (aniState->listenTime > ah->aniperiod) { |
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if (cckPhyErrRate < ah->config.cck_trig_low && |
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ofdmPhyErrRate < ah->config.ofdm_trig_low) { |
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ath9k_hw_ani_lower_immunity(ah); |
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aniState->ofdmsTurn = !aniState->ofdmsTurn; |
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} else if (ofdmPhyErrRate > ah->config.ofdm_trig_high) { |
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ath9k_hw_ani_ofdm_err_trigger(ah); |
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aniState->ofdmsTurn = false; |
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} else if (cckPhyErrRate > ah->config.cck_trig_high) { |
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ath9k_hw_ani_cck_err_trigger(ah); |
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aniState->ofdmsTurn = true; |
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} else |
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return; |
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|
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ath9k_ani_restart(ah); |
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} |
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} |
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EXPORT_SYMBOL(ath9k_hw_ani_monitor); |
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|
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void ath9k_enable_mib_counters(struct ath_hw *ah) |
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{ |
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struct ath_common *common = ath9k_hw_common(ah); |
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|
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ath_dbg(common, ANI, "Enable MIB counters\n"); |
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ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
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|
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ENABLE_REGWRITE_BUFFER(ah); |
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|
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REG_WRITE(ah, AR_FILT_OFDM, 0); |
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REG_WRITE(ah, AR_FILT_CCK, 0); |
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REG_WRITE(ah, AR_MIBC, |
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~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) |
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& 0x0f); |
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REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); |
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REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); |
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|
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REGWRITE_BUFFER_FLUSH(ah); |
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} |
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|
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/* Freeze the MIB counters, get the stats and then clear them */ |
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void ath9k_hw_disable_mib_counters(struct ath_hw *ah) |
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{ |
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struct ath_common *common = ath9k_hw_common(ah); |
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|
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ath_dbg(common, ANI, "Disable MIB counters\n"); |
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|
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REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); |
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ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); |
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REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); |
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REG_WRITE(ah, AR_FILT_OFDM, 0); |
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REG_WRITE(ah, AR_FILT_CCK, 0); |
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} |
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EXPORT_SYMBOL(ath9k_hw_disable_mib_counters); |
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|
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void ath9k_hw_ani_init(struct ath_hw *ah) |
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{ |
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struct ath_common *common = ath9k_hw_common(ah); |
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struct ar5416AniState *ani = &ah->ani; |
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|
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ath_dbg(common, ANI, "Initialize ANI\n"); |
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if (AR_SREV_9300_20_OR_LATER(ah)) { |
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ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH; |
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ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW; |
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ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH; |
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ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW; |
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} else { |
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ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD; |
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ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD; |
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ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD; |
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ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD; |
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} |
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ani->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; |
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ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; |
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ani->mrcCCK = AR_SREV_9300_20_OR_LATER(ah) ? true : false; |
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ani->ofdmsTurn = true; |
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ani->ofdmWeakSigDetect = true; |
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ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL; |
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ani->ofdmNoiseImmunityLevel = ATH9K_ANI_OFDM_DEF_LEVEL; |
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|
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/* |
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* since we expect some ongoing maintenance on the tables, let's sanity |
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* check here default level should not modify INI setting. |
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*/ |
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ah->aniperiod = ATH9K_ANI_PERIOD; |
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ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL; |
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ath9k_ani_restart(ah); |
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ath9k_enable_mib_counters(ah); |
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}
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