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699 lines
18 KiB
699 lines
18 KiB
/* |
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* Copyright (c) 2007-2011 Atheros Communications Inc. |
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* Copyright (c) 2011-2012 Qualcomm Atheros, Inc. |
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* |
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* Permission to use, copy, modify, and/or distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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*/ |
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#include "hif.h" |
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|
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#include <linux/export.h> |
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|
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#include "core.h" |
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#include "target.h" |
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#include "hif-ops.h" |
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#include "debug.h" |
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#include "trace.h" |
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|
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#define MAILBOX_FOR_BLOCK_SIZE 1 |
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|
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#define ATH6KL_TIME_QUANTUM 10 /* in ms */ |
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|
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static int ath6kl_hif_cp_scat_dma_buf(struct hif_scatter_req *req, |
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bool from_dma) |
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{ |
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u8 *buf; |
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int i; |
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buf = req->virt_dma_buf; |
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|
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for (i = 0; i < req->scat_entries; i++) { |
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if (from_dma) |
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memcpy(req->scat_list[i].buf, buf, |
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req->scat_list[i].len); |
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else |
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memcpy(buf, req->scat_list[i].buf, |
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req->scat_list[i].len); |
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buf += req->scat_list[i].len; |
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} |
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return 0; |
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} |
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|
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int ath6kl_hif_rw_comp_handler(void *context, int status) |
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{ |
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struct htc_packet *packet = context; |
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|
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ath6kl_dbg(ATH6KL_DBG_HIF, "hif rw completion pkt 0x%p status %d\n", |
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packet, status); |
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packet->status = status; |
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packet->completion(packet->context, packet); |
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return 0; |
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} |
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EXPORT_SYMBOL(ath6kl_hif_rw_comp_handler); |
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|
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#define REGISTER_DUMP_COUNT 60 |
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#define REGISTER_DUMP_LEN_MAX 60 |
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|
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static void ath6kl_hif_dump_fw_crash(struct ath6kl *ar) |
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{ |
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__le32 regdump_val[REGISTER_DUMP_LEN_MAX]; |
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u32 i, address, regdump_addr = 0; |
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int ret; |
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|
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/* the reg dump pointer is copied to the host interest area */ |
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address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_failure_state)); |
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address = TARG_VTOP(ar->target_type, address); |
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|
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/* read RAM location through diagnostic window */ |
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ret = ath6kl_diag_read32(ar, address, ®dump_addr); |
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|
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if (ret || !regdump_addr) { |
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ath6kl_warn("failed to get ptr to register dump area: %d\n", |
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ret); |
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return; |
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} |
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ath6kl_dbg(ATH6KL_DBG_IRQ, "register dump data address 0x%x\n", |
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regdump_addr); |
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regdump_addr = TARG_VTOP(ar->target_type, regdump_addr); |
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|
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/* fetch register dump data */ |
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ret = ath6kl_diag_read(ar, regdump_addr, (u8 *)®dump_val[0], |
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REGISTER_DUMP_COUNT * (sizeof(u32))); |
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if (ret) { |
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ath6kl_warn("failed to get register dump: %d\n", ret); |
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return; |
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} |
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ath6kl_info("crash dump:\n"); |
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ath6kl_info("hw 0x%x fw %s\n", ar->wiphy->hw_version, |
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ar->wiphy->fw_version); |
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BUILD_BUG_ON(REGISTER_DUMP_COUNT % 4); |
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for (i = 0; i < REGISTER_DUMP_COUNT; i += 4) { |
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ath6kl_info("%d: 0x%8.8x 0x%8.8x 0x%8.8x 0x%8.8x\n", |
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i, |
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le32_to_cpu(regdump_val[i]), |
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le32_to_cpu(regdump_val[i + 1]), |
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le32_to_cpu(regdump_val[i + 2]), |
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le32_to_cpu(regdump_val[i + 3])); |
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} |
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} |
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static int ath6kl_hif_proc_dbg_intr(struct ath6kl_device *dev) |
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{ |
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u32 dummy; |
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int ret; |
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ath6kl_warn("firmware crashed\n"); |
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|
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/* |
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* read counter to clear the interrupt, the debug error interrupt is |
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* counter 0. |
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*/ |
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ret = hif_read_write_sync(dev->ar, COUNT_DEC_ADDRESS, |
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(u8 *)&dummy, 4, HIF_RD_SYNC_BYTE_INC); |
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if (ret) |
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ath6kl_warn("Failed to clear debug interrupt: %d\n", ret); |
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ath6kl_hif_dump_fw_crash(dev->ar); |
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ath6kl_read_fwlogs(dev->ar); |
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ath6kl_recovery_err_notify(dev->ar, ATH6KL_FW_ASSERT); |
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return ret; |
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} |
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/* mailbox recv message polling */ |
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int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd, |
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int timeout) |
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{ |
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struct ath6kl_irq_proc_registers *rg; |
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int status = 0, i; |
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u8 htc_mbox = 1 << HTC_MAILBOX; |
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for (i = timeout / ATH6KL_TIME_QUANTUM; i > 0; i--) { |
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/* this is the standard HIF way, load the reg table */ |
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status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, |
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(u8 *) &dev->irq_proc_reg, |
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sizeof(dev->irq_proc_reg), |
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HIF_RD_SYNC_BYTE_INC); |
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if (status) { |
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ath6kl_err("failed to read reg table\n"); |
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return status; |
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} |
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/* check for MBOX data and valid lookahead */ |
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if (dev->irq_proc_reg.host_int_status & htc_mbox) { |
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if (dev->irq_proc_reg.rx_lkahd_valid & |
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htc_mbox) { |
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/* |
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* Mailbox has a message and the look ahead |
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* is valid. |
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*/ |
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rg = &dev->irq_proc_reg; |
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*lk_ahd = |
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le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); |
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break; |
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} |
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} |
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/* delay a little */ |
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mdelay(ATH6KL_TIME_QUANTUM); |
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ath6kl_dbg(ATH6KL_DBG_HIF, "hif retry mbox poll try %d\n", i); |
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} |
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if (i == 0) { |
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ath6kl_err("timeout waiting for recv message\n"); |
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status = -ETIME; |
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/* check if the target asserted */ |
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if (dev->irq_proc_reg.counter_int_status & |
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ATH6KL_TARGET_DEBUG_INTR_MASK) |
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/* |
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* Target failure handler will be called in case of |
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* an assert. |
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*/ |
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ath6kl_hif_proc_dbg_intr(dev); |
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} |
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return status; |
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} |
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/* |
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* Disable packet reception (used in case the host runs out of buffers) |
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* using the interrupt enable registers through the host I/F |
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*/ |
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int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx) |
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{ |
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struct ath6kl_irq_enable_reg regs; |
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int status = 0; |
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ath6kl_dbg(ATH6KL_DBG_HIF, "hif rx %s\n", |
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enable_rx ? "enable" : "disable"); |
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|
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/* take the lock to protect interrupt enable shadows */ |
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spin_lock_bh(&dev->lock); |
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if (enable_rx) |
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dev->irq_en_reg.int_status_en |= |
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SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); |
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else |
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dev->irq_en_reg.int_status_en &= |
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~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); |
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memcpy(®s, &dev->irq_en_reg, sizeof(regs)); |
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spin_unlock_bh(&dev->lock); |
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status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, |
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®s.int_status_en, |
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sizeof(struct ath6kl_irq_enable_reg), |
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HIF_WR_SYNC_BYTE_INC); |
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return status; |
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} |
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int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev, |
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struct hif_scatter_req *scat_req, bool read) |
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{ |
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int status = 0; |
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if (read) { |
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scat_req->req = HIF_RD_SYNC_BLOCK_FIX; |
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scat_req->addr = dev->ar->mbox_info.htc_addr; |
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} else { |
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scat_req->req = HIF_WR_ASYNC_BLOCK_INC; |
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scat_req->addr = |
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(scat_req->len > HIF_MBOX_WIDTH) ? |
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dev->ar->mbox_info.htc_ext_addr : |
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dev->ar->mbox_info.htc_addr; |
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} |
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ath6kl_dbg(ATH6KL_DBG_HIF, |
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"hif submit scatter request entries %d len %d mbox 0x%x %s %s\n", |
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scat_req->scat_entries, scat_req->len, |
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scat_req->addr, !read ? "async" : "sync", |
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(read) ? "rd" : "wr"); |
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if (!read && scat_req->virt_scat) { |
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status = ath6kl_hif_cp_scat_dma_buf(scat_req, false); |
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if (status) { |
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scat_req->status = status; |
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scat_req->complete(dev->ar->htc_target, scat_req); |
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return 0; |
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} |
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} |
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status = ath6kl_hif_scat_req_rw(dev->ar, scat_req); |
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if (read) { |
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/* in sync mode, we can touch the scatter request */ |
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scat_req->status = status; |
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if (!status && scat_req->virt_scat) |
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scat_req->status = |
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ath6kl_hif_cp_scat_dma_buf(scat_req, true); |
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} |
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return status; |
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} |
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static int ath6kl_hif_proc_counter_intr(struct ath6kl_device *dev) |
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{ |
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u8 counter_int_status; |
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ath6kl_dbg(ATH6KL_DBG_IRQ, "counter interrupt\n"); |
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counter_int_status = dev->irq_proc_reg.counter_int_status & |
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dev->irq_en_reg.cntr_int_status_en; |
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ath6kl_dbg(ATH6KL_DBG_IRQ, |
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"valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n", |
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counter_int_status); |
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/* |
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* NOTE: other modules like GMBOX may use the counter interrupt for |
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* credit flow control on other counters, we only need to check for |
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* the debug assertion counter interrupt. |
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*/ |
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if (counter_int_status & ATH6KL_TARGET_DEBUG_INTR_MASK) |
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return ath6kl_hif_proc_dbg_intr(dev); |
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return 0; |
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} |
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static int ath6kl_hif_proc_err_intr(struct ath6kl_device *dev) |
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{ |
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int status; |
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u8 error_int_status; |
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u8 reg_buf[4]; |
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ath6kl_dbg(ATH6KL_DBG_IRQ, "error interrupt\n"); |
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error_int_status = dev->irq_proc_reg.error_int_status & 0x0F; |
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if (!error_int_status) { |
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WARN_ON(1); |
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return -EIO; |
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} |
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ath6kl_dbg(ATH6KL_DBG_IRQ, |
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"valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n", |
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error_int_status); |
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if (MS(ERROR_INT_STATUS_WAKEUP, error_int_status)) |
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ath6kl_dbg(ATH6KL_DBG_IRQ, "error : wakeup\n"); |
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if (MS(ERROR_INT_STATUS_RX_UNDERFLOW, error_int_status)) |
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ath6kl_err("rx underflow\n"); |
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if (MS(ERROR_INT_STATUS_TX_OVERFLOW, error_int_status)) |
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ath6kl_err("tx overflow\n"); |
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|
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/* Clear the interrupt */ |
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dev->irq_proc_reg.error_int_status &= ~error_int_status; |
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|
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/* set W1C value to clear the interrupt, this hits the register first */ |
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reg_buf[0] = error_int_status; |
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reg_buf[1] = 0; |
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reg_buf[2] = 0; |
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reg_buf[3] = 0; |
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status = hif_read_write_sync(dev->ar, ERROR_INT_STATUS_ADDRESS, |
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reg_buf, 4, HIF_WR_SYNC_BYTE_FIX); |
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|
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WARN_ON(status); |
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return status; |
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} |
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|
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static int ath6kl_hif_proc_cpu_intr(struct ath6kl_device *dev) |
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{ |
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int status; |
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u8 cpu_int_status; |
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u8 reg_buf[4]; |
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ath6kl_dbg(ATH6KL_DBG_IRQ, "cpu interrupt\n"); |
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cpu_int_status = dev->irq_proc_reg.cpu_int_status & |
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dev->irq_en_reg.cpu_int_status_en; |
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if (!cpu_int_status) { |
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WARN_ON(1); |
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return -EIO; |
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} |
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ath6kl_dbg(ATH6KL_DBG_IRQ, |
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"valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n", |
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cpu_int_status); |
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|
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/* Clear the interrupt */ |
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dev->irq_proc_reg.cpu_int_status &= ~cpu_int_status; |
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|
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/* |
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* Set up the register transfer buffer to hit the register 4 times , |
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* this is done to make the access 4-byte aligned to mitigate issues |
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* with host bus interconnects that restrict bus transfer lengths to |
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* be a multiple of 4-bytes. |
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*/ |
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|
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/* set W1C value to clear the interrupt, this hits the register first */ |
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reg_buf[0] = cpu_int_status; |
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/* the remaining are set to zero which have no-effect */ |
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reg_buf[1] = 0; |
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reg_buf[2] = 0; |
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reg_buf[3] = 0; |
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|
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status = hif_read_write_sync(dev->ar, CPU_INT_STATUS_ADDRESS, |
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reg_buf, 4, HIF_WR_SYNC_BYTE_FIX); |
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|
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WARN_ON(status); |
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|
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return status; |
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} |
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|
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/* process pending interrupts synchronously */ |
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static int proc_pending_irqs(struct ath6kl_device *dev, bool *done) |
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{ |
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struct ath6kl_irq_proc_registers *rg; |
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int status = 0; |
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u8 host_int_status = 0; |
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u32 lk_ahd = 0; |
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u8 htc_mbox = 1 << HTC_MAILBOX; |
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|
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ath6kl_dbg(ATH6KL_DBG_IRQ, "proc_pending_irqs: (dev: 0x%p)\n", dev); |
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|
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/* |
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* NOTE: HIF implementation guarantees that the context of this |
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* call allows us to perform SYNCHRONOUS I/O, that is we can block, |
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* sleep or call any API that can block or switch thread/task |
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* contexts. This is a fully schedulable context. |
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*/ |
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|
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/* |
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* Process pending intr only when int_status_en is clear, it may |
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* result in unnecessary bus transaction otherwise. Target may be |
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* unresponsive at the time. |
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*/ |
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if (dev->irq_en_reg.int_status_en) { |
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/* |
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* Read the first 28 bytes of the HTC register table. This |
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* will yield us the value of different int status |
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* registers and the lookahead registers. |
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* |
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* length = sizeof(int_status) + sizeof(cpu_int_status) |
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* + sizeof(error_int_status) + |
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* sizeof(counter_int_status) + |
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* sizeof(mbox_frame) + sizeof(rx_lkahd_valid) |
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* + sizeof(hole) + sizeof(rx_lkahd) + |
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* sizeof(int_status_en) + |
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* sizeof(cpu_int_status_en) + |
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* sizeof(err_int_status_en) + |
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* sizeof(cntr_int_status_en); |
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*/ |
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status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, |
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(u8 *) &dev->irq_proc_reg, |
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sizeof(dev->irq_proc_reg), |
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HIF_RD_SYNC_BYTE_INC); |
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if (status) |
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goto out; |
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|
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ath6kl_dump_registers(dev, &dev->irq_proc_reg, |
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&dev->irq_en_reg); |
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trace_ath6kl_sdio_irq(&dev->irq_en_reg, |
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sizeof(dev->irq_en_reg)); |
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|
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/* Update only those registers that are enabled */ |
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host_int_status = dev->irq_proc_reg.host_int_status & |
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dev->irq_en_reg.int_status_en; |
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|
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/* Look at mbox status */ |
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if (host_int_status & htc_mbox) { |
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/* |
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* Mask out pending mbox value, we use "lookAhead as |
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* the real flag for mbox processing. |
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*/ |
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host_int_status &= ~htc_mbox; |
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if (dev->irq_proc_reg.rx_lkahd_valid & |
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htc_mbox) { |
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rg = &dev->irq_proc_reg; |
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lk_ahd = le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); |
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if (!lk_ahd) |
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ath6kl_err("lookAhead is zero!\n"); |
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} |
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} |
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} |
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|
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if (!host_int_status && !lk_ahd) { |
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*done = true; |
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goto out; |
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} |
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|
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if (lk_ahd) { |
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int fetched = 0; |
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|
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ath6kl_dbg(ATH6KL_DBG_IRQ, |
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"pending mailbox msg, lk_ahd: 0x%X\n", lk_ahd); |
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/* |
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* Mailbox Interrupt, the HTC layer may issue async |
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* requests to empty the mailbox. When emptying the recv |
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* mailbox we use the async handler above called from the |
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* completion routine of the callers read request. This can |
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* improve performance by reducing context switching when |
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* we rapidly pull packets. |
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*/ |
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status = ath6kl_htc_rxmsg_pending_handler(dev->htc_cnxt, |
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lk_ahd, &fetched); |
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if (status) |
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goto out; |
|
|
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if (!fetched) |
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/* |
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* HTC could not pull any messages out due to lack |
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* of resources. |
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*/ |
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dev->htc_cnxt->chk_irq_status_cnt = 0; |
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} |
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|
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/* now handle the rest of them */ |
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ath6kl_dbg(ATH6KL_DBG_IRQ, |
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"valid interrupt source(s) for other interrupts: 0x%x\n", |
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host_int_status); |
|
|
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if (MS(HOST_INT_STATUS_CPU, host_int_status)) { |
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/* CPU Interrupt */ |
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status = ath6kl_hif_proc_cpu_intr(dev); |
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if (status) |
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goto out; |
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} |
|
|
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if (MS(HOST_INT_STATUS_ERROR, host_int_status)) { |
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/* Error Interrupt */ |
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status = ath6kl_hif_proc_err_intr(dev); |
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if (status) |
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goto out; |
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} |
|
|
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if (MS(HOST_INT_STATUS_COUNTER, host_int_status)) |
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/* Counter Interrupt */ |
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status = ath6kl_hif_proc_counter_intr(dev); |
|
|
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out: |
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/* |
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* An optimization to bypass reading the IRQ status registers |
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* unecessarily which can re-wake the target, if upper layers |
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* determine that we are in a low-throughput mode, we can rely on |
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* taking another interrupt rather than re-checking the status |
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* registers which can re-wake the target. |
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* |
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* NOTE : for host interfaces that makes use of detecting pending |
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* mbox messages at hif can not use this optimization due to |
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* possible side effects, SPI requires the host to drain all |
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* messages from the mailbox before exiting the ISR routine. |
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*/ |
|
|
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ath6kl_dbg(ATH6KL_DBG_IRQ, |
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"bypassing irq status re-check, forcing done\n"); |
|
|
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if (!dev->htc_cnxt->chk_irq_status_cnt) |
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*done = true; |
|
|
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ath6kl_dbg(ATH6KL_DBG_IRQ, |
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"proc_pending_irqs: (done:%d, status=%d\n", *done, status); |
|
|
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return status; |
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} |
|
|
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/* interrupt handler, kicks off all interrupt processing */ |
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int ath6kl_hif_intr_bh_handler(struct ath6kl *ar) |
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{ |
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struct ath6kl_device *dev = ar->htc_target->dev; |
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unsigned long timeout; |
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int status = 0; |
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bool done = false; |
|
|
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/* |
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* Reset counter used to flag a re-scan of IRQ status registers on |
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* the target. |
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*/ |
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dev->htc_cnxt->chk_irq_status_cnt = 0; |
|
|
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/* |
|
* IRQ processing is synchronous, interrupt status registers can be |
|
* re-read. |
|
*/ |
|
timeout = jiffies + msecs_to_jiffies(ATH6KL_HIF_COMMUNICATION_TIMEOUT); |
|
while (time_before(jiffies, timeout) && !done) { |
|
status = proc_pending_irqs(dev, &done); |
|
if (status) |
|
break; |
|
} |
|
|
|
return status; |
|
} |
|
EXPORT_SYMBOL(ath6kl_hif_intr_bh_handler); |
|
|
|
static int ath6kl_hif_enable_intrs(struct ath6kl_device *dev) |
|
{ |
|
struct ath6kl_irq_enable_reg regs; |
|
int status; |
|
|
|
spin_lock_bh(&dev->lock); |
|
|
|
/* Enable all but ATH6KL CPU interrupts */ |
|
dev->irq_en_reg.int_status_en = |
|
SM(INT_STATUS_ENABLE_ERROR, 0x01) | |
|
SM(INT_STATUS_ENABLE_CPU, 0x01) | |
|
SM(INT_STATUS_ENABLE_COUNTER, 0x01); |
|
|
|
/* |
|
* NOTE: There are some cases where HIF can do detection of |
|
* pending mbox messages which is disabled now. |
|
*/ |
|
dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); |
|
|
|
/* Set up the CPU Interrupt status Register */ |
|
dev->irq_en_reg.cpu_int_status_en = 0; |
|
|
|
/* Set up the Error Interrupt status Register */ |
|
dev->irq_en_reg.err_int_status_en = |
|
SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) | |
|
SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1); |
|
|
|
/* |
|
* Enable Counter interrupt status register to get fatal errors for |
|
* debugging. |
|
*/ |
|
dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT, |
|
ATH6KL_TARGET_DEBUG_INTR_MASK); |
|
memcpy(®s, &dev->irq_en_reg, sizeof(regs)); |
|
|
|
spin_unlock_bh(&dev->lock); |
|
|
|
status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, |
|
®s.int_status_en, sizeof(regs), |
|
HIF_WR_SYNC_BYTE_INC); |
|
|
|
if (status) |
|
ath6kl_err("failed to update interrupt ctl reg err: %d\n", |
|
status); |
|
|
|
return status; |
|
} |
|
|
|
int ath6kl_hif_disable_intrs(struct ath6kl_device *dev) |
|
{ |
|
struct ath6kl_irq_enable_reg regs; |
|
|
|
spin_lock_bh(&dev->lock); |
|
/* Disable all interrupts */ |
|
dev->irq_en_reg.int_status_en = 0; |
|
dev->irq_en_reg.cpu_int_status_en = 0; |
|
dev->irq_en_reg.err_int_status_en = 0; |
|
dev->irq_en_reg.cntr_int_status_en = 0; |
|
memcpy(®s, &dev->irq_en_reg, sizeof(regs)); |
|
spin_unlock_bh(&dev->lock); |
|
|
|
return hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, |
|
®s.int_status_en, sizeof(regs), |
|
HIF_WR_SYNC_BYTE_INC); |
|
} |
|
|
|
/* enable device interrupts */ |
|
int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev) |
|
{ |
|
int status = 0; |
|
|
|
/* |
|
* Make sure interrupt are disabled before unmasking at the HIF |
|
* layer. The rationale here is that between device insertion |
|
* (where we clear the interrupts the first time) and when HTC |
|
* is finally ready to handle interrupts, other software can perform |
|
* target "soft" resets. The ATH6KL interrupt enables reset back to an |
|
* "enabled" state when this happens. |
|
*/ |
|
ath6kl_hif_disable_intrs(dev); |
|
|
|
/* unmask the host controller interrupts */ |
|
ath6kl_hif_irq_enable(dev->ar); |
|
status = ath6kl_hif_enable_intrs(dev); |
|
|
|
return status; |
|
} |
|
|
|
/* disable all device interrupts */ |
|
int ath6kl_hif_mask_intrs(struct ath6kl_device *dev) |
|
{ |
|
/* |
|
* Mask the interrupt at the HIF layer to avoid any stray interrupt |
|
* taken while we zero out our shadow registers in |
|
* ath6kl_hif_disable_intrs(). |
|
*/ |
|
ath6kl_hif_irq_disable(dev->ar); |
|
|
|
return ath6kl_hif_disable_intrs(dev); |
|
} |
|
|
|
int ath6kl_hif_setup(struct ath6kl_device *dev) |
|
{ |
|
int status = 0; |
|
|
|
spin_lock_init(&dev->lock); |
|
|
|
/* |
|
* NOTE: we actually get the block size of a mailbox other than 0, |
|
* for SDIO the block size on mailbox 0 is artificially set to 1. |
|
* So we use the block size that is set for the other 3 mailboxes. |
|
*/ |
|
dev->htc_cnxt->block_sz = dev->ar->mbox_info.block_size; |
|
|
|
/* must be a power of 2 */ |
|
if ((dev->htc_cnxt->block_sz & (dev->htc_cnxt->block_sz - 1)) != 0) { |
|
WARN_ON(1); |
|
status = -EINVAL; |
|
goto fail_setup; |
|
} |
|
|
|
/* assemble mask, used for padding to a block */ |
|
dev->htc_cnxt->block_mask = dev->htc_cnxt->block_sz - 1; |
|
|
|
ath6kl_dbg(ATH6KL_DBG_HIF, "hif block size %d mbox addr 0x%x\n", |
|
dev->htc_cnxt->block_sz, dev->ar->mbox_info.htc_addr); |
|
|
|
status = ath6kl_hif_disable_intrs(dev); |
|
|
|
fail_setup: |
|
return status; |
|
}
|
|
|