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1011 lines
28 KiB
1011 lines
28 KiB
/* |
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* Copyright (c) 2004-2008 Reyk Floeter <[email protected]> |
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* Copyright (c) 2006-2008 Nick Kossifidis <[email protected]> |
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* Copyright (c) 2007-2008 Matthew W. S. Bell <[email protected]> |
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* Copyright (c) 2007-2008 Luis Rodriguez <[email protected]> |
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* Copyright (c) 2007-2008 Pavel Roskin <[email protected]> |
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* Copyright (c) 2007-2008 Jiri Slaby <[email protected]> |
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* |
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* Permission to use, copy, modify, and distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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* |
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*/ |
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|
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/*********************************\ |
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* Protocol Control Unit Functions * |
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\*********************************/ |
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|
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#include <asm/unaligned.h> |
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|
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#include "ath5k.h" |
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#include "reg.h" |
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#include "debug.h" |
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|
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/** |
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* DOC: Protocol Control Unit (PCU) functions |
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* |
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* Protocol control unit is responsible to maintain various protocol |
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* properties before a frame is send and after a frame is received to/from |
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* baseband. To be more specific, PCU handles: |
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* |
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* - Buffering of RX and TX frames (after QCU/DCUs) |
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* |
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* - Encrypting and decrypting (using the built-in engine) |
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* |
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* - Generating ACKs, RTS/CTS frames |
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* |
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* - Maintaining TSF |
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* |
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* - FCS |
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* |
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* - Updating beacon data (with TSF etc) |
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* |
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* - Generating virtual CCA |
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* |
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* - RX/Multicast filtering |
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* |
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* - BSSID filtering |
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* |
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* - Various statistics |
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* |
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* -Different operating modes: AP, STA, IBSS |
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* |
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* Note: Most of these functions can be tweaked/bypassed so you can do |
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* them on sw above for debugging or research. For more infos check out PCU |
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* registers on reg.h. |
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*/ |
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|
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/** |
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* DOC: ACK rates |
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* |
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* AR5212+ can use higher rates for ack transmission |
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* based on current tx rate instead of the base rate. |
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* It does this to better utilize channel usage. |
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* There is a mapping between G rates (that cover both |
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* CCK and OFDM) and ack rates that we use when setting |
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* rate -> duration table. This mapping is hw-based so |
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* don't change anything. |
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* |
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* To enable this functionality we must set |
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* ah->ah_ack_bitrate_high to true else base rate is |
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* used (1Mb for CCK, 6Mb for OFDM). |
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*/ |
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static const unsigned int ack_rates_high[] = |
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/* Tx -> ACK */ |
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/* 1Mb -> 1Mb */ { 0, |
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/* 2MB -> 2Mb */ 1, |
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/* 5.5Mb -> 2Mb */ 1, |
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/* 11Mb -> 2Mb */ 1, |
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/* 6Mb -> 6Mb */ 4, |
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/* 9Mb -> 6Mb */ 4, |
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/* 12Mb -> 12Mb */ 6, |
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/* 18Mb -> 12Mb */ 6, |
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/* 24Mb -> 24Mb */ 8, |
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/* 36Mb -> 24Mb */ 8, |
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/* 48Mb -> 24Mb */ 8, |
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/* 54Mb -> 24Mb */ 8 }; |
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|
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/*******************\ |
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* Helper functions * |
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\*******************/ |
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|
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/** |
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* ath5k_hw_get_frame_duration() - Get tx time of a frame |
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* @ah: The &struct ath5k_hw |
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* @band: One of enum nl80211_band |
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* @len: Frame's length in bytes |
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* @rate: The @struct ieee80211_rate |
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* @shortpre: Indicate short preample |
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* |
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* Calculate tx duration of a frame given it's rate and length |
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* It extends ieee80211_generic_frame_duration for non standard |
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* bwmodes. |
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*/ |
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int |
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ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum nl80211_band band, |
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int len, struct ieee80211_rate *rate, bool shortpre) |
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{ |
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int sifs, preamble, plcp_bits, sym_time; |
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int bitrate, bits, symbols, symbol_bits; |
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int dur; |
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|
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/* Fallback */ |
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if (!ah->ah_bwmode) { |
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__le16 raw_dur = ieee80211_generic_frame_duration(ah->hw, |
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NULL, band, len, rate); |
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|
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/* subtract difference between long and short preamble */ |
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dur = le16_to_cpu(raw_dur); |
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if (shortpre) |
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dur -= 96; |
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return dur; |
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} |
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bitrate = rate->bitrate; |
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preamble = AR5K_INIT_OFDM_PREAMPLE_TIME; |
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plcp_bits = AR5K_INIT_OFDM_PLCP_BITS; |
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sym_time = AR5K_INIT_OFDM_SYMBOL_TIME; |
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|
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switch (ah->ah_bwmode) { |
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case AR5K_BWMODE_40MHZ: |
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sifs = AR5K_INIT_SIFS_TURBO; |
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preamble = AR5K_INIT_OFDM_PREAMBLE_TIME_MIN; |
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break; |
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case AR5K_BWMODE_10MHZ: |
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sifs = AR5K_INIT_SIFS_HALF_RATE; |
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preamble *= 2; |
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sym_time *= 2; |
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bitrate = DIV_ROUND_UP(bitrate, 2); |
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break; |
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case AR5K_BWMODE_5MHZ: |
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sifs = AR5K_INIT_SIFS_QUARTER_RATE; |
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preamble *= 4; |
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sym_time *= 4; |
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bitrate = DIV_ROUND_UP(bitrate, 4); |
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break; |
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default: |
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sifs = AR5K_INIT_SIFS_DEFAULT_BG; |
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break; |
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} |
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bits = plcp_bits + (len << 3); |
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/* Bit rate is in 100Kbits */ |
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symbol_bits = bitrate * sym_time; |
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symbols = DIV_ROUND_UP(bits * 10, symbol_bits); |
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dur = sifs + preamble + (sym_time * symbols); |
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return dur; |
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} |
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/** |
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* ath5k_hw_get_default_slottime() - Get the default slot time for current mode |
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* @ah: The &struct ath5k_hw |
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*/ |
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unsigned int |
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ath5k_hw_get_default_slottime(struct ath5k_hw *ah) |
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{ |
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struct ieee80211_channel *channel = ah->ah_current_channel; |
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unsigned int slot_time; |
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|
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switch (ah->ah_bwmode) { |
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case AR5K_BWMODE_40MHZ: |
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slot_time = AR5K_INIT_SLOT_TIME_TURBO; |
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break; |
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case AR5K_BWMODE_10MHZ: |
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slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE; |
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break; |
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case AR5K_BWMODE_5MHZ: |
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slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE; |
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break; |
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case AR5K_BWMODE_DEFAULT: |
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default: |
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slot_time = AR5K_INIT_SLOT_TIME_DEFAULT; |
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if ((channel->hw_value == AR5K_MODE_11B) && !ah->ah_short_slot) |
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slot_time = AR5K_INIT_SLOT_TIME_B; |
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break; |
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} |
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return slot_time; |
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} |
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|
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/** |
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* ath5k_hw_get_default_sifs() - Get the default SIFS for current mode |
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* @ah: The &struct ath5k_hw |
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*/ |
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unsigned int |
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ath5k_hw_get_default_sifs(struct ath5k_hw *ah) |
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{ |
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struct ieee80211_channel *channel = ah->ah_current_channel; |
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unsigned int sifs; |
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|
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switch (ah->ah_bwmode) { |
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case AR5K_BWMODE_40MHZ: |
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sifs = AR5K_INIT_SIFS_TURBO; |
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break; |
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case AR5K_BWMODE_10MHZ: |
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sifs = AR5K_INIT_SIFS_HALF_RATE; |
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break; |
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case AR5K_BWMODE_5MHZ: |
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sifs = AR5K_INIT_SIFS_QUARTER_RATE; |
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break; |
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case AR5K_BWMODE_DEFAULT: |
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default: |
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sifs = AR5K_INIT_SIFS_DEFAULT_BG; |
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if (channel->band == NL80211_BAND_5GHZ) |
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sifs = AR5K_INIT_SIFS_DEFAULT_A; |
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break; |
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} |
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return sifs; |
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} |
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/** |
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* ath5k_hw_update_mib_counters() - Update MIB counters (mac layer statistics) |
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* @ah: The &struct ath5k_hw |
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* |
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* Reads MIB counters from PCU and updates sw statistics. Is called after a |
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* MIB interrupt, because one of these counters might have reached their maximum |
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* and triggered the MIB interrupt, to let us read and clear the counter. |
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* |
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* NOTE: Is called in interrupt context! |
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*/ |
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void |
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ath5k_hw_update_mib_counters(struct ath5k_hw *ah) |
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{ |
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struct ath5k_statistics *stats = &ah->stats; |
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|
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/* Read-And-Clear */ |
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stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); |
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stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL); |
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stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK); |
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stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL); |
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stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT); |
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} |
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/******************\ |
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* ACK/CTS Timeouts * |
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\******************/ |
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/** |
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* ath5k_hw_write_rate_duration() - Fill rate code to duration table |
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* @ah: The &struct ath5k_hw |
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* |
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* Write the rate code to duration table upon hw reset. This is a helper for |
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* ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on |
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* the hardware, based on current mode, for each rate. The rates which are |
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* capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have |
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* different rate code so we write their value twice (one for long preamble |
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* and one for short). |
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* |
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* Note: Band doesn't matter here, if we set the values for OFDM it works |
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* on both a and g modes. So all we have to do is set values for all g rates |
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* that include all OFDM and CCK rates. |
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* |
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*/ |
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static inline void |
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ath5k_hw_write_rate_duration(struct ath5k_hw *ah) |
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{ |
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struct ieee80211_rate *rate; |
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unsigned int i; |
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/* 802.11g covers both OFDM and CCK */ |
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u8 band = NL80211_BAND_2GHZ; |
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|
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/* Write rate duration table */ |
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for (i = 0; i < ah->sbands[band].n_bitrates; i++) { |
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u32 reg; |
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u16 tx_time; |
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if (ah->ah_ack_bitrate_high) |
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rate = &ah->sbands[band].bitrates[ack_rates_high[i]]; |
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/* CCK -> 1Mb */ |
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else if (i < 4) |
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rate = &ah->sbands[band].bitrates[0]; |
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/* OFDM -> 6Mb */ |
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else |
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rate = &ah->sbands[band].bitrates[4]; |
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|
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/* Set ACK timeout */ |
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reg = AR5K_RATE_DUR(rate->hw_value); |
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|
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/* An ACK frame consists of 10 bytes. If you add the FCS, |
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* which ieee80211_generic_frame_duration() adds, |
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* its 14 bytes. Note we use the control rate and not the |
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* actual rate for this rate. See mac80211 tx.c |
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* ieee80211_duration() for a brief description of |
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* what rate we should choose to TX ACKs. */ |
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tx_time = ath5k_hw_get_frame_duration(ah, band, 10, |
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rate, false); |
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ath5k_hw_reg_write(ah, tx_time, reg); |
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|
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if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE)) |
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continue; |
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tx_time = ath5k_hw_get_frame_duration(ah, band, 10, rate, true); |
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ath5k_hw_reg_write(ah, tx_time, |
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reg + (AR5K_SET_SHORT_PREAMBLE << 2)); |
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} |
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} |
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/** |
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* ath5k_hw_set_ack_timeout() - Set ACK timeout on PCU |
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* @ah: The &struct ath5k_hw |
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* @timeout: Timeout in usec |
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*/ |
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static int |
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ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout) |
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{ |
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if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK)) |
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<= timeout) |
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return -EINVAL; |
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AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, |
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ath5k_hw_htoclock(ah, timeout)); |
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return 0; |
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} |
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/** |
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* ath5k_hw_set_cts_timeout() - Set CTS timeout on PCU |
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* @ah: The &struct ath5k_hw |
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* @timeout: Timeout in usec |
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*/ |
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static int |
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ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout) |
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{ |
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if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS)) |
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<= timeout) |
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return -EINVAL; |
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AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, |
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ath5k_hw_htoclock(ah, timeout)); |
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return 0; |
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} |
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/*******************\ |
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* RX filter Control * |
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\*******************/ |
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/** |
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* ath5k_hw_set_lladdr() - Set station id |
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* @ah: The &struct ath5k_hw |
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* @mac: The card's mac address (array of octets) |
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* |
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* Set station id on hw using the provided mac address |
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*/ |
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int |
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ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac) |
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{ |
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struct ath_common *common = ath5k_hw_common(ah); |
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u32 low_id, high_id; |
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u32 pcu_reg; |
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|
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/* Set new station ID */ |
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memcpy(common->macaddr, mac, ETH_ALEN); |
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|
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pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; |
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low_id = get_unaligned_le32(mac); |
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high_id = get_unaligned_le16(mac + 4); |
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ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); |
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ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); |
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|
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return 0; |
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} |
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|
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/** |
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* ath5k_hw_set_bssid() - Set current BSSID on hw |
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* @ah: The &struct ath5k_hw |
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* |
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* Sets the current BSSID and BSSID mask we have from the |
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* common struct into the hardware |
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*/ |
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void |
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ath5k_hw_set_bssid(struct ath5k_hw *ah) |
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{ |
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struct ath_common *common = ath5k_hw_common(ah); |
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u16 tim_offset = 0; |
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|
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/* |
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* Set BSSID mask on 5212 |
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*/ |
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if (ah->ah_version == AR5K_AR5212) |
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ath_hw_setbssidmask(common); |
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|
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/* |
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* Set BSSID |
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*/ |
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ath5k_hw_reg_write(ah, |
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get_unaligned_le32(common->curbssid), |
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AR5K_BSS_ID0); |
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ath5k_hw_reg_write(ah, |
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get_unaligned_le16(common->curbssid + 4) | |
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((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S), |
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AR5K_BSS_ID1); |
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|
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if (common->curaid == 0) { |
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ath5k_hw_disable_pspoll(ah); |
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return; |
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} |
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|
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AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM, |
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tim_offset ? tim_offset + 4 : 0); |
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|
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ath5k_hw_enable_pspoll(ah, NULL, 0); |
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} |
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|
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/** |
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* ath5k_hw_set_bssid_mask() - Filter out bssids we listen |
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* @ah: The &struct ath5k_hw |
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* @mask: The BSSID mask to set (array of octets) |
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* |
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* BSSID masking is a method used by AR5212 and newer hardware to inform PCU |
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* which bits of the interface's MAC address should be looked at when trying |
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* to decide which packets to ACK. In station mode and AP mode with a single |
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* BSS every bit matters since we lock to only one BSS. In AP mode with |
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* multiple BSSes (virtual interfaces) not every bit matters because hw must |
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* accept frames for all BSSes and so we tweak some bits of our mac address |
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* in order to have multiple BSSes. |
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* |
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* For more information check out ../hw.c of the common ath module. |
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*/ |
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void |
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ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask) |
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{ |
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struct ath_common *common = ath5k_hw_common(ah); |
|
|
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/* Cache bssid mask so that we can restore it |
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* on reset */ |
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memcpy(common->bssidmask, mask, ETH_ALEN); |
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if (ah->ah_version == AR5K_AR5212) |
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ath_hw_setbssidmask(common); |
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} |
|
|
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/** |
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* ath5k_hw_set_mcast_filter() - Set multicast filter |
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* @ah: The &struct ath5k_hw |
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* @filter0: Lower 32bits of muticast filter |
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* @filter1: Higher 16bits of multicast filter |
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*/ |
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void |
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ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1) |
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{ |
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ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); |
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ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); |
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} |
|
|
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/** |
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* ath5k_hw_get_rx_filter() - Get current rx filter |
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* @ah: The &struct ath5k_hw |
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* |
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* Returns the RX filter by reading rx filter and |
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* phy error filter registers. RX filter is used |
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* to set the allowed frame types that PCU will accept |
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* and pass to the driver. For a list of frame types |
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* check out reg.h. |
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*/ |
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u32 |
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ath5k_hw_get_rx_filter(struct ath5k_hw *ah) |
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{ |
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u32 data, filter = 0; |
|
|
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filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); |
|
|
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/*Radar detection for 5212*/ |
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if (ah->ah_version == AR5K_AR5212) { |
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data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); |
|
|
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if (data & AR5K_PHY_ERR_FIL_RADAR) |
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filter |= AR5K_RX_FILTER_RADARERR; |
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if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) |
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filter |= AR5K_RX_FILTER_PHYERR; |
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} |
|
|
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return filter; |
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} |
|
|
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/** |
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* ath5k_hw_set_rx_filter() - Set rx filter |
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* @ah: The &struct ath5k_hw |
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* @filter: RX filter mask (see reg.h) |
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* |
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* Sets RX filter register and also handles PHY error filter |
|
* register on 5212 and newer chips so that we have proper PHY |
|
* error reporting. |
|
*/ |
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void |
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ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter) |
|
{ |
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u32 data = 0; |
|
|
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/* Set PHY error filter register on 5212*/ |
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if (ah->ah_version == AR5K_AR5212) { |
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if (filter & AR5K_RX_FILTER_RADARERR) |
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data |= AR5K_PHY_ERR_FIL_RADAR; |
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if (filter & AR5K_RX_FILTER_PHYERR) |
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data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; |
|
} |
|
|
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/* |
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* The AR5210 uses promiscuous mode to detect radar activity |
|
*/ |
|
if (ah->ah_version == AR5K_AR5210 && |
|
(filter & AR5K_RX_FILTER_RADARERR)) { |
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filter &= ~AR5K_RX_FILTER_RADARERR; |
|
filter |= AR5K_RX_FILTER_PROM; |
|
} |
|
|
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/*Zero length DMA (phy error reporting) */ |
|
if (data) |
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AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); |
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else |
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AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); |
|
|
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/*Write RX Filter register*/ |
|
ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); |
|
|
|
/*Write PHY error filter register on 5212*/ |
|
if (ah->ah_version == AR5K_AR5212) |
|
ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); |
|
|
|
} |
|
|
|
|
|
/****************\ |
|
* Beacon control * |
|
\****************/ |
|
|
|
#define ATH5K_MAX_TSF_READ 10 |
|
|
|
/** |
|
* ath5k_hw_get_tsf64() - Get the full 64bit TSF |
|
* @ah: The &struct ath5k_hw |
|
* |
|
* Returns the current TSF |
|
*/ |
|
u64 |
|
ath5k_hw_get_tsf64(struct ath5k_hw *ah) |
|
{ |
|
u32 tsf_lower, tsf_upper1, tsf_upper2; |
|
int i; |
|
unsigned long flags; |
|
|
|
/* This code is time critical - we don't want to be interrupted here */ |
|
local_irq_save(flags); |
|
|
|
/* |
|
* While reading TSF upper and then lower part, the clock is still |
|
* counting (or jumping in case of IBSS merge) so we might get |
|
* inconsistent values. To avoid this, we read the upper part again |
|
* and check it has not been changed. We make the hypothesis that a |
|
* maximum of 3 changes can happens in a row (we use 10 as a safe |
|
* value). |
|
* |
|
* Impact on performance is pretty small, since in most cases, only |
|
* 3 register reads are needed. |
|
*/ |
|
|
|
tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); |
|
for (i = 0; i < ATH5K_MAX_TSF_READ; i++) { |
|
tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32); |
|
tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32); |
|
if (tsf_upper2 == tsf_upper1) |
|
break; |
|
tsf_upper1 = tsf_upper2; |
|
} |
|
|
|
local_irq_restore(flags); |
|
|
|
WARN_ON(i == ATH5K_MAX_TSF_READ); |
|
|
|
return ((u64)tsf_upper1 << 32) | tsf_lower; |
|
} |
|
|
|
#undef ATH5K_MAX_TSF_READ |
|
|
|
/** |
|
* ath5k_hw_set_tsf64() - Set a new 64bit TSF |
|
* @ah: The &struct ath5k_hw |
|
* @tsf64: The new 64bit TSF |
|
* |
|
* Sets the new TSF |
|
*/ |
|
void |
|
ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64) |
|
{ |
|
ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32); |
|
ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32); |
|
} |
|
|
|
/** |
|
* ath5k_hw_reset_tsf() - Force a TSF reset |
|
* @ah: The &struct ath5k_hw |
|
* |
|
* Forces a TSF reset on PCU |
|
*/ |
|
void |
|
ath5k_hw_reset_tsf(struct ath5k_hw *ah) |
|
{ |
|
u32 val; |
|
|
|
val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF; |
|
|
|
/* |
|
* Each write to the RESET_TSF bit toggles a hardware internal |
|
* signal to reset TSF, but if left high it will cause a TSF reset |
|
* on the next chip reset as well. Thus we always write the value |
|
* twice to clear the signal. |
|
*/ |
|
ath5k_hw_reg_write(ah, val, AR5K_BEACON); |
|
ath5k_hw_reg_write(ah, val, AR5K_BEACON); |
|
} |
|
|
|
/** |
|
* ath5k_hw_init_beacon_timers() - Initialize beacon timers |
|
* @ah: The &struct ath5k_hw |
|
* @next_beacon: Next TBTT |
|
* @interval: Current beacon interval |
|
* |
|
* This function is used to initialize beacon timers based on current |
|
* operation mode and settings. |
|
*/ |
|
void |
|
ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval) |
|
{ |
|
u32 timer1, timer2, timer3; |
|
|
|
/* |
|
* Set the additional timers by mode |
|
*/ |
|
switch (ah->opmode) { |
|
case NL80211_IFTYPE_MONITOR: |
|
case NL80211_IFTYPE_STATION: |
|
/* In STA mode timer1 is used as next wakeup |
|
* timer and timer2 as next CFP duration start |
|
* timer. Both in 1/8TUs. */ |
|
/* TODO: PCF handling */ |
|
if (ah->ah_version == AR5K_AR5210) { |
|
timer1 = 0xffffffff; |
|
timer2 = 0xffffffff; |
|
} else { |
|
timer1 = 0x0000ffff; |
|
timer2 = 0x0007ffff; |
|
} |
|
/* Mark associated AP as PCF incapable for now */ |
|
AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF); |
|
break; |
|
case NL80211_IFTYPE_ADHOC: |
|
AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM); |
|
fallthrough; |
|
default: |
|
/* On non-STA modes timer1 is used as next DMA |
|
* beacon alert (DBA) timer and timer2 as next |
|
* software beacon alert. Both in 1/8TUs. */ |
|
timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3; |
|
timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3; |
|
break; |
|
} |
|
|
|
/* Timer3 marks the end of our ATIM window |
|
* a zero length window is not allowed because |
|
* we 'll get no beacons */ |
|
timer3 = next_beacon + 1; |
|
|
|
/* |
|
* Set the beacon register and enable all timers. |
|
*/ |
|
/* When in AP or Mesh Point mode zero timer0 to start TSF */ |
|
if (ah->opmode == NL80211_IFTYPE_AP || |
|
ah->opmode == NL80211_IFTYPE_MESH_POINT) |
|
ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); |
|
|
|
ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); |
|
ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1); |
|
ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2); |
|
ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3); |
|
|
|
/* Force a TSF reset if requested and enable beacons */ |
|
if (interval & AR5K_BEACON_RESET_TSF) |
|
ath5k_hw_reset_tsf(ah); |
|
|
|
ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD | |
|
AR5K_BEACON_ENABLE), |
|
AR5K_BEACON); |
|
|
|
/* Flush any pending BMISS interrupts on ISR by |
|
* performing a clear-on-write operation on PISR |
|
* register for the BMISS bit (writing a bit on |
|
* ISR toggles a reset for that bit and leaves |
|
* the remaining bits intact) */ |
|
if (ah->ah_version == AR5K_AR5210) |
|
ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR); |
|
else |
|
ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); |
|
|
|
/* TODO: Set enhanced sleep registers on AR5212 |
|
* based on vif->bss_conf params, until then |
|
* disable power save reporting.*/ |
|
AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); |
|
|
|
} |
|
|
|
/** |
|
* ath5k_check_timer_win() - Check if timer B is timer A + window |
|
* @a: timer a (before b) |
|
* @b: timer b (after a) |
|
* @window: difference between a and b |
|
* @intval: timers are increased by this interval |
|
* |
|
* This helper function checks if timer B is timer A + window and covers |
|
* cases where timer A or B might have already been updated or wrapped |
|
* around (Timers are 16 bit). |
|
* |
|
* Returns true if O.K. |
|
*/ |
|
static inline bool |
|
ath5k_check_timer_win(int a, int b, int window, int intval) |
|
{ |
|
/* |
|
* 1.) usually B should be A + window |
|
* 2.) A already updated, B not updated yet |
|
* 3.) A already updated and has wrapped around |
|
* 4.) B has wrapped around |
|
*/ |
|
if ((b - a == window) || /* 1.) */ |
|
(a - b == intval - window) || /* 2.) */ |
|
((a | 0x10000) - b == intval - window) || /* 3.) */ |
|
((b | 0x10000) - a == window)) /* 4.) */ |
|
return true; /* O.K. */ |
|
return false; |
|
} |
|
|
|
/** |
|
* ath5k_hw_check_beacon_timers() - Check if the beacon timers are correct |
|
* @ah: The &struct ath5k_hw |
|
* @intval: beacon interval |
|
* |
|
* This is a workaround for IBSS mode |
|
* |
|
* The need for this function arises from the fact that we have 4 separate |
|
* HW timer registers (TIMER0 - TIMER3), which are closely related to the |
|
* next beacon target time (NBTT), and that the HW updates these timers |
|
* separately based on the current TSF value. The hardware increments each |
|
* timer by the beacon interval, when the local TSF converted to TU is equal |
|
* to the value stored in the timer. |
|
* |
|
* The reception of a beacon with the same BSSID can update the local HW TSF |
|
* at any time - this is something we can't avoid. If the TSF jumps to a |
|
* time which is later than the time stored in a timer, this timer will not |
|
* be updated until the TSF in TU wraps around at 16 bit (the size of the |
|
* timers) and reaches the time which is stored in the timer. |
|
* |
|
* The problem is that these timers are closely related to TIMER0 (NBTT) and |
|
* that they define a time "window". When the TSF jumps between two timers |
|
* (e.g. ATIM and NBTT), the one in the past will be left behind (not |
|
* updated), while the one in the future will be updated every beacon |
|
* interval. This causes the window to get larger, until the TSF wraps |
|
* around as described above and the timer which was left behind gets |
|
* updated again. But - because the beacon interval is usually not an exact |
|
* divisor of the size of the timers (16 bit), an unwanted "window" between |
|
* these timers has developed! |
|
* |
|
* This is especially important with the ATIM window, because during |
|
* the ATIM window only ATIM frames and no data frames are allowed to be |
|
* sent, which creates transmission pauses after each beacon. This symptom |
|
* has been described as "ramping ping" because ping times increase linearly |
|
* for some time and then drop down again. A wrong window on the DMA beacon |
|
* timer has the same effect, so we check for these two conditions. |
|
* |
|
* Returns true if O.K. |
|
*/ |
|
bool |
|
ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval) |
|
{ |
|
unsigned int nbtt, atim, dma; |
|
|
|
nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0); |
|
atim = ath5k_hw_reg_read(ah, AR5K_TIMER3); |
|
dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3; |
|
|
|
/* NOTE: SWBA is different. Having a wrong window there does not |
|
* stop us from sending data and this condition is caught by |
|
* other means (SWBA interrupt) */ |
|
|
|
if (ath5k_check_timer_win(nbtt, atim, 1, intval) && |
|
ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP, |
|
intval)) |
|
return true; /* O.K. */ |
|
return false; |
|
} |
|
|
|
/** |
|
* ath5k_hw_set_coverage_class() - Set IEEE 802.11 coverage class |
|
* @ah: The &struct ath5k_hw |
|
* @coverage_class: IEEE 802.11 coverage class number |
|
* |
|
* Sets IFS intervals and ACK/CTS timeouts for given coverage class. |
|
*/ |
|
void |
|
ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class) |
|
{ |
|
/* As defined by IEEE 802.11-2007 17.3.8.6 */ |
|
int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class; |
|
int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time; |
|
int cts_timeout = ack_timeout; |
|
|
|
ath5k_hw_set_ifs_intervals(ah, slot_time); |
|
ath5k_hw_set_ack_timeout(ah, ack_timeout); |
|
ath5k_hw_set_cts_timeout(ah, cts_timeout); |
|
|
|
ah->ah_coverage_class = coverage_class; |
|
} |
|
|
|
/***************************\ |
|
* Init/Start/Stop functions * |
|
\***************************/ |
|
|
|
/** |
|
* ath5k_hw_start_rx_pcu() - Start RX engine |
|
* @ah: The &struct ath5k_hw |
|
* |
|
* Starts RX engine on PCU so that hw can process RXed frames |
|
* (ACK etc). |
|
* |
|
* NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma |
|
*/ |
|
void |
|
ath5k_hw_start_rx_pcu(struct ath5k_hw *ah) |
|
{ |
|
AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); |
|
} |
|
|
|
/** |
|
* ath5k_hw_stop_rx_pcu() - Stop RX engine |
|
* @ah: The &struct ath5k_hw |
|
* |
|
* Stops RX engine on PCU |
|
*/ |
|
void |
|
ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah) |
|
{ |
|
AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); |
|
} |
|
|
|
/** |
|
* ath5k_hw_set_opmode() - Set PCU operating mode |
|
* @ah: The &struct ath5k_hw |
|
* @op_mode: One of enum nl80211_iftype |
|
* |
|
* Configure PCU for the various operating modes (AP/STA etc) |
|
*/ |
|
int |
|
ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode) |
|
{ |
|
struct ath_common *common = ath5k_hw_common(ah); |
|
u32 pcu_reg, beacon_reg, low_id, high_id; |
|
|
|
ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode); |
|
|
|
/* Preserve rest settings */ |
|
pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; |
|
pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP |
|
| AR5K_STA_ID1_KEYSRCH_MODE |
|
| (ah->ah_version == AR5K_AR5210 ? |
|
(AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0)); |
|
|
|
beacon_reg = 0; |
|
|
|
switch (op_mode) { |
|
case NL80211_IFTYPE_ADHOC: |
|
pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE; |
|
beacon_reg |= AR5K_BCR_ADHOC; |
|
if (ah->ah_version == AR5K_AR5210) |
|
pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; |
|
else |
|
AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); |
|
break; |
|
|
|
case NL80211_IFTYPE_AP: |
|
case NL80211_IFTYPE_MESH_POINT: |
|
pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE; |
|
beacon_reg |= AR5K_BCR_AP; |
|
if (ah->ah_version == AR5K_AR5210) |
|
pcu_reg |= AR5K_STA_ID1_NO_PSPOLL; |
|
else |
|
AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS); |
|
break; |
|
|
|
case NL80211_IFTYPE_STATION: |
|
pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE |
|
| (ah->ah_version == AR5K_AR5210 ? |
|
AR5K_STA_ID1_PWR_SV : 0); |
|
fallthrough; |
|
case NL80211_IFTYPE_MONITOR: |
|
pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE |
|
| (ah->ah_version == AR5K_AR5210 ? |
|
AR5K_STA_ID1_NO_PSPOLL : 0); |
|
break; |
|
|
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
/* |
|
* Set PCU registers |
|
*/ |
|
low_id = get_unaligned_le32(common->macaddr); |
|
high_id = get_unaligned_le16(common->macaddr + 4); |
|
ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); |
|
ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); |
|
|
|
/* |
|
* Set Beacon Control Register on 5210 |
|
*/ |
|
if (ah->ah_version == AR5K_AR5210) |
|
ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* ath5k_hw_pcu_init() - Initialize PCU |
|
* @ah: The &struct ath5k_hw |
|
* @op_mode: One of enum nl80211_iftype |
|
* |
|
* This function is used to initialize PCU by setting current |
|
* operation mode and various other settings. |
|
*/ |
|
void |
|
ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode) |
|
{ |
|
/* Set bssid and bssid mask */ |
|
ath5k_hw_set_bssid(ah); |
|
|
|
/* Set PCU config */ |
|
ath5k_hw_set_opmode(ah, op_mode); |
|
|
|
/* Write rate duration table only on AR5212 and if |
|
* virtual interface has already been brought up |
|
* XXX: rethink this after new mode changes to |
|
* mac80211 are integrated */ |
|
if (ah->ah_version == AR5K_AR5212 && |
|
ah->nvifs) |
|
ath5k_hw_write_rate_duration(ah); |
|
|
|
/* Set RSSI/BRSSI thresholds |
|
* |
|
* Note: If we decide to set this value |
|
* dynamically, have in mind that when AR5K_RSSI_THR |
|
* register is read it might return 0x40 if we haven't |
|
* wrote anything to it plus BMISS RSSI threshold is zeroed. |
|
* So doing a save/restore procedure here isn't the right |
|
* choice. Instead store it on ath5k_hw */ |
|
ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | |
|
AR5K_TUNE_BMISS_THRES << |
|
AR5K_RSSI_THR_BMISS_S), |
|
AR5K_RSSI_THR); |
|
|
|
/* MIC QoS support */ |
|
if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { |
|
ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); |
|
ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); |
|
} |
|
|
|
/* QoS NOACK Policy */ |
|
if (ah->ah_version == AR5K_AR5212) { |
|
ath5k_hw_reg_write(ah, |
|
AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | |
|
AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | |
|
AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), |
|
AR5K_QOS_NOACK); |
|
} |
|
|
|
/* Restore slot time and ACK timeouts */ |
|
if (ah->ah_coverage_class > 0) |
|
ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class); |
|
|
|
/* Set ACK bitrate mode (see ack_rates_high) */ |
|
if (ah->ah_version == AR5K_AR5212) { |
|
u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; |
|
if (ah->ah_ack_bitrate_high) |
|
AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); |
|
else |
|
AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); |
|
} |
|
return; |
|
}
|
|
|