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879 lines
21 KiB
879 lines
21 KiB
// SPDX-License-Identifier: ISC |
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/* |
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* Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved. |
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* Copyright (c) 2015 The Linux Foundation. All rights reserved. |
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*/ |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/clk.h> |
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#include <linux/reset.h> |
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#include "core.h" |
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#include "debug.h" |
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#include "pci.h" |
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#include "ahb.h" |
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static const struct of_device_id ath10k_ahb_of_match[] = { |
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{ .compatible = "qcom,ipq4019-wifi", |
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.data = (void *)ATH10K_HW_QCA4019 |
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}, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, ath10k_ahb_of_match); |
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#define QCA4019_SRAM_ADDR 0x000C0000 |
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#define QCA4019_SRAM_LEN 0x00040000 /* 256 kb */ |
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static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar) |
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{ |
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return &((struct ath10k_pci *)ar->drv_priv)->ahb[0]; |
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} |
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static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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iowrite32(value, ar_ahb->mem + offset); |
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} |
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static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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return ioread32(ar_ahb->mem + offset); |
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} |
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static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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return ioread32(ar_ahb->gcc_mem + offset); |
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} |
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static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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iowrite32(value, ar_ahb->tcsr_mem + offset); |
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} |
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static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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return ioread32(ar_ahb->tcsr_mem + offset); |
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} |
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static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr) |
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{ |
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return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr); |
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} |
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static int ath10k_ahb_get_num_banks(struct ath10k *ar) |
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{ |
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if (ar->hw_rev == ATH10K_HW_QCA4019) |
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return 1; |
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ath10k_warn(ar, "unknown number of banks, assuming 1\n"); |
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return 1; |
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} |
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static int ath10k_ahb_clock_init(struct ath10k *ar) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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struct device *dev; |
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dev = &ar_ahb->pdev->dev; |
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ar_ahb->cmd_clk = devm_clk_get(dev, "wifi_wcss_cmd"); |
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if (IS_ERR_OR_NULL(ar_ahb->cmd_clk)) { |
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ath10k_err(ar, "failed to get cmd clk: %ld\n", |
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PTR_ERR(ar_ahb->cmd_clk)); |
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return ar_ahb->cmd_clk ? PTR_ERR(ar_ahb->cmd_clk) : -ENODEV; |
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} |
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ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref"); |
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if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) { |
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ath10k_err(ar, "failed to get ref clk: %ld\n", |
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PTR_ERR(ar_ahb->ref_clk)); |
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return ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV; |
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} |
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ar_ahb->rtc_clk = devm_clk_get(dev, "wifi_wcss_rtc"); |
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if (IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { |
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ath10k_err(ar, "failed to get rtc clk: %ld\n", |
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PTR_ERR(ar_ahb->rtc_clk)); |
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return ar_ahb->rtc_clk ? PTR_ERR(ar_ahb->rtc_clk) : -ENODEV; |
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} |
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return 0; |
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} |
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static void ath10k_ahb_clock_deinit(struct ath10k *ar) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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ar_ahb->cmd_clk = NULL; |
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ar_ahb->ref_clk = NULL; |
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ar_ahb->rtc_clk = NULL; |
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} |
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static int ath10k_ahb_clock_enable(struct ath10k *ar) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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int ret; |
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if (IS_ERR_OR_NULL(ar_ahb->cmd_clk) || |
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IS_ERR_OR_NULL(ar_ahb->ref_clk) || |
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IS_ERR_OR_NULL(ar_ahb->rtc_clk)) { |
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ath10k_err(ar, "clock(s) is/are not initialized\n"); |
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ret = -EIO; |
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goto out; |
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} |
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ret = clk_prepare_enable(ar_ahb->cmd_clk); |
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if (ret) { |
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ath10k_err(ar, "failed to enable cmd clk: %d\n", ret); |
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goto out; |
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} |
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ret = clk_prepare_enable(ar_ahb->ref_clk); |
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if (ret) { |
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ath10k_err(ar, "failed to enable ref clk: %d\n", ret); |
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goto err_cmd_clk_disable; |
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} |
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ret = clk_prepare_enable(ar_ahb->rtc_clk); |
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if (ret) { |
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ath10k_err(ar, "failed to enable rtc clk: %d\n", ret); |
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goto err_ref_clk_disable; |
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} |
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return 0; |
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err_ref_clk_disable: |
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clk_disable_unprepare(ar_ahb->ref_clk); |
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err_cmd_clk_disable: |
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clk_disable_unprepare(ar_ahb->cmd_clk); |
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out: |
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return ret; |
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} |
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static void ath10k_ahb_clock_disable(struct ath10k *ar) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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clk_disable_unprepare(ar_ahb->cmd_clk); |
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clk_disable_unprepare(ar_ahb->ref_clk); |
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clk_disable_unprepare(ar_ahb->rtc_clk); |
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} |
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static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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struct device *dev; |
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dev = &ar_ahb->pdev->dev; |
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ar_ahb->core_cold_rst = devm_reset_control_get_exclusive(dev, |
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"wifi_core_cold"); |
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if (IS_ERR(ar_ahb->core_cold_rst)) { |
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ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n", |
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PTR_ERR(ar_ahb->core_cold_rst)); |
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return PTR_ERR(ar_ahb->core_cold_rst); |
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} |
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ar_ahb->radio_cold_rst = devm_reset_control_get_exclusive(dev, |
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"wifi_radio_cold"); |
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if (IS_ERR(ar_ahb->radio_cold_rst)) { |
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ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n", |
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PTR_ERR(ar_ahb->radio_cold_rst)); |
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return PTR_ERR(ar_ahb->radio_cold_rst); |
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} |
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ar_ahb->radio_warm_rst = devm_reset_control_get_exclusive(dev, |
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"wifi_radio_warm"); |
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if (IS_ERR(ar_ahb->radio_warm_rst)) { |
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ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n", |
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PTR_ERR(ar_ahb->radio_warm_rst)); |
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return PTR_ERR(ar_ahb->radio_warm_rst); |
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} |
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ar_ahb->radio_srif_rst = devm_reset_control_get_exclusive(dev, |
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"wifi_radio_srif"); |
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if (IS_ERR(ar_ahb->radio_srif_rst)) { |
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ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n", |
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PTR_ERR(ar_ahb->radio_srif_rst)); |
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return PTR_ERR(ar_ahb->radio_srif_rst); |
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} |
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ar_ahb->cpu_init_rst = devm_reset_control_get_exclusive(dev, |
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"wifi_cpu_init"); |
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if (IS_ERR(ar_ahb->cpu_init_rst)) { |
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ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n", |
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PTR_ERR(ar_ahb->cpu_init_rst)); |
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return PTR_ERR(ar_ahb->cpu_init_rst); |
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} |
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return 0; |
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} |
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static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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ar_ahb->core_cold_rst = NULL; |
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ar_ahb->radio_cold_rst = NULL; |
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ar_ahb->radio_warm_rst = NULL; |
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ar_ahb->radio_srif_rst = NULL; |
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ar_ahb->cpu_init_rst = NULL; |
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} |
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static int ath10k_ahb_release_reset(struct ath10k *ar) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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int ret; |
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if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || |
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IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || |
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IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || |
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IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { |
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ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); |
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return -EINVAL; |
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} |
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ret = reset_control_deassert(ar_ahb->radio_cold_rst); |
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if (ret) { |
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ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret); |
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return ret; |
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} |
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ret = reset_control_deassert(ar_ahb->radio_warm_rst); |
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if (ret) { |
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ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret); |
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return ret; |
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} |
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ret = reset_control_deassert(ar_ahb->radio_srif_rst); |
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if (ret) { |
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ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret); |
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return ret; |
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} |
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ret = reset_control_deassert(ar_ahb->cpu_init_rst); |
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if (ret) { |
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ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret); |
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return ret; |
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} |
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return 0; |
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} |
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static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg, |
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u32 haltack_reg) |
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{ |
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unsigned long timeout; |
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u32 val; |
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/* Issue halt axi bus request */ |
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val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); |
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val |= AHB_AXI_BUS_HALT_REQ; |
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ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); |
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/* Wait for axi bus halted ack */ |
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timeout = jiffies + msecs_to_jiffies(ATH10K_AHB_AXI_BUS_HALT_TIMEOUT); |
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do { |
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val = ath10k_ahb_tcsr_read32(ar, haltack_reg); |
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if (val & AHB_AXI_BUS_HALT_ACK) |
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break; |
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mdelay(1); |
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} while (time_before(jiffies, timeout)); |
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if (!(val & AHB_AXI_BUS_HALT_ACK)) { |
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ath10k_err(ar, "failed to halt axi bus: %d\n", val); |
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return; |
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} |
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ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n"); |
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} |
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static void ath10k_ahb_halt_chip(struct ath10k *ar) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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u32 core_id, glb_cfg_reg, haltreq_reg, haltack_reg; |
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u32 val; |
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int ret; |
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if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst) || |
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IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) || |
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IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) || |
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IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) || |
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IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) { |
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ath10k_err(ar, "rst ctrl(s) is/are not initialized\n"); |
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return; |
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} |
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core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG); |
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switch (core_id) { |
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case 0: |
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glb_cfg_reg = ATH10K_AHB_TCSR_WIFI0_GLB_CFG; |
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haltreq_reg = ATH10K_AHB_TCSR_WCSS0_HALTREQ; |
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haltack_reg = ATH10K_AHB_TCSR_WCSS0_HALTACK; |
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break; |
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case 1: |
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glb_cfg_reg = ATH10K_AHB_TCSR_WIFI1_GLB_CFG; |
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haltreq_reg = ATH10K_AHB_TCSR_WCSS1_HALTREQ; |
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haltack_reg = ATH10K_AHB_TCSR_WCSS1_HALTACK; |
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break; |
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default: |
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ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n", |
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core_id); |
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return; |
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} |
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ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg); |
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val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); |
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val |= TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; |
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ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); |
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ret = reset_control_assert(ar_ahb->core_cold_rst); |
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if (ret) |
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ath10k_err(ar, "failed to assert core cold rst: %d\n", ret); |
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msleep(1); |
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ret = reset_control_assert(ar_ahb->radio_cold_rst); |
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if (ret) |
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ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret); |
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msleep(1); |
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ret = reset_control_assert(ar_ahb->radio_warm_rst); |
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if (ret) |
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ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret); |
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msleep(1); |
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ret = reset_control_assert(ar_ahb->radio_srif_rst); |
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if (ret) |
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ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret); |
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msleep(1); |
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ret = reset_control_assert(ar_ahb->cpu_init_rst); |
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if (ret) |
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ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret); |
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msleep(10); |
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/* Clear halt req and core clock disable req before |
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* deasserting wifi core reset. |
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*/ |
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val = ath10k_ahb_tcsr_read32(ar, haltreq_reg); |
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val &= ~AHB_AXI_BUS_HALT_REQ; |
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ath10k_ahb_tcsr_write32(ar, haltreq_reg, val); |
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val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg); |
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val &= ~TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK; |
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ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val); |
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ret = reset_control_deassert(ar_ahb->core_cold_rst); |
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if (ret) |
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ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret); |
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ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id); |
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} |
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static irqreturn_t ath10k_ahb_interrupt_handler(int irq, void *arg) |
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{ |
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struct ath10k *ar = arg; |
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if (!ath10k_pci_irq_pending(ar)) |
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return IRQ_NONE; |
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ath10k_pci_disable_and_clear_legacy_irq(ar); |
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ath10k_pci_irq_msi_fw_mask(ar); |
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napi_schedule(&ar->napi); |
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return IRQ_HANDLED; |
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} |
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static int ath10k_ahb_request_irq_legacy(struct ath10k *ar) |
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{ |
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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int ret; |
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ret = request_irq(ar_ahb->irq, |
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ath10k_ahb_interrupt_handler, |
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IRQF_SHARED, "ath10k_ahb", ar); |
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if (ret) { |
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ath10k_warn(ar, "failed to request legacy irq %d: %d\n", |
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ar_ahb->irq, ret); |
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return ret; |
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} |
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ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY; |
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return 0; |
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} |
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static void ath10k_ahb_release_irq_legacy(struct ath10k *ar) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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free_irq(ar_ahb->irq, ar); |
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} |
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static void ath10k_ahb_irq_disable(struct ath10k *ar) |
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{ |
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ath10k_ce_disable_interrupts(ar); |
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ath10k_pci_disable_and_clear_legacy_irq(ar); |
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} |
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static int ath10k_ahb_resource_init(struct ath10k *ar) |
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{ |
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
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struct platform_device *pdev; |
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struct resource *res; |
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int ret; |
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pdev = ar_ahb->pdev; |
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ar_ahb->mem = devm_platform_get_and_ioremap_resource(pdev, 0, &res); |
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if (IS_ERR(ar_ahb->mem)) { |
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ath10k_err(ar, "mem ioremap error\n"); |
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ret = PTR_ERR(ar_ahb->mem); |
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goto out; |
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} |
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ar_ahb->mem_len = resource_size(res); |
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ar_ahb->gcc_mem = ioremap(ATH10K_GCC_REG_BASE, |
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ATH10K_GCC_REG_SIZE); |
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if (!ar_ahb->gcc_mem) { |
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ath10k_err(ar, "gcc mem ioremap error\n"); |
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ret = -ENOMEM; |
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goto err_mem_unmap; |
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} |
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ar_ahb->tcsr_mem = ioremap(ATH10K_TCSR_REG_BASE, |
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ATH10K_TCSR_REG_SIZE); |
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if (!ar_ahb->tcsr_mem) { |
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ath10k_err(ar, "tcsr mem ioremap error\n"); |
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ret = -ENOMEM; |
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goto err_gcc_mem_unmap; |
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} |
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ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
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if (ret) { |
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ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret); |
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goto err_tcsr_mem_unmap; |
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} |
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ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
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if (ret) { |
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ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n", |
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ret); |
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goto err_tcsr_mem_unmap; |
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} |
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ret = ath10k_ahb_clock_init(ar); |
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if (ret) |
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goto err_tcsr_mem_unmap; |
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ret = ath10k_ahb_rst_ctrl_init(ar); |
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if (ret) |
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goto err_clock_deinit; |
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ar_ahb->irq = platform_get_irq_byname(pdev, "legacy"); |
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if (ar_ahb->irq < 0) { |
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ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq); |
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ret = ar_ahb->irq; |
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goto err_clock_deinit; |
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} |
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|
|
ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq); |
|
|
|
ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%pK mem_len: %lu gcc mem: 0x%pK tcsr_mem: 0x%pK\n", |
|
ar_ahb->mem, ar_ahb->mem_len, |
|
ar_ahb->gcc_mem, ar_ahb->tcsr_mem); |
|
return 0; |
|
|
|
err_clock_deinit: |
|
ath10k_ahb_clock_deinit(ar); |
|
|
|
err_tcsr_mem_unmap: |
|
iounmap(ar_ahb->tcsr_mem); |
|
|
|
err_gcc_mem_unmap: |
|
ar_ahb->tcsr_mem = NULL; |
|
iounmap(ar_ahb->gcc_mem); |
|
|
|
err_mem_unmap: |
|
ar_ahb->gcc_mem = NULL; |
|
devm_iounmap(&pdev->dev, ar_ahb->mem); |
|
|
|
out: |
|
ar_ahb->mem = NULL; |
|
return ret; |
|
} |
|
|
|
static void ath10k_ahb_resource_deinit(struct ath10k *ar) |
|
{ |
|
struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
|
struct device *dev; |
|
|
|
dev = &ar_ahb->pdev->dev; |
|
|
|
if (ar_ahb->mem) |
|
devm_iounmap(dev, ar_ahb->mem); |
|
|
|
if (ar_ahb->gcc_mem) |
|
iounmap(ar_ahb->gcc_mem); |
|
|
|
if (ar_ahb->tcsr_mem) |
|
iounmap(ar_ahb->tcsr_mem); |
|
|
|
ar_ahb->mem = NULL; |
|
ar_ahb->gcc_mem = NULL; |
|
ar_ahb->tcsr_mem = NULL; |
|
|
|
ath10k_ahb_clock_deinit(ar); |
|
ath10k_ahb_rst_ctrl_deinit(ar); |
|
} |
|
|
|
static int ath10k_ahb_prepare_device(struct ath10k *ar) |
|
{ |
|
u32 val; |
|
int ret; |
|
|
|
ret = ath10k_ahb_clock_enable(ar); |
|
if (ret) { |
|
ath10k_err(ar, "failed to enable clocks\n"); |
|
return ret; |
|
} |
|
|
|
/* Clock for the target is supplied from outside of target (ie, |
|
* external clock module controlled by the host). Target needs |
|
* to know what frequency target cpu is configured which is needed |
|
* for target internal use. Read target cpu frequency info from |
|
* gcc register and write into target's scratch register where |
|
* target expects this information. |
|
*/ |
|
val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV); |
|
ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val); |
|
|
|
ret = ath10k_ahb_release_reset(ar); |
|
if (ret) |
|
goto err_clk_disable; |
|
|
|
ath10k_ahb_irq_disable(ar); |
|
|
|
ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY); |
|
|
|
ret = ath10k_pci_wait_for_target_init(ar); |
|
if (ret) |
|
goto err_halt_chip; |
|
|
|
return 0; |
|
|
|
err_halt_chip: |
|
ath10k_ahb_halt_chip(ar); |
|
|
|
err_clk_disable: |
|
ath10k_ahb_clock_disable(ar); |
|
|
|
return ret; |
|
} |
|
|
|
static int ath10k_ahb_chip_reset(struct ath10k *ar) |
|
{ |
|
int ret; |
|
|
|
ath10k_ahb_halt_chip(ar); |
|
ath10k_ahb_clock_disable(ar); |
|
|
|
ret = ath10k_ahb_prepare_device(ar); |
|
if (ret) |
|
return ret; |
|
|
|
return 0; |
|
} |
|
|
|
static int ath10k_ahb_wake_target_cpu(struct ath10k *ar) |
|
{ |
|
u32 addr, val; |
|
|
|
addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS; |
|
val = ath10k_ahb_read32(ar, addr); |
|
val |= ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK; |
|
ath10k_ahb_write32(ar, addr, val); |
|
|
|
return 0; |
|
} |
|
|
|
static int ath10k_ahb_hif_start(struct ath10k *ar) |
|
{ |
|
ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n"); |
|
|
|
ath10k_core_napi_enable(ar); |
|
ath10k_ce_enable_interrupts(ar); |
|
ath10k_pci_enable_legacy_irq(ar); |
|
|
|
ath10k_pci_rx_post(ar); |
|
|
|
return 0; |
|
} |
|
|
|
static void ath10k_ahb_hif_stop(struct ath10k *ar) |
|
{ |
|
struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar); |
|
|
|
ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n"); |
|
|
|
ath10k_ahb_irq_disable(ar); |
|
synchronize_irq(ar_ahb->irq); |
|
|
|
ath10k_core_napi_sync_disable(ar); |
|
|
|
ath10k_pci_flush(ar); |
|
} |
|
|
|
static int ath10k_ahb_hif_power_up(struct ath10k *ar, |
|
enum ath10k_firmware_mode fw_mode) |
|
{ |
|
int ret; |
|
|
|
ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n"); |
|
|
|
ret = ath10k_ahb_chip_reset(ar); |
|
if (ret) { |
|
ath10k_err(ar, "failed to reset chip: %d\n", ret); |
|
goto out; |
|
} |
|
|
|
ret = ath10k_pci_init_pipes(ar); |
|
if (ret) { |
|
ath10k_err(ar, "failed to initialize CE: %d\n", ret); |
|
goto out; |
|
} |
|
|
|
ret = ath10k_pci_init_config(ar); |
|
if (ret) { |
|
ath10k_err(ar, "failed to setup init config: %d\n", ret); |
|
goto err_ce_deinit; |
|
} |
|
|
|
ret = ath10k_ahb_wake_target_cpu(ar); |
|
if (ret) { |
|
ath10k_err(ar, "could not wake up target CPU: %d\n", ret); |
|
goto err_ce_deinit; |
|
} |
|
|
|
return 0; |
|
|
|
err_ce_deinit: |
|
ath10k_pci_ce_deinit(ar); |
|
out: |
|
return ret; |
|
} |
|
|
|
static u32 ath10k_ahb_qca4019_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr) |
|
{ |
|
u32 val = 0, region = addr & 0xfffff; |
|
|
|
val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS); |
|
|
|
if (region >= QCA4019_SRAM_ADDR && region <= |
|
(QCA4019_SRAM_ADDR + QCA4019_SRAM_LEN)) { |
|
/* SRAM contents for QCA4019 can be directly accessed and |
|
* no conversions are required |
|
*/ |
|
val |= region; |
|
} else { |
|
val |= 0x100000 | region; |
|
} |
|
|
|
return val; |
|
} |
|
|
|
static const struct ath10k_hif_ops ath10k_ahb_hif_ops = { |
|
.tx_sg = ath10k_pci_hif_tx_sg, |
|
.diag_read = ath10k_pci_hif_diag_read, |
|
.diag_write = ath10k_pci_diag_write_mem, |
|
.exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, |
|
.start = ath10k_ahb_hif_start, |
|
.stop = ath10k_ahb_hif_stop, |
|
.map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, |
|
.get_default_pipe = ath10k_pci_hif_get_default_pipe, |
|
.send_complete_check = ath10k_pci_hif_send_complete_check, |
|
.get_free_queue_number = ath10k_pci_hif_get_free_queue_number, |
|
.power_up = ath10k_ahb_hif_power_up, |
|
.power_down = ath10k_pci_hif_power_down, |
|
.read32 = ath10k_ahb_read32, |
|
.write32 = ath10k_ahb_write32, |
|
}; |
|
|
|
static const struct ath10k_bus_ops ath10k_ahb_bus_ops = { |
|
.read32 = ath10k_ahb_read32, |
|
.write32 = ath10k_ahb_write32, |
|
.get_num_banks = ath10k_ahb_get_num_banks, |
|
}; |
|
|
|
static int ath10k_ahb_probe(struct platform_device *pdev) |
|
{ |
|
struct ath10k *ar; |
|
struct ath10k_ahb *ar_ahb; |
|
struct ath10k_pci *ar_pci; |
|
const struct of_device_id *of_id; |
|
enum ath10k_hw_rev hw_rev; |
|
size_t size; |
|
int ret; |
|
struct ath10k_bus_params bus_params = {}; |
|
|
|
of_id = of_match_device(ath10k_ahb_of_match, &pdev->dev); |
|
if (!of_id) { |
|
dev_err(&pdev->dev, "failed to find matching device tree id\n"); |
|
return -EINVAL; |
|
} |
|
|
|
hw_rev = (enum ath10k_hw_rev)of_id->data; |
|
|
|
size = sizeof(*ar_pci) + sizeof(*ar_ahb); |
|
ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB, |
|
hw_rev, &ath10k_ahb_hif_ops); |
|
if (!ar) { |
|
dev_err(&pdev->dev, "failed to allocate core\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n"); |
|
|
|
ar_pci = ath10k_pci_priv(ar); |
|
ar_ahb = ath10k_ahb_priv(ar); |
|
|
|
ar_ahb->pdev = pdev; |
|
platform_set_drvdata(pdev, ar); |
|
|
|
ret = ath10k_ahb_resource_init(ar); |
|
if (ret) |
|
goto err_core_destroy; |
|
|
|
ar->dev_id = 0; |
|
ar_pci->mem = ar_ahb->mem; |
|
ar_pci->mem_len = ar_ahb->mem_len; |
|
ar_pci->ar = ar; |
|
ar_pci->ce.bus_ops = &ath10k_ahb_bus_ops; |
|
ar_pci->targ_cpu_to_ce_addr = ath10k_ahb_qca4019_targ_cpu_to_ce_addr; |
|
ar->ce_priv = &ar_pci->ce; |
|
|
|
ret = ath10k_pci_setup_resource(ar); |
|
if (ret) { |
|
ath10k_err(ar, "failed to setup resource: %d\n", ret); |
|
goto err_resource_deinit; |
|
} |
|
|
|
ath10k_pci_init_napi(ar); |
|
|
|
ret = ath10k_ahb_request_irq_legacy(ar); |
|
if (ret) |
|
goto err_free_pipes; |
|
|
|
ret = ath10k_ahb_prepare_device(ar); |
|
if (ret) |
|
goto err_free_irq; |
|
|
|
ath10k_pci_ce_deinit(ar); |
|
|
|
bus_params.dev_type = ATH10K_DEV_TYPE_LL; |
|
bus_params.chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS); |
|
if (bus_params.chip_id == 0xffffffff) { |
|
ath10k_err(ar, "failed to get chip id\n"); |
|
ret = -ENODEV; |
|
goto err_halt_device; |
|
} |
|
|
|
ret = ath10k_core_register(ar, &bus_params); |
|
if (ret) { |
|
ath10k_err(ar, "failed to register driver core: %d\n", ret); |
|
goto err_halt_device; |
|
} |
|
|
|
return 0; |
|
|
|
err_halt_device: |
|
ath10k_ahb_halt_chip(ar); |
|
ath10k_ahb_clock_disable(ar); |
|
|
|
err_free_irq: |
|
ath10k_ahb_release_irq_legacy(ar); |
|
|
|
err_free_pipes: |
|
ath10k_pci_release_resource(ar); |
|
|
|
err_resource_deinit: |
|
ath10k_ahb_resource_deinit(ar); |
|
|
|
err_core_destroy: |
|
ath10k_core_destroy(ar); |
|
platform_set_drvdata(pdev, NULL); |
|
|
|
return ret; |
|
} |
|
|
|
static int ath10k_ahb_remove(struct platform_device *pdev) |
|
{ |
|
struct ath10k *ar = platform_get_drvdata(pdev); |
|
struct ath10k_ahb *ar_ahb; |
|
|
|
if (!ar) |
|
return -EINVAL; |
|
|
|
ar_ahb = ath10k_ahb_priv(ar); |
|
|
|
if (!ar_ahb) |
|
return -EINVAL; |
|
|
|
ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n"); |
|
|
|
ath10k_core_unregister(ar); |
|
ath10k_ahb_irq_disable(ar); |
|
ath10k_ahb_release_irq_legacy(ar); |
|
ath10k_pci_release_resource(ar); |
|
ath10k_ahb_halt_chip(ar); |
|
ath10k_ahb_clock_disable(ar); |
|
ath10k_ahb_resource_deinit(ar); |
|
ath10k_core_destroy(ar); |
|
|
|
platform_set_drvdata(pdev, NULL); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver ath10k_ahb_driver = { |
|
.driver = { |
|
.name = "ath10k_ahb", |
|
.of_match_table = ath10k_ahb_of_match, |
|
}, |
|
.probe = ath10k_ahb_probe, |
|
.remove = ath10k_ahb_remove, |
|
}; |
|
|
|
int ath10k_ahb_init(void) |
|
{ |
|
int ret; |
|
|
|
ret = platform_driver_register(&ath10k_ahb_driver); |
|
if (ret) |
|
printk(KERN_ERR "failed to register ath10k ahb driver: %d\n", |
|
ret); |
|
return ret; |
|
} |
|
|
|
void ath10k_ahb_exit(void) |
|
{ |
|
platform_driver_unregister(&ath10k_ahb_driver); |
|
}
|
|
|