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431 lines
11 KiB
431 lines
11 KiB
/* |
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* Copyright (c) 2006 Damien Bergamini <[email protected]> |
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* Copyright (c) 2006 Sam Leffler, Errno Consulting |
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* Copyright (c) 2007 Christoph Hellwig <[email protected]> |
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* Copyright (c) 2008-2009 Weongyo Jeong <[email protected]> |
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* Copyright (c) 2012 Pontus Fuchs <[email protected]> |
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* |
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* Permission to use, copy, modify, and/or distribute this software for any |
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* purpose with or without fee is hereby granted, provided that the above |
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* copyright notice and this permission notice appear in all copies. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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*/ |
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/* all fields are big endian */ |
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struct ar5523_fwblock { |
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__be32 flags; |
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#define AR5523_WRITE_BLOCK (1 << 4) |
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__be32 len; |
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#define AR5523_MAX_FWBLOCK_SIZE 2048 |
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__be32 total; |
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__be32 remain; |
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__be32 rxtotal; |
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__be32 pad[123]; |
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} __packed; |
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#define AR5523_MAX_RXCMDSZ 1024 |
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#define AR5523_MAX_TXCMDSZ 1024 |
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struct ar5523_cmd_hdr { |
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__be32 len; |
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__be32 code; |
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/* NB: these are defined for rev 1.5 firmware; rev 1.6 is different */ |
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/* messages from Host -> Target */ |
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#define WDCMSG_HOST_AVAILABLE 0x01 |
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#define WDCMSG_BIND 0x02 |
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#define WDCMSG_TARGET_RESET 0x03 |
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#define WDCMSG_TARGET_GET_CAPABILITY 0x04 |
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#define WDCMSG_TARGET_SET_CONFIG 0x05 |
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#define WDCMSG_TARGET_GET_STATUS 0x06 |
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#define WDCMSG_TARGET_GET_STATS 0x07 |
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#define WDCMSG_TARGET_START 0x08 |
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#define WDCMSG_TARGET_STOP 0x09 |
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#define WDCMSG_TARGET_ENABLE 0x0a |
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#define WDCMSG_TARGET_DISABLE 0x0b |
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#define WDCMSG_CREATE_CONNECTION 0x0c |
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#define WDCMSG_UPDATE_CONNECT_ATTR 0x0d |
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#define WDCMSG_DELETE_CONNECT 0x0e |
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#define WDCMSG_SEND 0x0f |
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#define WDCMSG_FLUSH 0x10 |
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/* messages from Target -> Host */ |
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#define WDCMSG_STATS_UPDATE 0x11 |
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#define WDCMSG_BMISS 0x12 |
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#define WDCMSG_DEVICE_AVAIL 0x13 |
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#define WDCMSG_SEND_COMPLETE 0x14 |
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#define WDCMSG_DATA_AVAIL 0x15 |
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#define WDCMSG_SET_PWR_MODE 0x16 |
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#define WDCMSG_BMISS_ACK 0x17 |
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#define WDCMSG_SET_LED_STEADY 0x18 |
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#define WDCMSG_SET_LED_BLINK 0x19 |
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/* more messages */ |
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#define WDCMSG_SETUP_BEACON_DESC 0x1a |
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#define WDCMSG_BEACON_INIT 0x1b |
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#define WDCMSG_RESET_KEY_CACHE 0x1c |
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#define WDCMSG_RESET_KEY_CACHE_ENTRY 0x1d |
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#define WDCMSG_SET_KEY_CACHE_ENTRY 0x1e |
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#define WDCMSG_SET_DECOMP_MASK 0x1f |
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#define WDCMSG_SET_REGULATORY_DOMAIN 0x20 |
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#define WDCMSG_SET_LED_STATE 0x21 |
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#define WDCMSG_WRITE_ASSOCID 0x22 |
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#define WDCMSG_SET_STA_BEACON_TIMERS 0x23 |
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#define WDCMSG_GET_TSF 0x24 |
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#define WDCMSG_RESET_TSF 0x25 |
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#define WDCMSG_SET_ADHOC_MODE 0x26 |
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#define WDCMSG_SET_BASIC_RATE 0x27 |
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#define WDCMSG_MIB_CONTROL 0x28 |
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#define WDCMSG_GET_CHANNEL_DATA 0x29 |
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#define WDCMSG_GET_CUR_RSSI 0x2a |
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#define WDCMSG_SET_ANTENNA_SWITCH 0x2b |
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#define WDCMSG_USE_SHORT_SLOT_TIME 0x2f |
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#define WDCMSG_SET_POWER_MODE 0x30 |
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#define WDCMSG_SETUP_PSPOLL_DESC 0x31 |
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#define WDCMSG_SET_RX_MULTICAST_FILTER 0x32 |
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#define WDCMSG_RX_FILTER 0x33 |
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#define WDCMSG_PER_CALIBRATION 0x34 |
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#define WDCMSG_RESET 0x35 |
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#define WDCMSG_DISABLE 0x36 |
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#define WDCMSG_PHY_DISABLE 0x37 |
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#define WDCMSG_SET_TX_POWER_LIMIT 0x38 |
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#define WDCMSG_SET_TX_QUEUE_PARAMS 0x39 |
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#define WDCMSG_SETUP_TX_QUEUE 0x3a |
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#define WDCMSG_RELEASE_TX_QUEUE 0x3b |
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#define WDCMSG_SET_DEFAULT_KEY 0x43 |
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__u32 priv; /* driver private data, |
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don't care about endianess */ |
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__be32 magic; |
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__be32 reserved2[4]; |
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}; |
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struct ar5523_cmd_host_available { |
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__be32 sw_ver_major; |
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__be32 sw_ver_minor; |
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__be32 sw_ver_patch; |
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__be32 sw_ver_build; |
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} __packed; |
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#define ATH_SW_VER_MAJOR 1 |
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#define ATH_SW_VER_MINOR 5 |
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#define ATH_SW_VER_PATCH 0 |
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#define ATH_SW_VER_BUILD 9999 |
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struct ar5523_chunk { |
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u8 seqnum; /* sequence number for ordering */ |
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u8 flags; |
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#define UATH_CFLAGS_FINAL 0x01 /* final chunk of a msg */ |
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#define UATH_CFLAGS_RXMSG 0x02 /* chunk contains rx completion */ |
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#define UATH_CFLAGS_DEBUG 0x04 /* for debugging */ |
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__be16 length; /* chunk size in bytes */ |
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/* chunk data follows */ |
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} __packed; |
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/* |
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* Message format for a WDCMSG_DATA_AVAIL message from Target to Host. |
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*/ |
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struct ar5523_rx_desc { |
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__be32 len; /* msg length including header */ |
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__be32 code; /* WDCMSG_DATA_AVAIL */ |
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__be32 gennum; /* generation number */ |
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__be32 status; /* start of RECEIVE_INFO */ |
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#define UATH_STATUS_OK 0 |
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#define UATH_STATUS_STOP_IN_PROGRESS 1 |
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#define UATH_STATUS_CRC_ERR 2 |
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#define UATH_STATUS_PHY_ERR 3 |
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#define UATH_STATUS_DECRYPT_CRC_ERR 4 |
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#define UATH_STATUS_DECRYPT_MIC_ERR 5 |
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#define UATH_STATUS_DECOMP_ERR 6 |
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#define UATH_STATUS_KEY_ERR 7 |
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#define UATH_STATUS_ERR 8 |
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__be32 tstamp_low; /* low-order 32-bits of rx timestamp */ |
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__be32 tstamp_high; /* high-order 32-bits of rx timestamp */ |
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__be32 framelen; /* frame length */ |
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__be32 rate; /* rx rate code */ |
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__be32 antenna; |
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__be32 rssi; |
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__be32 channel; |
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__be32 phyerror; |
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__be32 connix; /* key table ix for bss traffic */ |
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__be32 decrypterror; |
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__be32 keycachemiss; |
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__be32 pad; /* XXX? */ |
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} __packed; |
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struct ar5523_tx_desc { |
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__be32 msglen; |
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u32 msgid; /* msg id (supplied by host) */ |
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__be32 type; /* opcode: WDMSG_SEND or WDCMSG_FLUSH */ |
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__be32 txqid; /* tx queue id and flags */ |
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#define UATH_TXQID_MASK 0x0f |
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#define UATH_TXQID_MINRATE 0x10 /* use min tx rate */ |
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#define UATH_TXQID_FF 0x20 /* content is fast frame */ |
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__be32 connid; /* tx connection id */ |
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#define UATH_ID_INVALID 0xffffffff /* for sending prior to connection */ |
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__be32 flags; /* non-zero if response desired */ |
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#define UATH_TX_NOTIFY (1 << 24) /* f/w will send a UATH_NOTIF_TX */ |
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__be32 buflen; /* payload length */ |
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} __packed; |
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#define AR5523_ID_BSS 2 |
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#define AR5523_ID_BROADCAST 0xffffffff |
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/* structure for command UATH_CMD_WRITE_MAC */ |
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struct ar5523_write_mac { |
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__be32 reg; |
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__be32 len; |
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u8 data[32]; |
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} __packed; |
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struct ar5523_cmd_rateset { |
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__u8 length; |
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#define AR5523_MAX_NRATES 32 |
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__u8 set[AR5523_MAX_NRATES]; |
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}; |
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struct ar5523_cmd_set_associd { /* AR5523_WRITE_ASSOCID */ |
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__be32 defaultrateix; |
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__be32 associd; |
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__be32 timoffset; |
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__be32 turboprime; |
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__u8 bssid[6]; |
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} __packed; |
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/* structure for command WDCMSG_RESET */ |
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struct ar5523_cmd_reset { |
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__be32 flags; /* channel flags */ |
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#define UATH_CHAN_TURBO 0x0100 |
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#define UATH_CHAN_CCK 0x0200 |
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#define UATH_CHAN_OFDM 0x0400 |
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#define UATH_CHAN_2GHZ 0x1000 |
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#define UATH_CHAN_5GHZ 0x2000 |
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__be32 freq; /* channel frequency */ |
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__be32 maxrdpower; |
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__be32 cfgctl; |
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__be32 twiceantennareduction; |
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__be32 channelchange; |
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__be32 keeprccontent; |
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} __packed; |
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/* structure for command WDCMSG_SET_BASIC_RATE */ |
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struct ar5523_cmd_rates { |
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__be32 connid; |
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__be32 keeprccontent; |
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__be32 size; |
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struct ar5523_cmd_rateset rateset; |
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} __packed; |
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enum { |
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WLAN_MODE_NONE = 0, |
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WLAN_MODE_11b, |
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WLAN_MODE_11a, |
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WLAN_MODE_11g, |
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WLAN_MODE_11a_TURBO, |
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WLAN_MODE_11g_TURBO, |
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WLAN_MODE_11a_TURBO_PRIME, |
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WLAN_MODE_11g_TURBO_PRIME, |
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WLAN_MODE_11a_XR, |
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WLAN_MODE_11g_XR, |
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}; |
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struct ar5523_cmd_connection_attr { |
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__be32 longpreambleonly; |
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struct ar5523_cmd_rateset rateset; |
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__be32 wlanmode; |
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} __packed; |
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/* structure for command AR5523_CREATE_CONNECTION */ |
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struct ar5523_cmd_create_connection { |
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__be32 connid; |
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__be32 bssid; |
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__be32 size; |
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struct ar5523_cmd_connection_attr connattr; |
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} __packed; |
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struct ar5523_cmd_ledsteady { /* WDCMSG_SET_LED_STEADY */ |
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__be32 lednum; |
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#define UATH_LED_LINK 0 |
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#define UATH_LED_ACTIVITY 1 |
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__be32 ledmode; |
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#define UATH_LED_OFF 0 |
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#define UATH_LED_ON 1 |
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} __packed; |
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struct ar5523_cmd_ledblink { /* WDCMSG_SET_LED_BLINK */ |
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__be32 lednum; |
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__be32 ledmode; |
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__be32 blinkrate; |
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__be32 slowmode; |
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} __packed; |
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struct ar5523_cmd_ledstate { /* WDCMSG_SET_LED_STATE */ |
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__be32 connected; |
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} __packed; |
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struct ar5523_cmd_txq_attr { |
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__be32 priority; |
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__be32 aifs; |
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__be32 logcwmin; |
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__be32 logcwmax; |
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__be32 bursttime; |
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__be32 mode; |
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__be32 qflags; |
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} __packed; |
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struct ar5523_cmd_txq_setup { /* WDCMSG_SETUP_TX_QUEUE */ |
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__be32 qid; |
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__be32 len; |
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struct ar5523_cmd_txq_attr attr; |
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} __packed; |
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struct ar5523_cmd_rx_filter { /* WDCMSG_RX_FILTER */ |
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__be32 bits; |
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#define UATH_FILTER_RX_UCAST 0x00000001 |
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#define UATH_FILTER_RX_MCAST 0x00000002 |
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#define UATH_FILTER_RX_BCAST 0x00000004 |
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#define UATH_FILTER_RX_CONTROL 0x00000008 |
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#define UATH_FILTER_RX_BEACON 0x00000010 /* beacon frames */ |
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#define UATH_FILTER_RX_PROM 0x00000020 /* promiscuous mode */ |
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#define UATH_FILTER_RX_PHY_ERR 0x00000040 /* phy errors */ |
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#define UATH_FILTER_RX_PHY_RADAR 0x00000080 /* radar phy errors */ |
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#define UATH_FILTER_RX_XR_POOL 0x00000400 /* XR group polls */ |
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#define UATH_FILTER_RX_PROBE_REQ 0x00000800 |
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__be32 op; |
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#define UATH_FILTER_OP_INIT 0x0 |
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#define UATH_FILTER_OP_SET 0x1 |
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#define UATH_FILTER_OP_CLEAR 0x2 |
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#define UATH_FILTER_OP_TEMP 0x3 |
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#define UATH_FILTER_OP_RESTORE 0x4 |
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} __packed; |
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enum { |
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CFG_NONE, /* Sentinal to indicate "no config" */ |
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CFG_REG_DOMAIN, /* Regulatory Domain */ |
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CFG_RATE_CONTROL_ENABLE, |
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CFG_DEF_XMIT_DATA_RATE, /* NB: if rate control is not enabled */ |
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CFG_HW_TX_RETRIES, |
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CFG_SW_TX_RETRIES, |
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CFG_SLOW_CLOCK_ENABLE, |
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CFG_COMP_PROC, |
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CFG_USER_RTS_THRESHOLD, |
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CFG_XR2NORM_RATE_THRESHOLD, |
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CFG_XRMODE_SWITCH_COUNT, |
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CFG_PROTECTION_TYPE, |
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CFG_BURST_SEQ_THRESHOLD, |
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CFG_ABOLT, |
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CFG_IQ_LOG_COUNT_MAX, |
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CFG_MODE_CTS, |
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CFG_WME_ENABLED, |
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CFG_GPRS_CBR_PERIOD, |
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CFG_SERVICE_TYPE, |
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/* MAC Address to use. Overrides EEPROM */ |
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CFG_MAC_ADDR, |
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CFG_DEBUG_EAR, |
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CFG_INIT_REGS, |
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/* An ID for use in error & debug messages */ |
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CFG_DEBUG_ID, |
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CFG_COMP_WIN_SZ, |
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CFG_DIVERSITY_CTL, |
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CFG_TP_SCALE, |
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CFG_TPC_HALF_DBM5, |
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CFG_TPC_HALF_DBM2, |
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CFG_OVERRD_TX_POWER, |
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CFG_USE_32KHZ_CLOCK, |
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CFG_GMODE_PROTECTION, |
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CFG_GMODE_PROTECT_RATE_INDEX, |
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CFG_GMODE_NON_ERP_PREAMBLE, |
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CFG_WDC_TRANSPORT_CHUNK_SIZE, |
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}; |
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enum { |
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/* Sentinal to indicate "no capability" */ |
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CAP_NONE, |
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CAP_ALL, /* ALL capabilities */ |
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CAP_TARGET_VERSION, |
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CAP_TARGET_REVISION, |
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CAP_MAC_VERSION, |
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CAP_MAC_REVISION, |
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CAP_PHY_REVISION, |
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CAP_ANALOG_5GHz_REVISION, |
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CAP_ANALOG_2GHz_REVISION, |
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/* Target supports WDC message debug features */ |
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CAP_DEBUG_WDCMSG_SUPPORT, |
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CAP_REG_DOMAIN, |
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CAP_COUNTRY_CODE, |
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CAP_REG_CAP_BITS, |
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CAP_WIRELESS_MODES, |
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CAP_CHAN_SPREAD_SUPPORT, |
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CAP_SLEEP_AFTER_BEACON_BROKEN, |
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CAP_COMPRESS_SUPPORT, |
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CAP_BURST_SUPPORT, |
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CAP_FAST_FRAMES_SUPPORT, |
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CAP_CHAP_TUNING_SUPPORT, |
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CAP_TURBOG_SUPPORT, |
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CAP_TURBO_PRIME_SUPPORT, |
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CAP_DEVICE_TYPE, |
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CAP_XR_SUPPORT, |
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CAP_WME_SUPPORT, |
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CAP_TOTAL_QUEUES, |
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CAP_CONNECTION_ID_MAX, /* Should absorb CAP_KEY_CACHE_SIZE */ |
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CAP_LOW_5GHZ_CHAN, |
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CAP_HIGH_5GHZ_CHAN, |
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CAP_LOW_2GHZ_CHAN, |
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CAP_HIGH_2GHZ_CHAN, |
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CAP_MIC_AES_CCM, |
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CAP_MIC_CKIP, |
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CAP_MIC_TKIP, |
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CAP_MIC_TKIP_WME, |
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CAP_CIPHER_AES_CCM, |
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CAP_CIPHER_CKIP, |
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CAP_CIPHER_TKIP, |
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CAP_TWICE_ANTENNAGAIN_5G, |
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CAP_TWICE_ANTENNAGAIN_2G, |
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}; |
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enum { |
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ST_NONE, /* Sentinal to indicate "no status" */ |
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ST_ALL, |
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ST_SERVICE_TYPE, |
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ST_WLAN_MODE, |
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ST_FREQ, |
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ST_BAND, |
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ST_LAST_RSSI, |
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ST_PS_FRAMES_DROPPED, |
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ST_CACHED_DEF_ANT, |
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ST_COUNT_OTHER_RX_ANT, |
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ST_USE_FAST_DIVERSITY, |
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ST_MAC_ADDR, |
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ST_RX_GENERATION_NUM, |
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ST_TX_QUEUE_DEPTH, |
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ST_SERIAL_NUMBER, |
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ST_WDC_TRANSPORT_CHUNK_SIZE, |
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}; |
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enum { |
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TARGET_DEVICE_AWAKE, |
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TARGET_DEVICE_SLEEP, |
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TARGET_DEVICE_PWRDN, |
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TARGET_DEVICE_PWRSAVE, |
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TARGET_DEVICE_SUSPEND, |
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TARGET_DEVICE_RESUME, |
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}; |
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/* this is in net/ieee80211.h, but that conflicts with the mac80211 headers */ |
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#define IEEE80211_2ADDR_LEN 16 |
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#define AR5523_MIN_RXBUFSZ \ |
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(((sizeof(__be32) + IEEE80211_2ADDR_LEN + \ |
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sizeof(struct ar5523_rx_desc)) + 3) & ~3)
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