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299 lines
9.7 KiB
299 lines
9.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2005, Intec Automation Inc. |
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* Copyright (C) 2014, Freescale Semiconductor, Inc. |
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*/ |
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#include <linux/mtd/spi-nor.h> |
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#include "core.h" |
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#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ |
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#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ |
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#define SPINOR_REG_CYPRESS_CFR2V 0x00800003 |
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#define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb |
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#define SPINOR_REG_CYPRESS_CFR3V 0x00800004 |
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#define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4) /* Page size. */ |
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#define SPINOR_REG_CYPRESS_CFR5V 0x00800006 |
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#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3 |
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#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS 0 |
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#define SPINOR_OP_CYPRESS_RD_FAST 0xee |
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/** |
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* spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes. |
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* @nor: pointer to a 'struct spi_nor' |
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* @enable: whether to enable or disable Octal DTR |
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* |
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* This also sets the memory access latency cycles to 24 to allow the flash to |
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* run at up to 200MHz. |
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* |
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* Return: 0 on success, -errno otherwise. |
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*/ |
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static int spi_nor_cypress_octal_dtr_enable(struct spi_nor *nor, bool enable) |
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{ |
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struct spi_mem_op op; |
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u8 *buf = nor->bouncebuf; |
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int ret; |
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if (enable) { |
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/* Use 24 dummy cycles for memory array reads. */ |
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ret = spi_nor_write_enable(nor); |
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if (ret) |
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return ret; |
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*buf = SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24; |
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op = (struct spi_mem_op) |
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), |
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SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR2V, |
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1), |
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SPI_MEM_OP_NO_DUMMY, |
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SPI_MEM_OP_DATA_OUT(1, buf, 1)); |
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ret = spi_mem_exec_op(nor->spimem, &op); |
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if (ret) |
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return ret; |
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ret = spi_nor_wait_till_ready(nor); |
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if (ret) |
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return ret; |
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nor->read_dummy = 24; |
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} |
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/* Set/unset the octal and DTR enable bits. */ |
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ret = spi_nor_write_enable(nor); |
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if (ret) |
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return ret; |
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if (enable) |
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*buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN; |
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else |
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*buf = SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS; |
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op = (struct spi_mem_op) |
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 1), |
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SPI_MEM_OP_ADDR(enable ? 3 : 4, |
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SPINOR_REG_CYPRESS_CFR5V, |
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1), |
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SPI_MEM_OP_NO_DUMMY, |
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SPI_MEM_OP_DATA_OUT(1, buf, 1)); |
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if (!enable) |
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spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); |
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ret = spi_mem_exec_op(nor->spimem, &op); |
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if (ret) |
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return ret; |
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/* Read flash ID to make sure the switch was successful. */ |
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op = (struct spi_mem_op) |
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), |
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SPI_MEM_OP_ADDR(enable ? 4 : 0, 0, 1), |
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SPI_MEM_OP_DUMMY(enable ? 3 : 0, 1), |
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SPI_MEM_OP_DATA_IN(round_up(nor->info->id_len, 2), |
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buf, 1)); |
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if (enable) |
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spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); |
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ret = spi_mem_exec_op(nor->spimem, &op); |
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if (ret) |
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return ret; |
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if (memcmp(buf, nor->info->id, nor->info->id_len)) |
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return -EINVAL; |
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return 0; |
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} |
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static void s28hs512t_default_init(struct spi_nor *nor) |
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{ |
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nor->params->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable; |
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nor->params->writesize = 16; |
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} |
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static void s28hs512t_post_sfdp_fixup(struct spi_nor *nor) |
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{ |
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/* |
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* On older versions of the flash the xSPI Profile 1.0 table has the |
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* 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. |
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*/ |
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if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0) |
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nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode = |
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SPINOR_OP_CYPRESS_RD_FAST; |
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/* This flash is also missing the 4-byte Page Program opcode bit. */ |
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spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP], |
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SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1); |
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/* |
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* Since xSPI Page Program opcode is backward compatible with |
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* Legacy SPI, use Legacy SPI opcode there as well. |
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*/ |
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spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR], |
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SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR); |
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/* |
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* The xSPI Profile 1.0 table advertises the number of additional |
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* address bytes needed for Read Status Register command as 0 but the |
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* actual value for that is 4. |
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*/ |
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nor->params->rdsr_addr_nbytes = 4; |
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} |
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static int s28hs512t_post_bfpt_fixup(struct spi_nor *nor, |
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const struct sfdp_parameter_header *bfpt_header, |
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const struct sfdp_bfpt *bfpt) |
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{ |
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/* |
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* The BFPT table advertises a 512B page size but the page size is |
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* actually configurable (with the default being 256B). Read from |
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* CFR3V[4] and set the correct size. |
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*/ |
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struct spi_mem_op op = |
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 1), |
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SPI_MEM_OP_ADDR(3, SPINOR_REG_CYPRESS_CFR3V, 1), |
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SPI_MEM_OP_NO_DUMMY, |
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SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1)); |
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int ret; |
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ret = spi_mem_exec_op(nor->spimem, &op); |
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if (ret) |
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return ret; |
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if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3V_PGSZ) |
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nor->params->page_size = 512; |
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else |
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nor->params->page_size = 256; |
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return 0; |
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} |
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static struct spi_nor_fixups s28hs512t_fixups = { |
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.default_init = s28hs512t_default_init, |
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.post_sfdp = s28hs512t_post_sfdp_fixup, |
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.post_bfpt = s28hs512t_post_bfpt_fixup, |
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}; |
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static int |
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s25fs_s_post_bfpt_fixups(struct spi_nor *nor, |
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const struct sfdp_parameter_header *bfpt_header, |
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const struct sfdp_bfpt *bfpt) |
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{ |
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/* |
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* The S25FS-S chip family reports 512-byte pages in BFPT but |
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* in reality the write buffer still wraps at the safe default |
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* of 256 bytes. Overwrite the page size advertised by BFPT |
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* to get the writes working. |
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*/ |
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nor->params->page_size = 256; |
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return 0; |
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} |
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static struct spi_nor_fixups s25fs_s_fixups = { |
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.post_bfpt = s25fs_s_post_bfpt_fixups, |
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}; |
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static const struct flash_info spansion_parts[] = { |
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/* Spansion/Cypress -- single (large) sector size only, at least |
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* for the chips listed here (without boot sectors). |
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*/ |
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{ "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
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{ "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
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{ "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64, |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
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USE_CLSR) }, |
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{ "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
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USE_CLSR) }, |
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{ "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128, |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
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USE_CLSR) }, |
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{ "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512, |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
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USE_CLSR) }, |
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{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256, |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
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SPI_NOR_HAS_LOCK | USE_CLSR) }, |
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{ "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256, |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) |
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.fixups = &s25fs_s_fixups, }, |
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{ "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128, |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
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USE_CLSR) }, |
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{ "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
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USE_CLSR) }, |
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{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) |
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.fixups = &s25fs_s_fixups, }, |
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{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, |
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{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, |
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{ "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
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USE_CLSR) }, |
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{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, |
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
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USE_CLSR) }, |
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{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, |
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{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, |
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{ "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, |
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{ "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, |
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{ "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, |
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{ "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8, |
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
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{ "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, |
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
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{ "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, |
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
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{ "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, |
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
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{ "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32, |
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, |
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{ "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64, SECT_4K) }, |
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{ "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128, SECT_4K) }, |
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{ "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8, |
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SECT_4K | SPI_NOR_DUAL_READ) }, |
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{ "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16, |
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SECT_4K | SPI_NOR_DUAL_READ) }, |
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{ "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128, |
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
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SPI_NOR_4B_OPCODES) }, |
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{ "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256, |
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
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SPI_NOR_4B_OPCODES) }, |
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{ "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512, |
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | |
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SPI_NOR_4B_OPCODES) }, |
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{ "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1, |
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SPI_NOR_NO_ERASE) }, |
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{ "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256, |
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SECT_4K | SPI_NOR_OCTAL_DTR_READ | |
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SPI_NOR_OCTAL_DTR_PP) |
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.fixups = &s28hs512t_fixups, |
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}, |
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}; |
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static void spansion_post_sfdp_fixups(struct spi_nor *nor) |
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{ |
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if (nor->params->size <= SZ_16M) |
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return; |
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nor->flags |= SNOR_F_4B_OPCODES; |
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/* No small sector erase for 4-byte command set */ |
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nor->erase_opcode = SPINOR_OP_SE; |
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nor->mtd.erasesize = nor->info->sector_size; |
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} |
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static const struct spi_nor_fixups spansion_fixups = { |
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.post_sfdp = spansion_post_sfdp_fixups, |
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}; |
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const struct spi_nor_manufacturer spi_nor_spansion = { |
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.name = "spansion", |
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.parts = spansion_parts, |
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.nparts = ARRAY_SIZE(spansion_parts), |
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.fixups = &spansion_fixups, |
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};
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