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56 lines
1.5 KiB
56 lines
1.5 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2008-2010 Samsung Electronics |
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* Kyungmin Park <[email protected]> |
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*/ |
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#ifndef __SAMSUNG_ONENAND_H__ |
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#define __SAMSUNG_ONENAND_H__ |
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/* |
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* OneNAND Controller |
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*/ |
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#define MEM_CFG_OFFSET 0x0000 |
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#define BURST_LEN_OFFSET 0x0010 |
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#define MEM_RESET_OFFSET 0x0020 |
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#define INT_ERR_STAT_OFFSET 0x0030 |
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#define INT_ERR_MASK_OFFSET 0x0040 |
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#define INT_ERR_ACK_OFFSET 0x0050 |
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#define ECC_ERR_STAT_OFFSET 0x0060 |
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#define MANUFACT_ID_OFFSET 0x0070 |
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#define DEVICE_ID_OFFSET 0x0080 |
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#define DATA_BUF_SIZE_OFFSET 0x0090 |
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#define BOOT_BUF_SIZE_OFFSET 0x00A0 |
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#define BUF_AMOUNT_OFFSET 0x00B0 |
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#define TECH_OFFSET 0x00C0 |
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#define FBA_WIDTH_OFFSET 0x00D0 |
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#define FPA_WIDTH_OFFSET 0x00E0 |
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#define FSA_WIDTH_OFFSET 0x00F0 |
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#define TRANS_SPARE_OFFSET 0x0140 |
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#define DBS_DFS_WIDTH_OFFSET 0x0160 |
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#define INT_PIN_ENABLE_OFFSET 0x01A0 |
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#define ACC_CLOCK_OFFSET 0x01C0 |
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#define FLASH_VER_ID_OFFSET 0x01F0 |
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#define FLASH_AUX_CNTRL_OFFSET 0x0300 /* s3c64xx only */ |
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#define ONENAND_MEM_RESET_HOT 0x3 |
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#define ONENAND_MEM_RESET_COLD 0x2 |
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#define ONENAND_MEM_RESET_WARM 0x1 |
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#define CACHE_OP_ERR (1 << 13) |
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#define RST_CMP (1 << 12) |
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#define RDY_ACT (1 << 11) |
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#define INT_ACT (1 << 10) |
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#define UNSUP_CMD (1 << 9) |
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#define LOCKED_BLK (1 << 8) |
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#define BLK_RW_CMP (1 << 7) |
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#define ERS_CMP (1 << 6) |
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#define PGM_CMP (1 << 5) |
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#define LOAD_CMP (1 << 4) |
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#define ERS_FAIL (1 << 3) |
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#define PGM_FAIL (1 << 2) |
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#define INT_TO (1 << 1) |
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#define LD_FAIL_ECC_ERR (1 << 0) |
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#define TSRF (1 << 0) |
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#endif
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