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496 lines
13 KiB
496 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* LPDDR2-NVM MTD driver. This module provides read, write, erase, lock/unlock |
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* support for LPDDR2-NVM PCM memories |
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* |
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* Copyright © 2012 Micron Technology, Inc. |
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* |
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* Vincenzo Aliberti <[email protected]> |
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* Domenico Manna <[email protected]> |
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* Many thanks to Andrea Vigilante for initial enabling |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": %s: " fmt, __func__ |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/mtd/map.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/slab.h> |
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#include <linux/platform_device.h> |
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#include <linux/ioport.h> |
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#include <linux/err.h> |
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/* Parameters */ |
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#define ERASE_BLOCKSIZE (0x00020000/2) /* in Word */ |
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#define WRITE_BUFFSIZE (0x00000400/2) /* in Word */ |
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#define OW_BASE_ADDRESS 0x00000000 /* OW offset */ |
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#define BUS_WIDTH 0x00000020 /* x32 devices */ |
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/* PFOW symbols address offset */ |
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#define PFOW_QUERY_STRING_P (0x0000/2) /* in Word */ |
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#define PFOW_QUERY_STRING_F (0x0002/2) /* in Word */ |
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#define PFOW_QUERY_STRING_O (0x0004/2) /* in Word */ |
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#define PFOW_QUERY_STRING_W (0x0006/2) /* in Word */ |
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/* OW registers address */ |
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#define CMD_CODE_OFS (0x0080/2) /* in Word */ |
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#define CMD_DATA_OFS (0x0084/2) /* in Word */ |
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#define CMD_ADD_L_OFS (0x0088/2) /* in Word */ |
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#define CMD_ADD_H_OFS (0x008A/2) /* in Word */ |
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#define MPR_L_OFS (0x0090/2) /* in Word */ |
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#define MPR_H_OFS (0x0092/2) /* in Word */ |
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#define CMD_EXEC_OFS (0x00C0/2) /* in Word */ |
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#define STATUS_REG_OFS (0x00CC/2) /* in Word */ |
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#define PRG_BUFFER_OFS (0x0010/2) /* in Word */ |
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/* Datamask */ |
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#define MR_CFGMASK 0x8000 |
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#define SR_OK_DATAMASK 0x0080 |
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/* LPDDR2-NVM Commands */ |
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#define LPDDR2_NVM_LOCK 0x0061 |
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#define LPDDR2_NVM_UNLOCK 0x0062 |
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#define LPDDR2_NVM_SW_PROGRAM 0x0041 |
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#define LPDDR2_NVM_SW_OVERWRITE 0x0042 |
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#define LPDDR2_NVM_BUF_PROGRAM 0x00E9 |
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#define LPDDR2_NVM_BUF_OVERWRITE 0x00EA |
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#define LPDDR2_NVM_ERASE 0x0020 |
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/* LPDDR2-NVM Registers offset */ |
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#define LPDDR2_MODE_REG_DATA 0x0040 |
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#define LPDDR2_MODE_REG_CFG 0x0050 |
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/* |
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* Internal Type Definitions |
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* pcm_int_data contains memory controller details: |
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* @reg_data : LPDDR2_MODE_REG_DATA register address after remapping |
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* @reg_cfg : LPDDR2_MODE_REG_CFG register address after remapping |
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* &bus_width: memory bus-width (eg: x16 2 Bytes, x32 4 Bytes) |
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*/ |
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struct pcm_int_data { |
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void __iomem *ctl_regs; |
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int bus_width; |
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}; |
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static DEFINE_MUTEX(lpdd2_nvm_mutex); |
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/* |
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* Build a map_word starting from an u_long |
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*/ |
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static inline map_word build_map_word(u_long myword) |
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{ |
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map_word val = { {0} }; |
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val.x[0] = myword; |
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return val; |
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} |
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/* |
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* Build Mode Register Configuration DataMask based on device bus-width |
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*/ |
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static inline u_int build_mr_cfgmask(u_int bus_width) |
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{ |
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u_int val = MR_CFGMASK; |
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if (bus_width == 0x0004) /* x32 device */ |
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val = val << 16; |
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return val; |
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} |
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/* |
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* Build Status Register OK DataMask based on device bus-width |
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*/ |
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static inline u_int build_sr_ok_datamask(u_int bus_width) |
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{ |
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u_int val = SR_OK_DATAMASK; |
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if (bus_width == 0x0004) /* x32 device */ |
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val = (val << 16)+val; |
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return val; |
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} |
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/* |
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* Evaluates Overlay Window Control Registers address |
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*/ |
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static inline u_long ow_reg_add(struct map_info *map, u_long offset) |
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{ |
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u_long val = 0; |
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struct pcm_int_data *pcm_data = map->fldrv_priv; |
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val = map->pfow_base + offset*pcm_data->bus_width; |
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return val; |
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} |
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/* |
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* Enable lpddr2-nvm Overlay Window |
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* Overlay Window is a memory mapped area containing all LPDDR2-NVM registers |
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* used by device commands as well as uservisible resources like Device Status |
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* Register, Device ID, etc |
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*/ |
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static inline void ow_enable(struct map_info *map) |
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{ |
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struct pcm_int_data *pcm_data = map->fldrv_priv; |
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writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18, |
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pcm_data->ctl_regs + LPDDR2_MODE_REG_CFG); |
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writel_relaxed(0x01, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA); |
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} |
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/* |
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* Disable lpddr2-nvm Overlay Window |
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* Overlay Window is a memory mapped area containing all LPDDR2-NVM registers |
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* used by device commands as well as uservisible resources like Device Status |
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* Register, Device ID, etc |
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*/ |
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static inline void ow_disable(struct map_info *map) |
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{ |
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struct pcm_int_data *pcm_data = map->fldrv_priv; |
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writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18, |
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pcm_data->ctl_regs + LPDDR2_MODE_REG_CFG); |
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writel_relaxed(0x02, pcm_data->ctl_regs + LPDDR2_MODE_REG_DATA); |
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} |
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/* |
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* Execute lpddr2-nvm operations |
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*/ |
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static int lpddr2_nvm_do_op(struct map_info *map, u_long cmd_code, |
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u_long cmd_data, u_long cmd_add, u_long cmd_mpr, u_char *buf) |
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{ |
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map_word add_l = { {0} }, add_h = { {0} }, mpr_l = { {0} }, |
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mpr_h = { {0} }, data_l = { {0} }, cmd = { {0} }, |
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exec_cmd = { {0} }, sr; |
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map_word data_h = { {0} }; /* only for 2x x16 devices stacked */ |
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u_long i, status_reg, prg_buff_ofs; |
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struct pcm_int_data *pcm_data = map->fldrv_priv; |
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u_int sr_ok_datamask = build_sr_ok_datamask(pcm_data->bus_width); |
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/* Builds low and high words for OW Control Registers */ |
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add_l.x[0] = cmd_add & 0x0000FFFF; |
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add_h.x[0] = (cmd_add >> 16) & 0x0000FFFF; |
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mpr_l.x[0] = cmd_mpr & 0x0000FFFF; |
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mpr_h.x[0] = (cmd_mpr >> 16) & 0x0000FFFF; |
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cmd.x[0] = cmd_code & 0x0000FFFF; |
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exec_cmd.x[0] = 0x0001; |
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data_l.x[0] = cmd_data & 0x0000FFFF; |
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data_h.x[0] = (cmd_data >> 16) & 0x0000FFFF; /* only for 2x x16 */ |
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/* Set Overlay Window Control Registers */ |
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map_write(map, cmd, ow_reg_add(map, CMD_CODE_OFS)); |
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map_write(map, data_l, ow_reg_add(map, CMD_DATA_OFS)); |
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map_write(map, add_l, ow_reg_add(map, CMD_ADD_L_OFS)); |
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map_write(map, add_h, ow_reg_add(map, CMD_ADD_H_OFS)); |
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map_write(map, mpr_l, ow_reg_add(map, MPR_L_OFS)); |
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map_write(map, mpr_h, ow_reg_add(map, MPR_H_OFS)); |
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if (pcm_data->bus_width == 0x0004) { /* 2x16 devices stacked */ |
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map_write(map, cmd, ow_reg_add(map, CMD_CODE_OFS) + 2); |
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map_write(map, data_h, ow_reg_add(map, CMD_DATA_OFS) + 2); |
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map_write(map, add_l, ow_reg_add(map, CMD_ADD_L_OFS) + 2); |
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map_write(map, add_h, ow_reg_add(map, CMD_ADD_H_OFS) + 2); |
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map_write(map, mpr_l, ow_reg_add(map, MPR_L_OFS) + 2); |
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map_write(map, mpr_h, ow_reg_add(map, MPR_H_OFS) + 2); |
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} |
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/* Fill Program Buffer */ |
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if ((cmd_code == LPDDR2_NVM_BUF_PROGRAM) || |
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(cmd_code == LPDDR2_NVM_BUF_OVERWRITE)) { |
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prg_buff_ofs = (map_read(map, |
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ow_reg_add(map, PRG_BUFFER_OFS))).x[0]; |
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for (i = 0; i < cmd_mpr; i++) { |
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map_write(map, build_map_word(buf[i]), map->pfow_base + |
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prg_buff_ofs + i); |
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} |
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} |
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/* Command Execute */ |
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map_write(map, exec_cmd, ow_reg_add(map, CMD_EXEC_OFS)); |
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if (pcm_data->bus_width == 0x0004) /* 2x16 devices stacked */ |
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map_write(map, exec_cmd, ow_reg_add(map, CMD_EXEC_OFS) + 2); |
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/* Status Register Check */ |
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do { |
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sr = map_read(map, ow_reg_add(map, STATUS_REG_OFS)); |
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status_reg = sr.x[0]; |
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if (pcm_data->bus_width == 0x0004) {/* 2x16 devices stacked */ |
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sr = map_read(map, ow_reg_add(map, |
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STATUS_REG_OFS) + 2); |
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status_reg += sr.x[0] << 16; |
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} |
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} while ((status_reg & sr_ok_datamask) != sr_ok_datamask); |
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return (((status_reg & sr_ok_datamask) == sr_ok_datamask) ? 0 : -EIO); |
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} |
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/* |
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* Execute lpddr2-nvm operations @ block level |
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*/ |
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static int lpddr2_nvm_do_block_op(struct mtd_info *mtd, loff_t start_add, |
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uint64_t len, u_char block_op) |
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{ |
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struct map_info *map = mtd->priv; |
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u_long add, end_add; |
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int ret = 0; |
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mutex_lock(&lpdd2_nvm_mutex); |
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ow_enable(map); |
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add = start_add; |
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end_add = add + len; |
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do { |
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ret = lpddr2_nvm_do_op(map, block_op, 0x00, add, add, NULL); |
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if (ret) |
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goto out; |
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add += mtd->erasesize; |
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} while (add < end_add); |
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out: |
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ow_disable(map); |
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mutex_unlock(&lpdd2_nvm_mutex); |
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return ret; |
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} |
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/* |
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* verify presence of PFOW string |
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*/ |
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static int lpddr2_nvm_pfow_present(struct map_info *map) |
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{ |
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map_word pfow_val[4]; |
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unsigned int found = 1; |
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mutex_lock(&lpdd2_nvm_mutex); |
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ow_enable(map); |
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/* Load string from array */ |
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pfow_val[0] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_P)); |
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pfow_val[1] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_F)); |
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pfow_val[2] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_O)); |
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pfow_val[3] = map_read(map, ow_reg_add(map, PFOW_QUERY_STRING_W)); |
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/* Verify the string loaded vs expected */ |
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if (!map_word_equal(map, build_map_word('P'), pfow_val[0])) |
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found = 0; |
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if (!map_word_equal(map, build_map_word('F'), pfow_val[1])) |
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found = 0; |
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if (!map_word_equal(map, build_map_word('O'), pfow_val[2])) |
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found = 0; |
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if (!map_word_equal(map, build_map_word('W'), pfow_val[3])) |
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found = 0; |
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ow_disable(map); |
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mutex_unlock(&lpdd2_nvm_mutex); |
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return found; |
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} |
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/* |
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* lpddr2_nvm driver read method |
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*/ |
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static int lpddr2_nvm_read(struct mtd_info *mtd, loff_t start_add, |
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size_t len, size_t *retlen, u_char *buf) |
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{ |
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struct map_info *map = mtd->priv; |
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mutex_lock(&lpdd2_nvm_mutex); |
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*retlen = len; |
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map_copy_from(map, buf, start_add, *retlen); |
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mutex_unlock(&lpdd2_nvm_mutex); |
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return 0; |
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} |
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/* |
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* lpddr2_nvm driver write method |
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*/ |
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static int lpddr2_nvm_write(struct mtd_info *mtd, loff_t start_add, |
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size_t len, size_t *retlen, const u_char *buf) |
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{ |
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struct map_info *map = mtd->priv; |
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struct pcm_int_data *pcm_data = map->fldrv_priv; |
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u_long add, current_len, tot_len, target_len, my_data; |
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u_char *write_buf = (u_char *)buf; |
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int ret = 0; |
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mutex_lock(&lpdd2_nvm_mutex); |
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ow_enable(map); |
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/* Set start value for the variables */ |
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add = start_add; |
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target_len = len; |
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tot_len = 0; |
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while (tot_len < target_len) { |
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if (!(IS_ALIGNED(add, mtd->writesize))) { /* do sw program */ |
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my_data = write_buf[tot_len]; |
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my_data += (write_buf[tot_len+1]) << 8; |
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if (pcm_data->bus_width == 0x0004) {/* 2x16 devices */ |
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my_data += (write_buf[tot_len+2]) << 16; |
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my_data += (write_buf[tot_len+3]) << 24; |
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} |
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ret = lpddr2_nvm_do_op(map, LPDDR2_NVM_SW_OVERWRITE, |
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my_data, add, 0x00, NULL); |
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if (ret) |
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goto out; |
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add += pcm_data->bus_width; |
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tot_len += pcm_data->bus_width; |
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} else { /* do buffer program */ |
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current_len = min(target_len - tot_len, |
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(u_long) mtd->writesize); |
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ret = lpddr2_nvm_do_op(map, LPDDR2_NVM_BUF_OVERWRITE, |
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0x00, add, current_len, write_buf + tot_len); |
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if (ret) |
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goto out; |
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add += current_len; |
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tot_len += current_len; |
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} |
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} |
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out: |
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*retlen = tot_len; |
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ow_disable(map); |
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mutex_unlock(&lpdd2_nvm_mutex); |
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return ret; |
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} |
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/* |
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* lpddr2_nvm driver erase method |
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*/ |
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static int lpddr2_nvm_erase(struct mtd_info *mtd, struct erase_info *instr) |
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{ |
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return lpddr2_nvm_do_block_op(mtd, instr->addr, instr->len, |
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LPDDR2_NVM_ERASE); |
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} |
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/* |
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* lpddr2_nvm driver unlock method |
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*/ |
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static int lpddr2_nvm_unlock(struct mtd_info *mtd, loff_t start_add, |
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uint64_t len) |
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{ |
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return lpddr2_nvm_do_block_op(mtd, start_add, len, LPDDR2_NVM_UNLOCK); |
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} |
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/* |
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* lpddr2_nvm driver lock method |
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*/ |
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static int lpddr2_nvm_lock(struct mtd_info *mtd, loff_t start_add, |
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uint64_t len) |
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{ |
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return lpddr2_nvm_do_block_op(mtd, start_add, len, LPDDR2_NVM_LOCK); |
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} |
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static const struct mtd_info lpddr2_nvm_mtd_info = { |
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.type = MTD_RAM, |
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.writesize = 1, |
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.flags = (MTD_CAP_NVRAM | MTD_POWERUP_LOCK), |
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._read = lpddr2_nvm_read, |
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._write = lpddr2_nvm_write, |
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._erase = lpddr2_nvm_erase, |
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._unlock = lpddr2_nvm_unlock, |
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._lock = lpddr2_nvm_lock, |
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}; |
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/* |
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* lpddr2_nvm driver probe method |
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*/ |
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static int lpddr2_nvm_probe(struct platform_device *pdev) |
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{ |
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struct map_info *map; |
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struct mtd_info *mtd; |
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struct resource *add_range; |
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struct resource *control_regs; |
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struct pcm_int_data *pcm_data; |
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/* Allocate memory control_regs data structures */ |
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pcm_data = devm_kzalloc(&pdev->dev, sizeof(*pcm_data), GFP_KERNEL); |
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if (!pcm_data) |
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return -ENOMEM; |
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pcm_data->bus_width = BUS_WIDTH; |
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/* Allocate memory for map_info & mtd_info data structures */ |
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map = devm_kzalloc(&pdev->dev, sizeof(*map), GFP_KERNEL); |
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if (!map) |
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return -ENOMEM; |
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mtd = devm_kzalloc(&pdev->dev, sizeof(*mtd), GFP_KERNEL); |
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if (!mtd) |
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return -ENOMEM; |
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/* lpddr2_nvm address range */ |
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add_range = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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/* Populate map_info data structure */ |
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*map = (struct map_info) { |
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.virt = devm_ioremap_resource(&pdev->dev, add_range), |
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.name = pdev->dev.init_name, |
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.phys = add_range->start, |
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.size = resource_size(add_range), |
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.bankwidth = pcm_data->bus_width / 2, |
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.pfow_base = OW_BASE_ADDRESS, |
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.fldrv_priv = pcm_data, |
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}; |
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if (IS_ERR(map->virt)) |
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return PTR_ERR(map->virt); |
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simple_map_init(map); /* fill with default methods */ |
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control_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
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pcm_data->ctl_regs = devm_ioremap_resource(&pdev->dev, control_regs); |
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if (IS_ERR(pcm_data->ctl_regs)) |
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return PTR_ERR(pcm_data->ctl_regs); |
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/* Populate mtd_info data structure */ |
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*mtd = lpddr2_nvm_mtd_info; |
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mtd->dev.parent = &pdev->dev; |
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mtd->name = pdev->dev.init_name; |
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mtd->priv = map; |
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mtd->size = resource_size(add_range); |
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mtd->erasesize = ERASE_BLOCKSIZE * pcm_data->bus_width; |
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mtd->writebufsize = WRITE_BUFFSIZE * pcm_data->bus_width; |
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/* Verify the presence of the device looking for PFOW string */ |
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if (!lpddr2_nvm_pfow_present(map)) { |
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pr_err("device not recognized\n"); |
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return -EINVAL; |
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} |
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/* Parse partitions and register the MTD device */ |
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return mtd_device_register(mtd, NULL, 0); |
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} |
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/* |
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* lpddr2_nvm driver remove method |
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*/ |
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static int lpddr2_nvm_remove(struct platform_device *pdev) |
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{ |
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return mtd_device_unregister(dev_get_drvdata(&pdev->dev)); |
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} |
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/* Initialize platform_driver data structure for lpddr2_nvm */ |
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static struct platform_driver lpddr2_nvm_drv = { |
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.driver = { |
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.name = "lpddr2_nvm", |
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}, |
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.probe = lpddr2_nvm_probe, |
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.remove = lpddr2_nvm_remove, |
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}; |
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module_platform_driver(lpddr2_nvm_drv); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Vincenzo Aliberti <[email protected]>"); |
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MODULE_DESCRIPTION("MTD driver for LPDDR2-NVM PCM memories");
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