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779 lines
19 KiB
779 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* linux/drivers/mfd/ucb1x00-core.c |
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* |
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* Copyright (C) 2001 Russell King, All Rights Reserved. |
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* |
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* The UCB1x00 core driver provides basic services for handling IO, |
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* the ADC, interrupts, and accessing registers. It is designed |
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* such that everything goes through this layer, thereby providing |
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* a consistent locking methodology, as well as allowing the drivers |
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* to be used on other non-MCP-enabled hardware platforms. |
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* |
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* Note that all locks are private to this file. Nothing else may |
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* touch them. |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/sched.h> |
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#include <linux/slab.h> |
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#include <linux/init.h> |
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#include <linux/errno.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/device.h> |
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#include <linux/mutex.h> |
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#include <linux/mfd/ucb1x00.h> |
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#include <linux/pm.h> |
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#include <linux/gpio/driver.h> |
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static DEFINE_MUTEX(ucb1x00_mutex); |
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static LIST_HEAD(ucb1x00_drivers); |
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static LIST_HEAD(ucb1x00_devices); |
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|
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/** |
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* ucb1x00_io_set_dir - set IO direction |
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* @ucb: UCB1x00 structure describing chip |
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* @in: bitfield of IO pins to be set as inputs |
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* @out: bitfield of IO pins to be set as outputs |
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* |
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* Set the IO direction of the ten general purpose IO pins on |
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* the UCB1x00 chip. The @in bitfield has priority over the |
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* @out bitfield, in that if you specify a pin as both input |
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* and output, it will end up as an input. |
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* |
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* ucb1x00_enable must have been called to enable the comms |
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* before using this function. |
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* |
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* This function takes a spinlock, disabling interrupts. |
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*/ |
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void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(&ucb->io_lock, flags); |
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ucb->io_dir |= out; |
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ucb->io_dir &= ~in; |
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ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
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spin_unlock_irqrestore(&ucb->io_lock, flags); |
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} |
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|
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/** |
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* ucb1x00_io_write - set or clear IO outputs |
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* @ucb: UCB1x00 structure describing chip |
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* @set: bitfield of IO pins to set to logic '1' |
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* @clear: bitfield of IO pins to set to logic '0' |
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* |
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* Set the IO output state of the specified IO pins. The value |
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* is retained if the pins are subsequently configured as inputs. |
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* The @clear bitfield has priority over the @set bitfield - |
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* outputs will be cleared. |
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* |
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* ucb1x00_enable must have been called to enable the comms |
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* before using this function. |
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* |
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* This function takes a spinlock, disabling interrupts. |
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*/ |
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void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(&ucb->io_lock, flags); |
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ucb->io_out |= set; |
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ucb->io_out &= ~clear; |
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ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
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spin_unlock_irqrestore(&ucb->io_lock, flags); |
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} |
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|
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/** |
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* ucb1x00_io_read - read the current state of the IO pins |
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* @ucb: UCB1x00 structure describing chip |
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* |
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* Return a bitfield describing the logic state of the ten |
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* general purpose IO pins. |
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* |
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* ucb1x00_enable must have been called to enable the comms |
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* before using this function. |
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* |
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* This function does not take any mutexes or spinlocks. |
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*/ |
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unsigned int ucb1x00_io_read(struct ucb1x00 *ucb) |
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{ |
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return ucb1x00_reg_read(ucb, UCB_IO_DATA); |
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} |
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static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
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{ |
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struct ucb1x00 *ucb = gpiochip_get_data(chip); |
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unsigned long flags; |
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spin_lock_irqsave(&ucb->io_lock, flags); |
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if (value) |
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ucb->io_out |= 1 << offset; |
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else |
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ucb->io_out &= ~(1 << offset); |
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ucb1x00_enable(ucb); |
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ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
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ucb1x00_disable(ucb); |
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spin_unlock_irqrestore(&ucb->io_lock, flags); |
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} |
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static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct ucb1x00 *ucb = gpiochip_get_data(chip); |
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unsigned val; |
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ucb1x00_enable(ucb); |
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val = ucb1x00_reg_read(ucb, UCB_IO_DATA); |
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ucb1x00_disable(ucb); |
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return !!(val & (1 << offset)); |
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} |
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static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct ucb1x00 *ucb = gpiochip_get_data(chip); |
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unsigned long flags; |
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spin_lock_irqsave(&ucb->io_lock, flags); |
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ucb->io_dir &= ~(1 << offset); |
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ucb1x00_enable(ucb); |
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ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
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ucb1x00_disable(ucb); |
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spin_unlock_irqrestore(&ucb->io_lock, flags); |
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return 0; |
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} |
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static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset |
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, int value) |
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{ |
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struct ucb1x00 *ucb = gpiochip_get_data(chip); |
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unsigned long flags; |
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unsigned old, mask = 1 << offset; |
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spin_lock_irqsave(&ucb->io_lock, flags); |
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old = ucb->io_out; |
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if (value) |
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ucb->io_out |= mask; |
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else |
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ucb->io_out &= ~mask; |
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ucb1x00_enable(ucb); |
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if (old != ucb->io_out) |
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ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
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if (!(ucb->io_dir & mask)) { |
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ucb->io_dir |= mask; |
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ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
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} |
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ucb1x00_disable(ucb); |
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spin_unlock_irqrestore(&ucb->io_lock, flags); |
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return 0; |
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} |
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static int ucb1x00_to_irq(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct ucb1x00 *ucb = gpiochip_get_data(chip); |
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return ucb->irq_base > 0 ? ucb->irq_base + offset : -ENXIO; |
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} |
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/* |
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* UCB1300 data sheet says we must: |
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* 1. enable ADC => 5us (including reference startup time) |
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* 2. select input => 51*tsibclk => 4.3us |
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* 3. start conversion => 102*tsibclk => 8.5us |
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* (tsibclk = 1/11981000) |
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* Period between SIB 128-bit frames = 10.7us |
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*/ |
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/** |
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* ucb1x00_adc_enable - enable the ADC converter |
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* @ucb: UCB1x00 structure describing chip |
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* |
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* Enable the ucb1x00 and ADC converter on the UCB1x00 for use. |
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* Any code wishing to use the ADC converter must call this |
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* function prior to using it. |
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* |
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* This function takes the ADC mutex to prevent two or more |
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* concurrent uses, and therefore may sleep. As a result, it |
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* can only be called from process context, not interrupt |
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* context. |
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* |
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* You should release the ADC as soon as possible using |
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* ucb1x00_adc_disable. |
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*/ |
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void ucb1x00_adc_enable(struct ucb1x00 *ucb) |
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{ |
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mutex_lock(&ucb->adc_mutex); |
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ucb->adc_cr |= UCB_ADC_ENA; |
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ucb1x00_enable(ucb); |
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ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); |
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} |
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/** |
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* ucb1x00_adc_read - read the specified ADC channel |
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* @ucb: UCB1x00 structure describing chip |
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* @adc_channel: ADC channel mask |
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* @sync: wait for syncronisation pulse. |
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* |
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* Start an ADC conversion and wait for the result. Note that |
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* synchronised ADC conversions (via the ADCSYNC pin) must wait |
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* until the trigger is asserted and the conversion is finished. |
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* |
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* This function currently spins waiting for the conversion to |
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* complete (2 frames max without sync). |
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* |
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* If called for a synchronised ADC conversion, it may sleep |
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* with the ADC mutex held. |
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*/ |
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unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync) |
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{ |
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unsigned int val; |
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if (sync) |
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adc_channel |= UCB_ADC_SYNC_ENA; |
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ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel); |
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ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START); |
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for (;;) { |
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val = ucb1x00_reg_read(ucb, UCB_ADC_DATA); |
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if (val & UCB_ADC_DAT_VAL) |
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break; |
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/* yield to other processes */ |
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set_current_state(TASK_INTERRUPTIBLE); |
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schedule_timeout(1); |
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} |
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return UCB_ADC_DAT(val); |
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} |
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/** |
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* ucb1x00_adc_disable - disable the ADC converter |
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* @ucb: UCB1x00 structure describing chip |
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* |
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* Disable the ADC converter and release the ADC mutex. |
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*/ |
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void ucb1x00_adc_disable(struct ucb1x00 *ucb) |
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{ |
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ucb->adc_cr &= ~UCB_ADC_ENA; |
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ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); |
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ucb1x00_disable(ucb); |
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mutex_unlock(&ucb->adc_mutex); |
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} |
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/* |
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* UCB1x00 Interrupt handling. |
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* |
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* The UCB1x00 can generate interrupts when the SIBCLK is stopped. |
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* Since we need to read an internal register, we must re-enable |
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* SIBCLK to talk to the chip. We leave the clock running until |
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* we have finished processing all interrupts from the chip. |
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*/ |
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static void ucb1x00_irq(struct irq_desc *desc) |
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{ |
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struct ucb1x00 *ucb = irq_desc_get_handler_data(desc); |
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unsigned int isr, i; |
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ucb1x00_enable(ucb); |
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isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS); |
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ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr); |
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ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); |
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for (i = 0; i < 16 && isr; i++, isr >>= 1) |
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if (isr & 1) |
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generic_handle_irq(ucb->irq_base + i); |
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ucb1x00_disable(ucb); |
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} |
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static void ucb1x00_irq_update(struct ucb1x00 *ucb, unsigned mask) |
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{ |
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ucb1x00_enable(ucb); |
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if (ucb->irq_ris_enbl & mask) |
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ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & |
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ucb->irq_mask); |
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if (ucb->irq_fal_enbl & mask) |
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ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & |
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ucb->irq_mask); |
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ucb1x00_disable(ucb); |
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} |
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static void ucb1x00_irq_noop(struct irq_data *data) |
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{ |
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} |
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static void ucb1x00_irq_mask(struct irq_data *data) |
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{ |
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struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); |
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unsigned mask = 1 << (data->irq - ucb->irq_base); |
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raw_spin_lock(&ucb->irq_lock); |
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ucb->irq_mask &= ~mask; |
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ucb1x00_irq_update(ucb, mask); |
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raw_spin_unlock(&ucb->irq_lock); |
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} |
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static void ucb1x00_irq_unmask(struct irq_data *data) |
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{ |
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struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); |
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unsigned mask = 1 << (data->irq - ucb->irq_base); |
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raw_spin_lock(&ucb->irq_lock); |
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ucb->irq_mask |= mask; |
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ucb1x00_irq_update(ucb, mask); |
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raw_spin_unlock(&ucb->irq_lock); |
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} |
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static int ucb1x00_irq_set_type(struct irq_data *data, unsigned int type) |
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{ |
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struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); |
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unsigned mask = 1 << (data->irq - ucb->irq_base); |
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raw_spin_lock(&ucb->irq_lock); |
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if (type & IRQ_TYPE_EDGE_RISING) |
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ucb->irq_ris_enbl |= mask; |
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else |
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ucb->irq_ris_enbl &= ~mask; |
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if (type & IRQ_TYPE_EDGE_FALLING) |
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ucb->irq_fal_enbl |= mask; |
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else |
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ucb->irq_fal_enbl &= ~mask; |
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if (ucb->irq_mask & mask) { |
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ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & |
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ucb->irq_mask); |
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ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & |
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ucb->irq_mask); |
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} |
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raw_spin_unlock(&ucb->irq_lock); |
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return 0; |
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} |
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static int ucb1x00_irq_set_wake(struct irq_data *data, unsigned int on) |
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{ |
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struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); |
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struct ucb1x00_plat_data *pdata = ucb->mcp->attached_device.platform_data; |
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unsigned mask = 1 << (data->irq - ucb->irq_base); |
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if (!pdata || !pdata->can_wakeup) |
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return -EINVAL; |
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raw_spin_lock(&ucb->irq_lock); |
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if (on) |
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ucb->irq_wake |= mask; |
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else |
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ucb->irq_wake &= ~mask; |
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raw_spin_unlock(&ucb->irq_lock); |
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return 0; |
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} |
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static struct irq_chip ucb1x00_irqchip = { |
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.name = "ucb1x00", |
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.irq_ack = ucb1x00_irq_noop, |
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.irq_mask = ucb1x00_irq_mask, |
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.irq_unmask = ucb1x00_irq_unmask, |
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.irq_set_type = ucb1x00_irq_set_type, |
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.irq_set_wake = ucb1x00_irq_set_wake, |
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}; |
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static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv) |
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{ |
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struct ucb1x00_dev *dev; |
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int ret; |
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dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL); |
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if (!dev) |
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return -ENOMEM; |
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dev->ucb = ucb; |
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dev->drv = drv; |
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ret = drv->add(dev); |
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if (ret) { |
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kfree(dev); |
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return ret; |
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} |
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list_add_tail(&dev->dev_node, &ucb->devs); |
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list_add_tail(&dev->drv_node, &drv->devs); |
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return ret; |
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} |
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static void ucb1x00_remove_dev(struct ucb1x00_dev *dev) |
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{ |
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dev->drv->remove(dev); |
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list_del(&dev->dev_node); |
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list_del(&dev->drv_node); |
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kfree(dev); |
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} |
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|
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/* |
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* Try to probe our interrupt, rather than relying on lots of |
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* hard-coded machine dependencies. For reference, the expected |
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* IRQ mappings are: |
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* |
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* Machine Default IRQ |
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* adsbitsy IRQ_GPCIN4 |
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* cerf IRQ_GPIO_UCB1200_IRQ |
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* flexanet IRQ_GPIO_GUI |
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* freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ |
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* graphicsclient ADS_EXT_IRQ(8) |
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* graphicsmaster ADS_EXT_IRQ(8) |
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* lart LART_IRQ_UCB1200 |
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* omnimeter IRQ_GPIO23 |
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* pfs168 IRQ_GPIO_UCB1300_IRQ |
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* simpad IRQ_GPIO_UCB1300_IRQ |
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* shannon SHANNON_IRQ_GPIO_IRQ_CODEC |
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* yopy IRQ_GPIO_UCB1200_IRQ |
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*/ |
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static int ucb1x00_detect_irq(struct ucb1x00 *ucb) |
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{ |
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unsigned long mask; |
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mask = probe_irq_on(); |
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|
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/* |
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* Enable the ADC interrupt. |
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*/ |
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ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC); |
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ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC); |
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ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); |
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ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); |
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|
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/* |
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* Cause an ADC interrupt. |
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*/ |
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ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); |
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ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START); |
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|
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/* |
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* Wait for the conversion to complete. |
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*/ |
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while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0); |
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ucb1x00_reg_write(ucb, UCB_ADC_CR, 0); |
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|
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/* |
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* Disable and clear interrupt. |
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*/ |
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ucb1x00_reg_write(ucb, UCB_IE_RIS, 0); |
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ucb1x00_reg_write(ucb, UCB_IE_FAL, 0); |
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ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); |
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ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); |
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|
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/* |
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* Read triggered interrupt. |
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*/ |
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return probe_irq_off(mask); |
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} |
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|
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static void ucb1x00_release(struct device *dev) |
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{ |
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struct ucb1x00 *ucb = classdev_to_ucb1x00(dev); |
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kfree(ucb); |
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} |
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static struct class ucb1x00_class = { |
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.name = "ucb1x00", |
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.dev_release = ucb1x00_release, |
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}; |
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static int ucb1x00_probe(struct mcp *mcp) |
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{ |
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struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
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struct ucb1x00_driver *drv; |
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struct ucb1x00 *ucb; |
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unsigned id, i, irq_base; |
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int ret = -ENODEV; |
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/* Tell the platform to deassert the UCB1x00 reset */ |
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if (pdata && pdata->reset) |
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pdata->reset(UCB_RST_PROBE); |
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mcp_enable(mcp); |
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id = mcp_reg_read(mcp, UCB_ID); |
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mcp_disable(mcp); |
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if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) { |
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printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id); |
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goto out; |
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} |
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ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL); |
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ret = -ENOMEM; |
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if (!ucb) |
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goto out; |
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device_initialize(&ucb->dev); |
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ucb->dev.class = &ucb1x00_class; |
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ucb->dev.parent = &mcp->attached_device; |
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dev_set_name(&ucb->dev, "ucb1x00"); |
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|
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raw_spin_lock_init(&ucb->irq_lock); |
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spin_lock_init(&ucb->io_lock); |
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mutex_init(&ucb->adc_mutex); |
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|
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ucb->id = id; |
|
ucb->mcp = mcp; |
|
|
|
ret = device_add(&ucb->dev); |
|
if (ret) |
|
goto err_dev_add; |
|
|
|
ucb1x00_enable(ucb); |
|
ucb->irq = ucb1x00_detect_irq(ucb); |
|
ucb1x00_disable(ucb); |
|
if (!ucb->irq) { |
|
dev_err(&ucb->dev, "IRQ probe failed\n"); |
|
ret = -ENODEV; |
|
goto err_no_irq; |
|
} |
|
|
|
ucb->gpio.base = -1; |
|
irq_base = pdata ? pdata->irq_base : 0; |
|
ucb->irq_base = irq_alloc_descs(-1, irq_base, 16, -1); |
|
if (ucb->irq_base < 0) { |
|
dev_err(&ucb->dev, "unable to allocate 16 irqs: %d\n", |
|
ucb->irq_base); |
|
ret = ucb->irq_base; |
|
goto err_irq_alloc; |
|
} |
|
|
|
for (i = 0; i < 16; i++) { |
|
unsigned irq = ucb->irq_base + i; |
|
|
|
irq_set_chip_and_handler(irq, &ucb1x00_irqchip, handle_edge_irq); |
|
irq_set_chip_data(irq, ucb); |
|
irq_clear_status_flags(irq, IRQ_NOREQUEST); |
|
} |
|
|
|
irq_set_irq_type(ucb->irq, IRQ_TYPE_EDGE_RISING); |
|
irq_set_chained_handler_and_data(ucb->irq, ucb1x00_irq, ucb); |
|
|
|
if (pdata && pdata->gpio_base) { |
|
ucb->gpio.label = dev_name(&ucb->dev); |
|
ucb->gpio.parent = &ucb->dev; |
|
ucb->gpio.owner = THIS_MODULE; |
|
ucb->gpio.base = pdata->gpio_base; |
|
ucb->gpio.ngpio = 10; |
|
ucb->gpio.set = ucb1x00_gpio_set; |
|
ucb->gpio.get = ucb1x00_gpio_get; |
|
ucb->gpio.direction_input = ucb1x00_gpio_direction_input; |
|
ucb->gpio.direction_output = ucb1x00_gpio_direction_output; |
|
ucb->gpio.to_irq = ucb1x00_to_irq; |
|
ret = gpiochip_add_data(&ucb->gpio, ucb); |
|
if (ret) |
|
goto err_gpio_add; |
|
} else |
|
dev_info(&ucb->dev, "gpio_base not set so no gpiolib support"); |
|
|
|
mcp_set_drvdata(mcp, ucb); |
|
|
|
if (pdata) |
|
device_set_wakeup_capable(&ucb->dev, pdata->can_wakeup); |
|
|
|
INIT_LIST_HEAD(&ucb->devs); |
|
mutex_lock(&ucb1x00_mutex); |
|
list_add_tail(&ucb->node, &ucb1x00_devices); |
|
list_for_each_entry(drv, &ucb1x00_drivers, node) { |
|
ucb1x00_add_dev(ucb, drv); |
|
} |
|
mutex_unlock(&ucb1x00_mutex); |
|
|
|
return ret; |
|
|
|
err_gpio_add: |
|
irq_set_chained_handler(ucb->irq, NULL); |
|
err_irq_alloc: |
|
if (ucb->irq_base > 0) |
|
irq_free_descs(ucb->irq_base, 16); |
|
err_no_irq: |
|
device_del(&ucb->dev); |
|
err_dev_add: |
|
put_device(&ucb->dev); |
|
out: |
|
if (pdata && pdata->reset) |
|
pdata->reset(UCB_RST_PROBE_FAIL); |
|
return ret; |
|
} |
|
|
|
static void ucb1x00_remove(struct mcp *mcp) |
|
{ |
|
struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
|
struct ucb1x00 *ucb = mcp_get_drvdata(mcp); |
|
struct list_head *l, *n; |
|
|
|
mutex_lock(&ucb1x00_mutex); |
|
list_del(&ucb->node); |
|
list_for_each_safe(l, n, &ucb->devs) { |
|
struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node); |
|
ucb1x00_remove_dev(dev); |
|
} |
|
mutex_unlock(&ucb1x00_mutex); |
|
|
|
if (ucb->gpio.base != -1) |
|
gpiochip_remove(&ucb->gpio); |
|
|
|
irq_set_chained_handler(ucb->irq, NULL); |
|
irq_free_descs(ucb->irq_base, 16); |
|
device_unregister(&ucb->dev); |
|
|
|
if (pdata && pdata->reset) |
|
pdata->reset(UCB_RST_REMOVE); |
|
} |
|
|
|
int ucb1x00_register_driver(struct ucb1x00_driver *drv) |
|
{ |
|
struct ucb1x00 *ucb; |
|
|
|
INIT_LIST_HEAD(&drv->devs); |
|
mutex_lock(&ucb1x00_mutex); |
|
list_add_tail(&drv->node, &ucb1x00_drivers); |
|
list_for_each_entry(ucb, &ucb1x00_devices, node) { |
|
ucb1x00_add_dev(ucb, drv); |
|
} |
|
mutex_unlock(&ucb1x00_mutex); |
|
return 0; |
|
} |
|
|
|
void ucb1x00_unregister_driver(struct ucb1x00_driver *drv) |
|
{ |
|
struct list_head *n, *l; |
|
|
|
mutex_lock(&ucb1x00_mutex); |
|
list_del(&drv->node); |
|
list_for_each_safe(l, n, &drv->devs) { |
|
struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node); |
|
ucb1x00_remove_dev(dev); |
|
} |
|
mutex_unlock(&ucb1x00_mutex); |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int ucb1x00_suspend(struct device *dev) |
|
{ |
|
struct ucb1x00_plat_data *pdata = dev_get_platdata(dev); |
|
struct ucb1x00 *ucb = dev_get_drvdata(dev); |
|
struct ucb1x00_dev *udev; |
|
|
|
mutex_lock(&ucb1x00_mutex); |
|
list_for_each_entry(udev, &ucb->devs, dev_node) { |
|
if (udev->drv->suspend) |
|
udev->drv->suspend(udev); |
|
} |
|
mutex_unlock(&ucb1x00_mutex); |
|
|
|
if (ucb->irq_wake) { |
|
unsigned long flags; |
|
|
|
raw_spin_lock_irqsave(&ucb->irq_lock, flags); |
|
ucb1x00_enable(ucb); |
|
ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & |
|
ucb->irq_wake); |
|
ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & |
|
ucb->irq_wake); |
|
ucb1x00_disable(ucb); |
|
raw_spin_unlock_irqrestore(&ucb->irq_lock, flags); |
|
|
|
enable_irq_wake(ucb->irq); |
|
} else if (pdata && pdata->reset) |
|
pdata->reset(UCB_RST_SUSPEND); |
|
|
|
return 0; |
|
} |
|
|
|
static int ucb1x00_resume(struct device *dev) |
|
{ |
|
struct ucb1x00_plat_data *pdata = dev_get_platdata(dev); |
|
struct ucb1x00 *ucb = dev_get_drvdata(dev); |
|
struct ucb1x00_dev *udev; |
|
|
|
if (!ucb->irq_wake && pdata && pdata->reset) |
|
pdata->reset(UCB_RST_RESUME); |
|
|
|
ucb1x00_enable(ucb); |
|
ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
|
ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
|
|
|
if (ucb->irq_wake) { |
|
unsigned long flags; |
|
|
|
raw_spin_lock_irqsave(&ucb->irq_lock, flags); |
|
ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & |
|
ucb->irq_mask); |
|
ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & |
|
ucb->irq_mask); |
|
raw_spin_unlock_irqrestore(&ucb->irq_lock, flags); |
|
|
|
disable_irq_wake(ucb->irq); |
|
} |
|
ucb1x00_disable(ucb); |
|
|
|
mutex_lock(&ucb1x00_mutex); |
|
list_for_each_entry(udev, &ucb->devs, dev_node) { |
|
if (udev->drv->resume) |
|
udev->drv->resume(udev); |
|
} |
|
mutex_unlock(&ucb1x00_mutex); |
|
return 0; |
|
} |
|
#endif |
|
|
|
static SIMPLE_DEV_PM_OPS(ucb1x00_pm_ops, ucb1x00_suspend, ucb1x00_resume); |
|
|
|
static struct mcp_driver ucb1x00_driver = { |
|
.drv = { |
|
.name = "ucb1x00", |
|
.owner = THIS_MODULE, |
|
.pm = &ucb1x00_pm_ops, |
|
}, |
|
.probe = ucb1x00_probe, |
|
.remove = ucb1x00_remove, |
|
}; |
|
|
|
static int __init ucb1x00_init(void) |
|
{ |
|
int ret = class_register(&ucb1x00_class); |
|
if (ret == 0) { |
|
ret = mcp_driver_register(&ucb1x00_driver); |
|
if (ret) |
|
class_unregister(&ucb1x00_class); |
|
} |
|
return ret; |
|
} |
|
|
|
static void __exit ucb1x00_exit(void) |
|
{ |
|
mcp_driver_unregister(&ucb1x00_driver); |
|
class_unregister(&ucb1x00_class); |
|
} |
|
|
|
module_init(ucb1x00_init); |
|
module_exit(ucb1x00_exit); |
|
|
|
EXPORT_SYMBOL(ucb1x00_io_set_dir); |
|
EXPORT_SYMBOL(ucb1x00_io_write); |
|
EXPORT_SYMBOL(ucb1x00_io_read); |
|
|
|
EXPORT_SYMBOL(ucb1x00_adc_enable); |
|
EXPORT_SYMBOL(ucb1x00_adc_read); |
|
EXPORT_SYMBOL(ucb1x00_adc_disable); |
|
|
|
EXPORT_SYMBOL(ucb1x00_register_driver); |
|
EXPORT_SYMBOL(ucb1x00_unregister_driver); |
|
|
|
MODULE_ALIAS("mcp:ucb1x00"); |
|
MODULE_AUTHOR("Russell King <[email protected]>"); |
|
MODULE_DESCRIPTION("UCB1x00 core driver"); |
|
MODULE_LICENSE("GPL");
|
|
|