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1128 lines
29 KiB
1128 lines
29 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2008-2009 Texas Instruments Inc |
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* |
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* Image Sensor Interface (ISIF) driver |
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* |
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* This driver is for configuring the ISIF IP available on DM365 or any other |
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* TI SoCs. This is used for capturing yuv or bayer video or image data |
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* from a decoder or sensor. This IP is similar to the CCDC IP on DM355 |
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* and DM6446, but with enhanced or additional ip blocks. The driver |
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* configures the ISIF upon commands from the vpfe bridge driver through |
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* ccdc_hw_device interface. |
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* |
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* TODO: 1) Raw bayer parameter settings and bayer capture |
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* 2) Add support for control ioctl |
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*/ |
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#include <linux/delay.h> |
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#include <linux/platform_device.h> |
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#include <linux/uaccess.h> |
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#include <linux/io.h> |
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#include <linux/videodev2.h> |
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#include <linux/err.h> |
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#include <linux/module.h> |
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|
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#include <media/davinci/isif.h> |
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#include <media/davinci/vpss.h> |
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|
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#include "isif_regs.h" |
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#include "ccdc_hw_device.h" |
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|
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/* Defaults for module configuration parameters */ |
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static const struct isif_config_params_raw isif_config_defaults = { |
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.linearize = { |
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.en = 0, |
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.corr_shft = ISIF_NO_SHIFT, |
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.scale_fact = {1, 0}, |
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}, |
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.df_csc = { |
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.df_or_csc = 0, |
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.csc = { |
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.en = 0, |
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}, |
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}, |
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.dfc = { |
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.en = 0, |
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}, |
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.bclamp = { |
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.en = 0, |
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}, |
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.gain_offset = { |
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.gain = { |
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.r_ye = {1, 0}, |
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.gr_cy = {1, 0}, |
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.gb_g = {1, 0}, |
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.b_mg = {1, 0}, |
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}, |
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}, |
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.culling = { |
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.hcpat_odd = 0xff, |
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.hcpat_even = 0xff, |
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.vcpat = 0xff, |
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}, |
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.compress = { |
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.alg = ISIF_ALAW, |
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}, |
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}; |
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|
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/* ISIF operation configuration */ |
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static struct isif_oper_config { |
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struct device *dev; |
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enum vpfe_hw_if_type if_type; |
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struct isif_ycbcr_config ycbcr; |
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struct isif_params_raw bayer; |
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enum isif_data_pack data_pack; |
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/* ISIF base address */ |
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void __iomem *base_addr; |
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/* ISIF Linear Table 0 */ |
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void __iomem *linear_tbl0_addr; |
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/* ISIF Linear Table 1 */ |
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void __iomem *linear_tbl1_addr; |
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} isif_cfg = { |
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.ycbcr = { |
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.pix_fmt = CCDC_PIXFMT_YCBCR_8BIT, |
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.frm_fmt = CCDC_FRMFMT_INTERLACED, |
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.win = ISIF_WIN_NTSC, |
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.fid_pol = VPFE_PINPOL_POSITIVE, |
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.vd_pol = VPFE_PINPOL_POSITIVE, |
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.hd_pol = VPFE_PINPOL_POSITIVE, |
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.pix_order = CCDC_PIXORDER_CBYCRY, |
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.buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED, |
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}, |
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.bayer = { |
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.pix_fmt = CCDC_PIXFMT_RAW, |
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.frm_fmt = CCDC_FRMFMT_PROGRESSIVE, |
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.win = ISIF_WIN_VGA, |
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.fid_pol = VPFE_PINPOL_POSITIVE, |
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.vd_pol = VPFE_PINPOL_POSITIVE, |
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.hd_pol = VPFE_PINPOL_POSITIVE, |
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.gain = { |
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.r_ye = {1, 0}, |
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.gr_cy = {1, 0}, |
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.gb_g = {1, 0}, |
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.b_mg = {1, 0}, |
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}, |
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.cfa_pat = ISIF_CFA_PAT_MOSAIC, |
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.data_msb = ISIF_BIT_MSB_11, |
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.config_params = { |
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.data_shift = ISIF_NO_SHIFT, |
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.col_pat_field0 = { |
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.olop = ISIF_GREEN_BLUE, |
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.olep = ISIF_BLUE, |
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.elop = ISIF_RED, |
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.elep = ISIF_GREEN_RED, |
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}, |
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.col_pat_field1 = { |
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.olop = ISIF_GREEN_BLUE, |
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.olep = ISIF_BLUE, |
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.elop = ISIF_RED, |
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.elep = ISIF_GREEN_RED, |
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}, |
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.test_pat_gen = 0, |
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}, |
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}, |
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.data_pack = ISIF_DATA_PACK8, |
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}; |
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|
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/* Raw Bayer formats */ |
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static const u32 isif_raw_bayer_pix_formats[] = { |
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V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16}; |
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|
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/* Raw YUV formats */ |
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static const u32 isif_raw_yuv_pix_formats[] = { |
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V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV}; |
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|
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/* register access routines */ |
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static inline u32 regr(u32 offset) |
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{ |
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return __raw_readl(isif_cfg.base_addr + offset); |
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} |
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|
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static inline void regw(u32 val, u32 offset) |
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{ |
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__raw_writel(val, isif_cfg.base_addr + offset); |
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} |
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|
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/* reg_modify() - read, modify and write register */ |
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static inline u32 reg_modify(u32 mask, u32 val, u32 offset) |
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{ |
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u32 new_val = (regr(offset) & ~mask) | (val & mask); |
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|
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regw(new_val, offset); |
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return new_val; |
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} |
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static inline void regw_lin_tbl(u32 val, u32 offset, int i) |
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{ |
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if (!i) |
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__raw_writel(val, isif_cfg.linear_tbl0_addr + offset); |
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else |
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__raw_writel(val, isif_cfg.linear_tbl1_addr + offset); |
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} |
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|
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static void isif_disable_all_modules(void) |
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{ |
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/* disable BC */ |
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regw(0, CLAMPCFG); |
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/* disable vdfc */ |
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regw(0, DFCCTL); |
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/* disable CSC */ |
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regw(0, CSCCTL); |
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/* disable linearization */ |
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regw(0, LINCFG0); |
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/* disable other modules here as they are supported */ |
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} |
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static void isif_enable(int en) |
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{ |
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if (!en) { |
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/* Before disable isif, disable all ISIF modules */ |
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isif_disable_all_modules(); |
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/* |
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* wait for next VD. Assume lowest scan rate is 12 Hz. So |
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* 100 msec delay is good enough |
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*/ |
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msleep(100); |
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} |
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reg_modify(ISIF_SYNCEN_VDHDEN_MASK, en, SYNCEN); |
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} |
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static void isif_enable_output_to_sdram(int en) |
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{ |
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reg_modify(ISIF_SYNCEN_WEN_MASK, en << ISIF_SYNCEN_WEN_SHIFT, SYNCEN); |
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} |
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static void isif_config_culling(struct isif_cul *cul) |
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{ |
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u32 val; |
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|
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/* Horizontal pattern */ |
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val = (cul->hcpat_even << CULL_PAT_EVEN_LINE_SHIFT) | cul->hcpat_odd; |
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regw(val, CULH); |
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|
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/* vertical pattern */ |
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regw(cul->vcpat, CULV); |
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|
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/* LPF */ |
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reg_modify(ISIF_LPF_MASK << ISIF_LPF_SHIFT, |
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cul->en_lpf << ISIF_LPF_SHIFT, MODESET); |
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} |
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static void isif_config_gain_offset(void) |
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{ |
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struct isif_gain_offsets_adj *gain_off_p = |
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&isif_cfg.bayer.config_params.gain_offset; |
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u32 val; |
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val = (!!gain_off_p->gain_sdram_en << GAIN_SDRAM_EN_SHIFT) | |
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(!!gain_off_p->gain_ipipe_en << GAIN_IPIPE_EN_SHIFT) | |
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(!!gain_off_p->gain_h3a_en << GAIN_H3A_EN_SHIFT) | |
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(!!gain_off_p->offset_sdram_en << OFST_SDRAM_EN_SHIFT) | |
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(!!gain_off_p->offset_ipipe_en << OFST_IPIPE_EN_SHIFT) | |
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(!!gain_off_p->offset_h3a_en << OFST_H3A_EN_SHIFT); |
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reg_modify(GAIN_OFFSET_EN_MASK, val, CGAMMAWD); |
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val = (gain_off_p->gain.r_ye.integer << GAIN_INTEGER_SHIFT) | |
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gain_off_p->gain.r_ye.decimal; |
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regw(val, CRGAIN); |
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val = (gain_off_p->gain.gr_cy.integer << GAIN_INTEGER_SHIFT) | |
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gain_off_p->gain.gr_cy.decimal; |
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regw(val, CGRGAIN); |
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val = (gain_off_p->gain.gb_g.integer << GAIN_INTEGER_SHIFT) | |
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gain_off_p->gain.gb_g.decimal; |
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regw(val, CGBGAIN); |
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val = (gain_off_p->gain.b_mg.integer << GAIN_INTEGER_SHIFT) | |
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gain_off_p->gain.b_mg.decimal; |
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regw(val, CBGAIN); |
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regw(gain_off_p->offset, COFSTA); |
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} |
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static void isif_restore_defaults(void) |
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{ |
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enum vpss_ccdc_source_sel source = VPSS_CCDCIN; |
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dev_dbg(isif_cfg.dev, "\nstarting isif_restore_defaults..."); |
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isif_cfg.bayer.config_params = isif_config_defaults; |
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/* Enable clock to ISIF, IPIPEIF and BL */ |
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vpss_enable_clock(VPSS_CCDC_CLOCK, 1); |
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vpss_enable_clock(VPSS_IPIPEIF_CLOCK, 1); |
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vpss_enable_clock(VPSS_BL_CLOCK, 1); |
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/* Set default offset and gain */ |
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isif_config_gain_offset(); |
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vpss_select_ccdc_source(source); |
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dev_dbg(isif_cfg.dev, "\nEnd of isif_restore_defaults..."); |
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} |
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static int isif_open(struct device *device) |
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{ |
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isif_restore_defaults(); |
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return 0; |
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} |
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/* This function will configure the window size to be capture in ISIF reg */ |
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static void isif_setwin(struct v4l2_rect *image_win, |
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enum ccdc_frmfmt frm_fmt, int ppc) |
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{ |
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int horz_start, horz_nr_pixels; |
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int vert_start, vert_nr_lines; |
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int mid_img = 0; |
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dev_dbg(isif_cfg.dev, "\nStarting isif_setwin..."); |
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/* |
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* ppc - per pixel count. indicates how many pixels per cell |
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* output to SDRAM. example, for ycbcr, it is one y and one c, so 2. |
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* raw capture this is 1 |
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*/ |
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horz_start = image_win->left << (ppc - 1); |
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horz_nr_pixels = ((image_win->width) << (ppc - 1)) - 1; |
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|
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/* Writing the horizontal info into the registers */ |
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regw(horz_start & START_PX_HOR_MASK, SPH); |
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regw(horz_nr_pixels & NUM_PX_HOR_MASK, LNH); |
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vert_start = image_win->top; |
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if (frm_fmt == CCDC_FRMFMT_INTERLACED) { |
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vert_nr_lines = (image_win->height >> 1) - 1; |
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vert_start >>= 1; |
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/* To account for VD since line 0 doesn't have any data */ |
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vert_start += 1; |
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} else { |
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/* To account for VD since line 0 doesn't have any data */ |
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vert_start += 1; |
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vert_nr_lines = image_win->height - 1; |
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/* configure VDINT0 and VDINT1 */ |
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mid_img = vert_start + (image_win->height / 2); |
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regw(mid_img, VDINT1); |
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} |
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regw(0, VDINT0); |
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regw(vert_start & START_VER_ONE_MASK, SLV0); |
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regw(vert_start & START_VER_TWO_MASK, SLV1); |
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regw(vert_nr_lines & NUM_LINES_VER, LNV); |
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} |
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static void isif_config_bclamp(struct isif_black_clamp *bc) |
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{ |
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u32 val; |
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/* |
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* DC Offset is always added to image data irrespective of bc enable |
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* status |
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*/ |
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regw(bc->dc_offset, CLDCOFST); |
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if (bc->en) { |
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val = bc->bc_mode_color << ISIF_BC_MODE_COLOR_SHIFT; |
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|
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/* Enable BC and horizontal clamp calculation parameters */ |
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val = val | 1 | (bc->horz.mode << ISIF_HORZ_BC_MODE_SHIFT); |
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regw(val, CLAMPCFG); |
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if (bc->horz.mode != ISIF_HORZ_BC_DISABLE) { |
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/* |
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* Window count for calculation |
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* Base window selection |
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* pixel limit |
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* Horizontal size of window |
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* vertical size of the window |
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* Horizontal start position of the window |
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* Vertical start position of the window |
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*/ |
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val = bc->horz.win_count_calc | |
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((!!bc->horz.base_win_sel_calc) << |
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ISIF_HORZ_BC_WIN_SEL_SHIFT) | |
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((!!bc->horz.clamp_pix_limit) << |
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ISIF_HORZ_BC_PIX_LIMIT_SHIFT) | |
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(bc->horz.win_h_sz_calc << |
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ISIF_HORZ_BC_WIN_H_SIZE_SHIFT) | |
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(bc->horz.win_v_sz_calc << |
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ISIF_HORZ_BC_WIN_V_SIZE_SHIFT); |
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regw(val, CLHWIN0); |
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|
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regw(bc->horz.win_start_h_calc, CLHWIN1); |
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regw(bc->horz.win_start_v_calc, CLHWIN2); |
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} |
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|
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/* vertical clamp calculation parameters */ |
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|
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/* Reset clamp value sel for previous line */ |
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val |= |
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(bc->vert.reset_val_sel << ISIF_VERT_BC_RST_VAL_SEL_SHIFT) | |
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(bc->vert.line_ave_coef << ISIF_VERT_BC_LINE_AVE_COEF_SHIFT); |
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regw(val, CLVWIN0); |
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|
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/* Optical Black horizontal start position */ |
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regw(bc->vert.ob_start_h, CLVWIN1); |
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/* Optical Black vertical start position */ |
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regw(bc->vert.ob_start_v, CLVWIN2); |
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/* Optical Black vertical size for calculation */ |
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regw(bc->vert.ob_v_sz_calc, CLVWIN3); |
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/* Vertical start position for BC subtraction */ |
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regw(bc->vert_start_sub, CLSV); |
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} |
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} |
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|
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static void isif_config_linearization(struct isif_linearize *linearize) |
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{ |
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u32 val, i; |
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|
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if (!linearize->en) { |
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regw(0, LINCFG0); |
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return; |
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} |
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|
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/* shift value for correction & enable linearization (set lsb) */ |
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val = (linearize->corr_shft << ISIF_LIN_CORRSFT_SHIFT) | 1; |
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regw(val, LINCFG0); |
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|
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/* Scale factor */ |
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val = ((!!linearize->scale_fact.integer) << |
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ISIF_LIN_SCALE_FACT_INTEG_SHIFT) | |
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linearize->scale_fact.decimal; |
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regw(val, LINCFG1); |
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|
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for (i = 0; i < ISIF_LINEAR_TAB_SIZE; i++) { |
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if (i % 2) |
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regw_lin_tbl(linearize->table[i], ((i >> 1) << 2), 1); |
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else |
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regw_lin_tbl(linearize->table[i], ((i >> 1) << 2), 0); |
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} |
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} |
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|
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static int isif_config_dfc(struct isif_dfc *vdfc) |
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{ |
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/* initialize retries to loop for max ~ 250 usec */ |
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u32 val, count, retries = loops_per_jiffy / (4000/HZ); |
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int i; |
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|
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if (!vdfc->en) |
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return 0; |
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|
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/* Correction mode */ |
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val = (vdfc->corr_mode << ISIF_VDFC_CORR_MOD_SHIFT); |
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|
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/* Correct whole line or partial */ |
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if (vdfc->corr_whole_line) |
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val |= 1 << ISIF_VDFC_CORR_WHOLE_LN_SHIFT; |
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|
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/* level shift value */ |
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val |= vdfc->def_level_shift << ISIF_VDFC_LEVEL_SHFT_SHIFT; |
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|
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regw(val, DFCCTL); |
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|
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/* Defect saturation level */ |
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regw(vdfc->def_sat_level, VDFSATLV); |
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|
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regw(vdfc->table[0].pos_vert, DFCMEM0); |
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regw(vdfc->table[0].pos_horz, DFCMEM1); |
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if (vdfc->corr_mode == ISIF_VDFC_NORMAL || |
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vdfc->corr_mode == ISIF_VDFC_HORZ_INTERPOL_IF_SAT) { |
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regw(vdfc->table[0].level_at_pos, DFCMEM2); |
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regw(vdfc->table[0].level_up_pixels, DFCMEM3); |
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regw(vdfc->table[0].level_low_pixels, DFCMEM4); |
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} |
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|
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/* set DFCMARST and set DFCMWR */ |
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val = regr(DFCMEMCTL) | (1 << ISIF_DFCMEMCTL_DFCMARST_SHIFT) | 1; |
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regw(val, DFCMEMCTL); |
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|
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count = retries; |
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while (count && (regr(DFCMEMCTL) & 0x1)) |
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count--; |
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|
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if (!count) { |
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dev_dbg(isif_cfg.dev, "defect table write timeout !!!\n"); |
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return -1; |
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} |
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|
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for (i = 1; i < vdfc->num_vdefects; i++) { |
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regw(vdfc->table[i].pos_vert, DFCMEM0); |
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regw(vdfc->table[i].pos_horz, DFCMEM1); |
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if (vdfc->corr_mode == ISIF_VDFC_NORMAL || |
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vdfc->corr_mode == ISIF_VDFC_HORZ_INTERPOL_IF_SAT) { |
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regw(vdfc->table[i].level_at_pos, DFCMEM2); |
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regw(vdfc->table[i].level_up_pixels, DFCMEM3); |
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regw(vdfc->table[i].level_low_pixels, DFCMEM4); |
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} |
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val = regr(DFCMEMCTL); |
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/* clear DFCMARST and set DFCMWR */ |
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val &= ~BIT(ISIF_DFCMEMCTL_DFCMARST_SHIFT); |
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val |= 1; |
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regw(val, DFCMEMCTL); |
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|
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count = retries; |
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while (count && (regr(DFCMEMCTL) & 0x1)) |
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count--; |
|
|
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if (!count) { |
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dev_err(isif_cfg.dev, |
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"defect table write timeout !!!\n"); |
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return -1; |
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} |
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} |
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if (vdfc->num_vdefects < ISIF_VDFC_TABLE_SIZE) { |
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/* Extra cycle needed */ |
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regw(0, DFCMEM0); |
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regw(0x1FFF, DFCMEM1); |
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regw(1, DFCMEMCTL); |
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} |
|
|
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/* enable VDFC */ |
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reg_modify((1 << ISIF_VDFC_EN_SHIFT), (1 << ISIF_VDFC_EN_SHIFT), |
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DFCCTL); |
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return 0; |
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} |
|
|
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static void isif_config_csc(struct isif_df_csc *df_csc) |
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{ |
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u32 val1 = 0, val2 = 0, i; |
|
|
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if (!df_csc->csc.en) { |
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regw(0, CSCCTL); |
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return; |
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} |
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for (i = 0; i < ISIF_CSC_NUM_COEFF; i++) { |
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if ((i % 2) == 0) { |
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/* CSCM - LSB */ |
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val1 = (df_csc->csc.coeff[i].integer << |
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ISIF_CSC_COEF_INTEG_SHIFT) | |
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df_csc->csc.coeff[i].decimal; |
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} else { |
|
|
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/* CSCM - MSB */ |
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val2 = (df_csc->csc.coeff[i].integer << |
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ISIF_CSC_COEF_INTEG_SHIFT) | |
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df_csc->csc.coeff[i].decimal; |
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val2 <<= ISIF_CSCM_MSB_SHIFT; |
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val2 |= val1; |
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regw(val2, (CSCM0 + ((i - 1) << 1))); |
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} |
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} |
|
|
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/* program the active area */ |
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regw(df_csc->start_pix, FMTSPH); |
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/* |
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* one extra pixel as required for CSC. Actually number of |
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* pixel - 1 should be configured in this register. So we |
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* need to subtract 1 before writing to FMTSPH, but we will |
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* not do this since csc requires one extra pixel |
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*/ |
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regw(df_csc->num_pixels, FMTLNH); |
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regw(df_csc->start_line, FMTSLV); |
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/* |
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* one extra line as required for CSC. See reason documented for |
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* num_pixels |
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*/ |
|
regw(df_csc->num_lines, FMTLNV); |
|
|
|
/* Enable CSC */ |
|
regw(1, CSCCTL); |
|
} |
|
|
|
static int isif_config_raw(void) |
|
{ |
|
struct isif_params_raw *params = &isif_cfg.bayer; |
|
struct isif_config_params_raw *module_params = |
|
&isif_cfg.bayer.config_params; |
|
struct vpss_pg_frame_size frame_size; |
|
struct vpss_sync_pol sync; |
|
u32 val; |
|
|
|
dev_dbg(isif_cfg.dev, "\nStarting isif_config_raw..\n"); |
|
|
|
/* |
|
* Configure CCDCFG register:- |
|
* Set CCD Not to swap input since input is RAW data |
|
* Set FID detection function to Latch at V-Sync |
|
* Set WENLOG - isif valid area |
|
* Set TRGSEL |
|
* Set EXTRG |
|
* Packed to 8 or 16 bits |
|
*/ |
|
|
|
val = ISIF_YCINSWP_RAW | ISIF_CCDCFG_FIDMD_LATCH_VSYNC | |
|
ISIF_CCDCFG_WENLOG_AND | ISIF_CCDCFG_TRGSEL_WEN | |
|
ISIF_CCDCFG_EXTRG_DISABLE | isif_cfg.data_pack; |
|
|
|
dev_dbg(isif_cfg.dev, "Writing 0x%x to ...CCDCFG \n", val); |
|
regw(val, CCDCFG); |
|
|
|
/* |
|
* Configure the vertical sync polarity(MODESET.VDPOL) |
|
* Configure the horizontal sync polarity (MODESET.HDPOL) |
|
* Configure frame id polarity (MODESET.FLDPOL) |
|
* Configure data polarity |
|
* Configure External WEN Selection |
|
* Configure frame format(progressive or interlace) |
|
* Configure pixel format (Input mode) |
|
* Configure the data shift |
|
*/ |
|
|
|
val = ISIF_VDHDOUT_INPUT | (params->vd_pol << ISIF_VD_POL_SHIFT) | |
|
(params->hd_pol << ISIF_HD_POL_SHIFT) | |
|
(params->fid_pol << ISIF_FID_POL_SHIFT) | |
|
(ISIF_DATAPOL_NORMAL << ISIF_DATAPOL_SHIFT) | |
|
(ISIF_EXWEN_DISABLE << ISIF_EXWEN_SHIFT) | |
|
(params->frm_fmt << ISIF_FRM_FMT_SHIFT) | |
|
(params->pix_fmt << ISIF_INPUT_SHIFT) | |
|
(params->config_params.data_shift << ISIF_DATASFT_SHIFT); |
|
|
|
regw(val, MODESET); |
|
dev_dbg(isif_cfg.dev, "Writing 0x%x to MODESET...\n", val); |
|
|
|
/* |
|
* Configure GAMMAWD register |
|
* CFA pattern setting |
|
*/ |
|
val = params->cfa_pat << ISIF_GAMMAWD_CFA_SHIFT; |
|
|
|
/* Gamma msb */ |
|
if (module_params->compress.alg == ISIF_ALAW) |
|
val |= ISIF_ALAW_ENABLE; |
|
|
|
val |= (params->data_msb << ISIF_ALAW_GAMMA_WD_SHIFT); |
|
regw(val, CGAMMAWD); |
|
|
|
/* Configure DPCM compression settings */ |
|
if (module_params->compress.alg == ISIF_DPCM) { |
|
val = BIT(ISIF_DPCM_EN_SHIFT) | |
|
(module_params->compress.pred << |
|
ISIF_DPCM_PREDICTOR_SHIFT); |
|
} |
|
|
|
regw(val, MISC); |
|
|
|
/* Configure Gain & Offset */ |
|
isif_config_gain_offset(); |
|
|
|
/* Configure Color pattern */ |
|
val = (params->config_params.col_pat_field0.olop) | |
|
(params->config_params.col_pat_field0.olep << 2) | |
|
(params->config_params.col_pat_field0.elop << 4) | |
|
(params->config_params.col_pat_field0.elep << 6) | |
|
(params->config_params.col_pat_field1.olop << 8) | |
|
(params->config_params.col_pat_field1.olep << 10) | |
|
(params->config_params.col_pat_field1.elop << 12) | |
|
(params->config_params.col_pat_field1.elep << 14); |
|
regw(val, CCOLP); |
|
dev_dbg(isif_cfg.dev, "Writing %x to CCOLP ...\n", val); |
|
|
|
/* Configure HSIZE register */ |
|
val = (!!params->horz_flip_en) << ISIF_HSIZE_FLIP_SHIFT; |
|
|
|
/* calculate line offset in 32 bytes based on pack value */ |
|
if (isif_cfg.data_pack == ISIF_PACK_8BIT) |
|
val |= ((params->win.width + 31) >> 5); |
|
else if (isif_cfg.data_pack == ISIF_PACK_12BIT) |
|
val |= (((params->win.width + |
|
(params->win.width >> 2)) + 31) >> 5); |
|
else |
|
val |= (((params->win.width * 2) + 31) >> 5); |
|
regw(val, HSIZE); |
|
|
|
/* Configure SDOFST register */ |
|
if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) { |
|
if (params->image_invert_en) { |
|
/* For interlace inverse mode */ |
|
regw(0x4B6D, SDOFST); |
|
dev_dbg(isif_cfg.dev, "Writing 0x4B6D to SDOFST...\n"); |
|
} else { |
|
/* For interlace non inverse mode */ |
|
regw(0x0B6D, SDOFST); |
|
dev_dbg(isif_cfg.dev, "Writing 0x0B6D to SDOFST...\n"); |
|
} |
|
} else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) { |
|
if (params->image_invert_en) { |
|
/* For progressive inverse mode */ |
|
regw(0x4000, SDOFST); |
|
dev_dbg(isif_cfg.dev, "Writing 0x4000 to SDOFST...\n"); |
|
} else { |
|
/* For progressive non inverse mode */ |
|
regw(0x0000, SDOFST); |
|
dev_dbg(isif_cfg.dev, "Writing 0x0000 to SDOFST...\n"); |
|
} |
|
} |
|
|
|
/* Configure video window */ |
|
isif_setwin(¶ms->win, params->frm_fmt, 1); |
|
|
|
/* Configure Black Clamp */ |
|
isif_config_bclamp(&module_params->bclamp); |
|
|
|
/* Configure Vertical Defection Pixel Correction */ |
|
if (isif_config_dfc(&module_params->dfc) < 0) |
|
return -EFAULT; |
|
|
|
if (!module_params->df_csc.df_or_csc) |
|
/* Configure Color Space Conversion */ |
|
isif_config_csc(&module_params->df_csc); |
|
|
|
isif_config_linearization(&module_params->linearize); |
|
|
|
/* Configure Culling */ |
|
isif_config_culling(&module_params->culling); |
|
|
|
/* Configure horizontal and vertical offsets(DFC,LSC,Gain) */ |
|
regw(module_params->horz_offset, DATAHOFST); |
|
regw(module_params->vert_offset, DATAVOFST); |
|
|
|
/* Setup test pattern if enabled */ |
|
if (params->config_params.test_pat_gen) { |
|
/* Use the HD/VD pol settings from user */ |
|
sync.ccdpg_hdpol = params->hd_pol; |
|
sync.ccdpg_vdpol = params->vd_pol; |
|
dm365_vpss_set_sync_pol(sync); |
|
frame_size.hlpfr = isif_cfg.bayer.win.width; |
|
frame_size.pplen = isif_cfg.bayer.win.height; |
|
dm365_vpss_set_pg_frame_size(frame_size); |
|
vpss_select_ccdc_source(VPSS_PGLPBK); |
|
} |
|
|
|
dev_dbg(isif_cfg.dev, "\nEnd of isif_config_ycbcr...\n"); |
|
return 0; |
|
} |
|
|
|
static int isif_set_buftype(enum ccdc_buftype buf_type) |
|
{ |
|
if (isif_cfg.if_type == VPFE_RAW_BAYER) |
|
isif_cfg.bayer.buf_type = buf_type; |
|
else |
|
isif_cfg.ycbcr.buf_type = buf_type; |
|
|
|
return 0; |
|
|
|
} |
|
static enum ccdc_buftype isif_get_buftype(void) |
|
{ |
|
if (isif_cfg.if_type == VPFE_RAW_BAYER) |
|
return isif_cfg.bayer.buf_type; |
|
|
|
return isif_cfg.ycbcr.buf_type; |
|
} |
|
|
|
static int isif_enum_pix(u32 *pix, int i) |
|
{ |
|
int ret = -EINVAL; |
|
|
|
if (isif_cfg.if_type == VPFE_RAW_BAYER) { |
|
if (i < ARRAY_SIZE(isif_raw_bayer_pix_formats)) { |
|
*pix = isif_raw_bayer_pix_formats[i]; |
|
ret = 0; |
|
} |
|
} else { |
|
if (i < ARRAY_SIZE(isif_raw_yuv_pix_formats)) { |
|
*pix = isif_raw_yuv_pix_formats[i]; |
|
ret = 0; |
|
} |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static int isif_set_pixel_format(unsigned int pixfmt) |
|
{ |
|
if (isif_cfg.if_type == VPFE_RAW_BAYER) { |
|
if (pixfmt == V4L2_PIX_FMT_SBGGR8) { |
|
if ((isif_cfg.bayer.config_params.compress.alg != |
|
ISIF_ALAW) && |
|
(isif_cfg.bayer.config_params.compress.alg != |
|
ISIF_DPCM)) { |
|
dev_dbg(isif_cfg.dev, |
|
"Either configure A-Law or DPCM\n"); |
|
return -EINVAL; |
|
} |
|
isif_cfg.data_pack = ISIF_PACK_8BIT; |
|
} else if (pixfmt == V4L2_PIX_FMT_SBGGR16) { |
|
isif_cfg.bayer.config_params.compress.alg = |
|
ISIF_NO_COMPRESSION; |
|
isif_cfg.data_pack = ISIF_PACK_16BIT; |
|
} else |
|
return -EINVAL; |
|
isif_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW; |
|
} else { |
|
if (pixfmt == V4L2_PIX_FMT_YUYV) |
|
isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR; |
|
else if (pixfmt == V4L2_PIX_FMT_UYVY) |
|
isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY; |
|
else |
|
return -EINVAL; |
|
isif_cfg.data_pack = ISIF_PACK_8BIT; |
|
} |
|
return 0; |
|
} |
|
|
|
static u32 isif_get_pixel_format(void) |
|
{ |
|
u32 pixfmt; |
|
|
|
if (isif_cfg.if_type == VPFE_RAW_BAYER) |
|
if (isif_cfg.bayer.config_params.compress.alg == ISIF_ALAW || |
|
isif_cfg.bayer.config_params.compress.alg == ISIF_DPCM) |
|
pixfmt = V4L2_PIX_FMT_SBGGR8; |
|
else |
|
pixfmt = V4L2_PIX_FMT_SBGGR16; |
|
else { |
|
if (isif_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR) |
|
pixfmt = V4L2_PIX_FMT_YUYV; |
|
else |
|
pixfmt = V4L2_PIX_FMT_UYVY; |
|
} |
|
return pixfmt; |
|
} |
|
|
|
static int isif_set_image_window(struct v4l2_rect *win) |
|
{ |
|
if (isif_cfg.if_type == VPFE_RAW_BAYER) { |
|
isif_cfg.bayer.win.top = win->top; |
|
isif_cfg.bayer.win.left = win->left; |
|
isif_cfg.bayer.win.width = win->width; |
|
isif_cfg.bayer.win.height = win->height; |
|
} else { |
|
isif_cfg.ycbcr.win.top = win->top; |
|
isif_cfg.ycbcr.win.left = win->left; |
|
isif_cfg.ycbcr.win.width = win->width; |
|
isif_cfg.ycbcr.win.height = win->height; |
|
} |
|
return 0; |
|
} |
|
|
|
static void isif_get_image_window(struct v4l2_rect *win) |
|
{ |
|
if (isif_cfg.if_type == VPFE_RAW_BAYER) |
|
*win = isif_cfg.bayer.win; |
|
else |
|
*win = isif_cfg.ycbcr.win; |
|
} |
|
|
|
static unsigned int isif_get_line_length(void) |
|
{ |
|
unsigned int len; |
|
|
|
if (isif_cfg.if_type == VPFE_RAW_BAYER) { |
|
if (isif_cfg.data_pack == ISIF_PACK_8BIT) |
|
len = ((isif_cfg.bayer.win.width)); |
|
else if (isif_cfg.data_pack == ISIF_PACK_12BIT) |
|
len = (((isif_cfg.bayer.win.width * 2) + |
|
(isif_cfg.bayer.win.width >> 2))); |
|
else |
|
len = (((isif_cfg.bayer.win.width * 2))); |
|
} else |
|
len = (((isif_cfg.ycbcr.win.width * 2))); |
|
return ALIGN(len, 32); |
|
} |
|
|
|
static int isif_set_frame_format(enum ccdc_frmfmt frm_fmt) |
|
{ |
|
if (isif_cfg.if_type == VPFE_RAW_BAYER) |
|
isif_cfg.bayer.frm_fmt = frm_fmt; |
|
else |
|
isif_cfg.ycbcr.frm_fmt = frm_fmt; |
|
return 0; |
|
} |
|
static enum ccdc_frmfmt isif_get_frame_format(void) |
|
{ |
|
if (isif_cfg.if_type == VPFE_RAW_BAYER) |
|
return isif_cfg.bayer.frm_fmt; |
|
return isif_cfg.ycbcr.frm_fmt; |
|
} |
|
|
|
static int isif_getfid(void) |
|
{ |
|
return (regr(MODESET) >> 15) & 0x1; |
|
} |
|
|
|
/* misc operations */ |
|
static void isif_setfbaddr(unsigned long addr) |
|
{ |
|
regw((addr >> 21) & 0x07ff, CADU); |
|
regw((addr >> 5) & 0x0ffff, CADL); |
|
} |
|
|
|
static int isif_set_hw_if_params(struct vpfe_hw_if_param *params) |
|
{ |
|
isif_cfg.if_type = params->if_type; |
|
|
|
switch (params->if_type) { |
|
case VPFE_BT656: |
|
case VPFE_BT656_10BIT: |
|
case VPFE_YCBCR_SYNC_8: |
|
isif_cfg.ycbcr.pix_fmt = CCDC_PIXFMT_YCBCR_8BIT; |
|
isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY; |
|
break; |
|
case VPFE_BT1120: |
|
case VPFE_YCBCR_SYNC_16: |
|
isif_cfg.ycbcr.pix_fmt = CCDC_PIXFMT_YCBCR_16BIT; |
|
isif_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY; |
|
break; |
|
case VPFE_RAW_BAYER: |
|
isif_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW; |
|
break; |
|
default: |
|
dev_dbg(isif_cfg.dev, "Invalid interface type\n"); |
|
return -EINVAL; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/* This function will configure ISIF for YCbCr parameters. */ |
|
static int isif_config_ycbcr(void) |
|
{ |
|
struct isif_ycbcr_config *params = &isif_cfg.ycbcr; |
|
u32 modeset = 0, ccdcfg = 0; |
|
|
|
dev_dbg(isif_cfg.dev, "\nStarting isif_config_ycbcr..."); |
|
|
|
/* configure pixel format or input mode */ |
|
modeset = modeset | (params->pix_fmt << ISIF_INPUT_SHIFT) | |
|
(params->frm_fmt << ISIF_FRM_FMT_SHIFT) | |
|
(params->fid_pol << ISIF_FID_POL_SHIFT) | |
|
(params->hd_pol << ISIF_HD_POL_SHIFT) | |
|
(params->vd_pol << ISIF_VD_POL_SHIFT); |
|
|
|
/* pack the data to 8-bit ISIFCFG */ |
|
switch (isif_cfg.if_type) { |
|
case VPFE_BT656: |
|
if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) { |
|
dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n"); |
|
return -EINVAL; |
|
} |
|
modeset |= (VPFE_PINPOL_NEGATIVE << ISIF_VD_POL_SHIFT); |
|
regw(3, REC656IF); |
|
ccdcfg = ccdcfg | ISIF_DATA_PACK8 | ISIF_YCINSWP_YCBCR; |
|
break; |
|
case VPFE_BT656_10BIT: |
|
if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) { |
|
dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n"); |
|
return -EINVAL; |
|
} |
|
/* setup BT.656, embedded sync */ |
|
regw(3, REC656IF); |
|
/* enable 10 bit mode in ccdcfg */ |
|
ccdcfg = ccdcfg | ISIF_DATA_PACK8 | ISIF_YCINSWP_YCBCR | |
|
ISIF_BW656_ENABLE; |
|
break; |
|
case VPFE_BT1120: |
|
if (params->pix_fmt != CCDC_PIXFMT_YCBCR_16BIT) { |
|
dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n"); |
|
return -EINVAL; |
|
} |
|
regw(3, REC656IF); |
|
break; |
|
|
|
case VPFE_YCBCR_SYNC_8: |
|
ccdcfg |= ISIF_DATA_PACK8; |
|
ccdcfg |= ISIF_YCINSWP_YCBCR; |
|
if (params->pix_fmt != CCDC_PIXFMT_YCBCR_8BIT) { |
|
dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n"); |
|
return -EINVAL; |
|
} |
|
break; |
|
case VPFE_YCBCR_SYNC_16: |
|
if (params->pix_fmt != CCDC_PIXFMT_YCBCR_16BIT) { |
|
dev_dbg(isif_cfg.dev, "Invalid pix_fmt(input mode)\n"); |
|
return -EINVAL; |
|
} |
|
break; |
|
default: |
|
/* should never come here */ |
|
dev_dbg(isif_cfg.dev, "Invalid interface type\n"); |
|
return -EINVAL; |
|
} |
|
|
|
regw(modeset, MODESET); |
|
|
|
/* Set up pix order */ |
|
ccdcfg |= params->pix_order << ISIF_PIX_ORDER_SHIFT; |
|
|
|
regw(ccdcfg, CCDCFG); |
|
|
|
/* configure video window */ |
|
if ((isif_cfg.if_type == VPFE_BT1120) || |
|
(isif_cfg.if_type == VPFE_YCBCR_SYNC_16)) |
|
isif_setwin(¶ms->win, params->frm_fmt, 1); |
|
else |
|
isif_setwin(¶ms->win, params->frm_fmt, 2); |
|
|
|
/* |
|
* configure the horizontal line offset |
|
* this is done by rounding up width to a multiple of 16 pixels |
|
* and multiply by two to account for y:cb:cr 4:2:2 data |
|
*/ |
|
regw(((((params->win.width * 2) + 31) & 0xffffffe0) >> 5), HSIZE); |
|
|
|
/* configure the memory line offset */ |
|
if ((params->frm_fmt == CCDC_FRMFMT_INTERLACED) && |
|
(params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED)) |
|
/* two fields are interleaved in memory */ |
|
regw(0x00000249, SDOFST); |
|
|
|
return 0; |
|
} |
|
|
|
static int isif_configure(void) |
|
{ |
|
if (isif_cfg.if_type == VPFE_RAW_BAYER) |
|
return isif_config_raw(); |
|
return isif_config_ycbcr(); |
|
} |
|
|
|
static int isif_close(struct device *device) |
|
{ |
|
/* copy defaults to module params */ |
|
isif_cfg.bayer.config_params = isif_config_defaults; |
|
return 0; |
|
} |
|
|
|
static const struct ccdc_hw_device isif_hw_dev = { |
|
.name = "ISIF", |
|
.owner = THIS_MODULE, |
|
.hw_ops = { |
|
.open = isif_open, |
|
.close = isif_close, |
|
.enable = isif_enable, |
|
.enable_out_to_sdram = isif_enable_output_to_sdram, |
|
.set_hw_if_params = isif_set_hw_if_params, |
|
.configure = isif_configure, |
|
.set_buftype = isif_set_buftype, |
|
.get_buftype = isif_get_buftype, |
|
.enum_pix = isif_enum_pix, |
|
.set_pixel_format = isif_set_pixel_format, |
|
.get_pixel_format = isif_get_pixel_format, |
|
.set_frame_format = isif_set_frame_format, |
|
.get_frame_format = isif_get_frame_format, |
|
.set_image_window = isif_set_image_window, |
|
.get_image_window = isif_get_image_window, |
|
.get_line_length = isif_get_line_length, |
|
.setfbaddr = isif_setfbaddr, |
|
.getfid = isif_getfid, |
|
}, |
|
}; |
|
|
|
static int isif_probe(struct platform_device *pdev) |
|
{ |
|
void (*setup_pinmux)(void); |
|
struct resource *res; |
|
void __iomem *addr; |
|
int status = 0, i; |
|
|
|
/* Platform data holds setup_pinmux function ptr */ |
|
if (!pdev->dev.platform_data) |
|
return -ENODEV; |
|
|
|
/* |
|
* first try to register with vpfe. If not correct platform, then we |
|
* don't have to iomap |
|
*/ |
|
status = vpfe_register_ccdc_device(&isif_hw_dev); |
|
if (status < 0) |
|
return status; |
|
|
|
setup_pinmux = pdev->dev.platform_data; |
|
/* |
|
* setup Mux configuration for ccdc which may be different for |
|
* different SoCs using this CCDC |
|
*/ |
|
setup_pinmux(); |
|
|
|
i = 0; |
|
/* Get the ISIF base address, linearization table0 and table1 addr. */ |
|
while (i < 3) { |
|
res = platform_get_resource(pdev, IORESOURCE_MEM, i); |
|
if (!res) { |
|
status = -ENODEV; |
|
goto fail_nobase_res; |
|
} |
|
res = request_mem_region(res->start, resource_size(res), |
|
res->name); |
|
if (!res) { |
|
status = -EBUSY; |
|
goto fail_nobase_res; |
|
} |
|
addr = ioremap(res->start, resource_size(res)); |
|
if (!addr) { |
|
status = -ENOMEM; |
|
goto fail_base_iomap; |
|
} |
|
switch (i) { |
|
case 0: |
|
/* ISIF base address */ |
|
isif_cfg.base_addr = addr; |
|
break; |
|
case 1: |
|
/* ISIF linear tbl0 address */ |
|
isif_cfg.linear_tbl0_addr = addr; |
|
break; |
|
default: |
|
/* ISIF linear tbl0 address */ |
|
isif_cfg.linear_tbl1_addr = addr; |
|
break; |
|
} |
|
i++; |
|
} |
|
isif_cfg.dev = &pdev->dev; |
|
|
|
printk(KERN_NOTICE "%s is registered with vpfe.\n", |
|
isif_hw_dev.name); |
|
return 0; |
|
fail_base_iomap: |
|
release_mem_region(res->start, resource_size(res)); |
|
i--; |
|
fail_nobase_res: |
|
if (isif_cfg.base_addr) { |
|
iounmap(isif_cfg.base_addr); |
|
isif_cfg.base_addr = NULL; |
|
} |
|
if (isif_cfg.linear_tbl0_addr) { |
|
iounmap(isif_cfg.linear_tbl0_addr); |
|
isif_cfg.linear_tbl0_addr = NULL; |
|
} |
|
|
|
while (i >= 0) { |
|
res = platform_get_resource(pdev, IORESOURCE_MEM, i); |
|
if (res) |
|
release_mem_region(res->start, resource_size(res)); |
|
i--; |
|
} |
|
vpfe_unregister_ccdc_device(&isif_hw_dev); |
|
return status; |
|
} |
|
|
|
static int isif_remove(struct platform_device *pdev) |
|
{ |
|
struct resource *res; |
|
int i = 0; |
|
|
|
iounmap(isif_cfg.base_addr); |
|
isif_cfg.base_addr = NULL; |
|
iounmap(isif_cfg.linear_tbl0_addr); |
|
isif_cfg.linear_tbl0_addr = NULL; |
|
iounmap(isif_cfg.linear_tbl1_addr); |
|
isif_cfg.linear_tbl1_addr = NULL; |
|
while (i < 3) { |
|
res = platform_get_resource(pdev, IORESOURCE_MEM, i); |
|
if (res) |
|
release_mem_region(res->start, resource_size(res)); |
|
i++; |
|
} |
|
vpfe_unregister_ccdc_device(&isif_hw_dev); |
|
return 0; |
|
} |
|
|
|
static struct platform_driver isif_driver = { |
|
.driver = { |
|
.name = "isif", |
|
}, |
|
.remove = isif_remove, |
|
.probe = isif_probe, |
|
}; |
|
|
|
module_platform_driver(isif_driver); |
|
|
|
MODULE_LICENSE("GPL");
|
|
|