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630 lines
17 KiB
630 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Microchip eXtended Image Sensor Controller (XISC) driver |
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* |
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* Copyright (C) 2019-2021 Microchip Technology, Inc. and its subsidiaries |
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* |
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* Author: Eugen Hristev <[email protected]> |
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* |
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* Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS |
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* |
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* ISC video pipeline integrates the following submodules: |
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* PFE: Parallel Front End to sample the camera sensor input stream |
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* DPC: Defective Pixel Correction with black offset correction, green disparity |
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* correction and defective pixel correction (3 modules total) |
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* WB: Programmable white balance in the Bayer domain |
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* CFA: Color filter array interpolation module |
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* CC: Programmable color correction |
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* GAM: Gamma correction |
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*VHXS: Vertical and Horizontal Scaler |
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* CSC: Programmable color space conversion |
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*CBHS: Contrast Brightness Hue and Saturation control |
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* SUB: This module performs YCbCr444 to YCbCr420 chrominance subsampling |
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* RLP: This module performs rounding, range limiting |
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* and packing of the incoming data |
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* DMA: This module performs DMA master accesses to write frames to external RAM |
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* HIS: Histogram module performs statistic counters on the frames |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clkdev.h> |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/math64.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_graph.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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#include <linux/videodev2.h> |
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#include <media/v4l2-ctrls.h> |
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#include <media/v4l2-device.h> |
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#include <media/v4l2-event.h> |
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#include <media/v4l2-image-sizes.h> |
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#include <media/v4l2-ioctl.h> |
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#include <media/v4l2-fwnode.h> |
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#include <media/v4l2-subdev.h> |
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#include <media/videobuf2-dma-contig.h> |
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#include "atmel-isc-regs.h" |
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#include "atmel-isc.h" |
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#define ISC_SAMA7G5_MAX_SUPPORT_WIDTH 3264 |
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#define ISC_SAMA7G5_MAX_SUPPORT_HEIGHT 2464 |
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#define ISC_SAMA7G5_PIPELINE \ |
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(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ |
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CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) |
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/* This is a list of the formats that the ISC can *output* */ |
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static const struct isc_format sama7g5_controller_formats[] = { |
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{ |
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.fourcc = V4L2_PIX_FMT_ARGB444, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_ARGB555, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_RGB565, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_ABGR32, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_XBGR32, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_YUV420, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_UYVY, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_VYUY, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_YUYV, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_YUV422P, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_GREY, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_Y10, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_Y16, |
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}, |
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}; |
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/* This is a list of formats that the ISC can receive as *input* */ |
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static struct isc_format sama7g5_formats_list[] = { |
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{ |
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.fourcc = V4L2_PIX_FMT_SBGGR8, |
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.mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, |
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.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, |
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.cfa_baycfg = ISC_BAY_CFG_BGBG, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_SGBRG8, |
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.mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, |
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.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, |
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.cfa_baycfg = ISC_BAY_CFG_GBGB, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_SGRBG8, |
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.mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, |
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.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, |
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.cfa_baycfg = ISC_BAY_CFG_GRGR, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_SRGGB8, |
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.mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, |
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.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, |
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.cfa_baycfg = ISC_BAY_CFG_RGRG, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_SBGGR10, |
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.mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, |
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, |
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.cfa_baycfg = ISC_BAY_CFG_RGRG, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_SGBRG10, |
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.mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, |
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, |
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.cfa_baycfg = ISC_BAY_CFG_GBGB, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_SGRBG10, |
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.mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, |
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, |
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.cfa_baycfg = ISC_BAY_CFG_GRGR, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_SRGGB10, |
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.mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, |
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, |
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.cfa_baycfg = ISC_BAY_CFG_RGRG, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_SBGGR12, |
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.mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, |
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, |
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.cfa_baycfg = ISC_BAY_CFG_BGBG, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_SGBRG12, |
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.mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, |
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, |
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.cfa_baycfg = ISC_BAY_CFG_GBGB, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_SGRBG12, |
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.mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, |
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, |
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.cfa_baycfg = ISC_BAY_CFG_GRGR, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_SRGGB12, |
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.mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, |
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, |
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.cfa_baycfg = ISC_BAY_CFG_RGRG, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_GREY, |
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.mbus_code = MEDIA_BUS_FMT_Y8_1X8, |
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.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_YUYV, |
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.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, |
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.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_UYVY, |
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.mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, |
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.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_RGB565, |
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.mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, |
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.pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, |
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}, |
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{ |
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.fourcc = V4L2_PIX_FMT_Y10, |
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.mbus_code = MEDIA_BUS_FMT_Y10_1X10, |
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.pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, |
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}, |
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}; |
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static void isc_sama7g5_config_csc(struct isc_device *isc) |
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{ |
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struct regmap *regmap = isc->regmap; |
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/* Convert RGB to YUV */ |
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regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, |
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0x42 | (0x81 << 16)); |
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regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, |
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0x19 | (0x10 << 16)); |
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regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, |
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0xFDA | (0xFB6 << 16)); |
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regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, |
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0x70 | (0x80 << 16)); |
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regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, |
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0x70 | (0xFA2 << 16)); |
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regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, |
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0xFEE | (0x80 << 16)); |
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} |
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static void isc_sama7g5_config_cbc(struct isc_device *isc) |
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{ |
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struct regmap *regmap = isc->regmap; |
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/* Configure what is set via v4l2 ctrls */ |
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regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.brightness); |
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regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.contrast); |
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/* Configure Hue and Saturation as neutral midpoint */ |
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regmap_write(regmap, ISC_CBCHS_HUE, 0); |
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regmap_write(regmap, ISC_CBCHS_SAT, (1 << 4)); |
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} |
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static void isc_sama7g5_config_cc(struct isc_device *isc) |
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{ |
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struct regmap *regmap = isc->regmap; |
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/* Configure each register at the neutral fixed point 1.0 or 0.0 */ |
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regmap_write(regmap, ISC_CC_RR_RG, (1 << 8)); |
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regmap_write(regmap, ISC_CC_RB_OR, 0); |
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regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16); |
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regmap_write(regmap, ISC_CC_GB_OG, 0); |
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regmap_write(regmap, ISC_CC_BR_BG, 0); |
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regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); |
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} |
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static void isc_sama7g5_config_ctrls(struct isc_device *isc, |
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const struct v4l2_ctrl_ops *ops) |
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{ |
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struct isc_ctrls *ctrls = &isc->ctrls; |
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struct v4l2_ctrl_handler *hdl = &ctrls->handler; |
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ctrls->contrast = 16; |
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v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 16); |
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} |
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static void isc_sama7g5_config_dpc(struct isc_device *isc) |
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{ |
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u32 bay_cfg = isc->config.sd_format->cfa_baycfg; |
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struct regmap *regmap = isc->regmap; |
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regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BLOFF_MASK, |
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(64 << ISC_DPC_CFG_BLOFF_SHIFT)); |
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regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BAYCFG_MASK, |
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(bay_cfg << ISC_DPC_CFG_BAYCFG_SHIFT)); |
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} |
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static void isc_sama7g5_config_gam(struct isc_device *isc) |
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{ |
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struct regmap *regmap = isc->regmap; |
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regmap_update_bits(regmap, ISC_GAM_CTRL, ISC_GAM_CTRL_BIPART, |
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ISC_GAM_CTRL_BIPART); |
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} |
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static void isc_sama7g5_config_rlp(struct isc_device *isc) |
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{ |
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struct regmap *regmap = isc->regmap; |
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u32 rlp_mode = isc->config.rlp_cfg_mode; |
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regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, |
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ISC_RLP_CFG_MODE_MASK | ISC_RLP_CFG_LSH | |
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ISC_RLP_CFG_YMODE_MASK, rlp_mode); |
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} |
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static void isc_sama7g5_adapt_pipeline(struct isc_device *isc) |
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{ |
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isc->try_config.bits_pipeline &= ISC_SAMA7G5_PIPELINE; |
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} |
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/* Gamma table with gamma 1/2.2 */ |
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static const u32 isc_sama7g5_gamma_table[][GAMMA_ENTRIES] = { |
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/* index 0 --> gamma bipartite */ |
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{ |
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0x980, 0x4c0320, 0x650260, 0x7801e0, 0x8701a0, 0x940180, |
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0xa00160, 0xab0120, 0xb40120, 0xbd0120, 0xc60100, 0xce0100, |
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0xd600e0, 0xdd00e0, 0xe400e0, 0xeb00c0, 0xf100c0, 0xf700c0, |
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0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0, |
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0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080, |
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0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a, |
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0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030, |
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0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026, |
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0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020, |
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0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c, |
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0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a }, |
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}; |
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static int xisc_parse_dt(struct device *dev, struct isc_device *isc) |
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{ |
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struct device_node *np = dev->of_node; |
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struct device_node *epn = NULL; |
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struct isc_subdev_entity *subdev_entity; |
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unsigned int flags; |
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int ret; |
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bool mipi_mode; |
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INIT_LIST_HEAD(&isc->subdev_entities); |
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mipi_mode = of_property_read_bool(np, "microchip,mipi-mode"); |
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while (1) { |
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struct v4l2_fwnode_endpoint v4l2_epn = { .bus_type = 0 }; |
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epn = of_graph_get_next_endpoint(np, epn); |
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if (!epn) |
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return 0; |
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ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn), |
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&v4l2_epn); |
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if (ret) { |
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ret = -EINVAL; |
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dev_err(dev, "Could not parse the endpoint\n"); |
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break; |
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} |
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subdev_entity = devm_kzalloc(dev, sizeof(*subdev_entity), |
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GFP_KERNEL); |
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if (!subdev_entity) { |
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ret = -ENOMEM; |
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break; |
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} |
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subdev_entity->epn = epn; |
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flags = v4l2_epn.bus.parallel.flags; |
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if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) |
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subdev_entity->pfe_cfg0 = ISC_PFE_CFG0_HPOL_LOW; |
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if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) |
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subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_VPOL_LOW; |
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if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) |
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subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW; |
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if (v4l2_epn.bus_type == V4L2_MBUS_BT656) |
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subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC | |
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ISC_PFE_CFG0_CCIR656; |
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if (mipi_mode) |
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subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_MIPI; |
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list_add_tail(&subdev_entity->list, &isc->subdev_entities); |
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} |
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of_node_put(epn); |
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return ret; |
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} |
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static int microchip_xisc_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct isc_device *isc; |
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struct resource *res; |
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void __iomem *io_base; |
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struct isc_subdev_entity *subdev_entity; |
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int irq; |
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int ret; |
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u32 ver; |
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isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL); |
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if (!isc) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, isc); |
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isc->dev = dev; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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io_base = devm_ioremap_resource(dev, res); |
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if (IS_ERR(io_base)) |
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return PTR_ERR(io_base); |
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isc->regmap = devm_regmap_init_mmio(dev, io_base, &isc_regmap_config); |
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if (IS_ERR(isc->regmap)) { |
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ret = PTR_ERR(isc->regmap); |
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dev_err(dev, "failed to init register map: %d\n", ret); |
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return ret; |
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} |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) |
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return irq; |
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ret = devm_request_irq(dev, irq, isc_interrupt, 0, |
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"microchip-sama7g5-xisc", isc); |
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if (ret < 0) { |
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dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", |
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irq, ret); |
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return ret; |
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} |
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isc->gamma_table = isc_sama7g5_gamma_table; |
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isc->gamma_max = 0; |
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isc->max_width = ISC_SAMA7G5_MAX_SUPPORT_WIDTH; |
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isc->max_height = ISC_SAMA7G5_MAX_SUPPORT_HEIGHT; |
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isc->config_dpc = isc_sama7g5_config_dpc; |
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isc->config_csc = isc_sama7g5_config_csc; |
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isc->config_cbc = isc_sama7g5_config_cbc; |
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isc->config_cc = isc_sama7g5_config_cc; |
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isc->config_gam = isc_sama7g5_config_gam; |
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isc->config_rlp = isc_sama7g5_config_rlp; |
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isc->config_ctrls = isc_sama7g5_config_ctrls; |
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isc->adapt_pipeline = isc_sama7g5_adapt_pipeline; |
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|
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isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; |
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isc->offsets.cbc = ISC_SAMA7G5_CBC_OFFSET; |
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isc->offsets.sub422 = ISC_SAMA7G5_SUB422_OFFSET; |
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isc->offsets.sub420 = ISC_SAMA7G5_SUB420_OFFSET; |
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isc->offsets.rlp = ISC_SAMA7G5_RLP_OFFSET; |
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isc->offsets.his = ISC_SAMA7G5_HIS_OFFSET; |
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isc->offsets.dma = ISC_SAMA7G5_DMA_OFFSET; |
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isc->offsets.version = ISC_SAMA7G5_VERSION_OFFSET; |
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isc->offsets.his_entry = ISC_SAMA7G5_HIS_ENTRY_OFFSET; |
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|
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isc->controller_formats = sama7g5_controller_formats; |
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isc->controller_formats_size = ARRAY_SIZE(sama7g5_controller_formats); |
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isc->formats_list = sama7g5_formats_list; |
|
isc->formats_list_size = ARRAY_SIZE(sama7g5_formats_list); |
|
|
|
/* sama7g5-isc RAM access port is full AXI4 - 32 bits per beat */ |
|
isc->dcfg = ISC_DCFG_YMBSIZE_BEATS32 | ISC_DCFG_CMBSIZE_BEATS32; |
|
|
|
ret = isc_pipeline_init(isc); |
|
if (ret) |
|
return ret; |
|
|
|
isc->hclock = devm_clk_get(dev, "hclock"); |
|
if (IS_ERR(isc->hclock)) { |
|
ret = PTR_ERR(isc->hclock); |
|
dev_err(dev, "failed to get hclock: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
ret = clk_prepare_enable(isc->hclock); |
|
if (ret) { |
|
dev_err(dev, "failed to enable hclock: %d\n", ret); |
|
return ret; |
|
} |
|
|
|
ret = isc_clk_init(isc); |
|
if (ret) { |
|
dev_err(dev, "failed to init isc clock: %d\n", ret); |
|
goto unprepare_hclk; |
|
} |
|
|
|
isc->ispck = isc->isc_clks[ISC_ISPCK].clk; |
|
|
|
ret = clk_prepare_enable(isc->ispck); |
|
if (ret) { |
|
dev_err(dev, "failed to enable ispck: %d\n", ret); |
|
goto unprepare_hclk; |
|
} |
|
|
|
/* ispck should be greater or equal to hclock */ |
|
ret = clk_set_rate(isc->ispck, clk_get_rate(isc->hclock)); |
|
if (ret) { |
|
dev_err(dev, "failed to set ispck rate: %d\n", ret); |
|
goto unprepare_clk; |
|
} |
|
|
|
ret = v4l2_device_register(dev, &isc->v4l2_dev); |
|
if (ret) { |
|
dev_err(dev, "unable to register v4l2 device.\n"); |
|
goto unprepare_clk; |
|
} |
|
|
|
ret = xisc_parse_dt(dev, isc); |
|
if (ret) { |
|
dev_err(dev, "fail to parse device tree\n"); |
|
goto unregister_v4l2_device; |
|
} |
|
|
|
if (list_empty(&isc->subdev_entities)) { |
|
dev_err(dev, "no subdev found\n"); |
|
ret = -ENODEV; |
|
goto unregister_v4l2_device; |
|
} |
|
|
|
list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { |
|
struct v4l2_async_subdev *asd; |
|
|
|
v4l2_async_notifier_init(&subdev_entity->notifier); |
|
|
|
asd = v4l2_async_notifier_add_fwnode_remote_subdev( |
|
&subdev_entity->notifier, |
|
of_fwnode_handle(subdev_entity->epn), |
|
struct v4l2_async_subdev); |
|
|
|
of_node_put(subdev_entity->epn); |
|
subdev_entity->epn = NULL; |
|
|
|
if (IS_ERR(asd)) { |
|
ret = PTR_ERR(asd); |
|
goto cleanup_subdev; |
|
} |
|
|
|
subdev_entity->notifier.ops = &isc_async_ops; |
|
|
|
ret = v4l2_async_notifier_register(&isc->v4l2_dev, |
|
&subdev_entity->notifier); |
|
if (ret) { |
|
dev_err(dev, "fail to register async notifier\n"); |
|
goto cleanup_subdev; |
|
} |
|
|
|
if (video_is_registered(&isc->video_dev)) |
|
break; |
|
} |
|
|
|
pm_runtime_set_active(dev); |
|
pm_runtime_enable(dev); |
|
pm_request_idle(dev); |
|
|
|
regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); |
|
dev_info(dev, "Microchip XISC version %x\n", ver); |
|
|
|
return 0; |
|
|
|
cleanup_subdev: |
|
isc_subdev_cleanup(isc); |
|
|
|
unregister_v4l2_device: |
|
v4l2_device_unregister(&isc->v4l2_dev); |
|
|
|
unprepare_clk: |
|
clk_disable_unprepare(isc->ispck); |
|
unprepare_hclk: |
|
clk_disable_unprepare(isc->hclock); |
|
|
|
isc_clk_cleanup(isc); |
|
|
|
return ret; |
|
} |
|
|
|
static int microchip_xisc_remove(struct platform_device *pdev) |
|
{ |
|
struct isc_device *isc = platform_get_drvdata(pdev); |
|
|
|
pm_runtime_disable(&pdev->dev); |
|
|
|
isc_subdev_cleanup(isc); |
|
|
|
v4l2_device_unregister(&isc->v4l2_dev); |
|
|
|
clk_disable_unprepare(isc->ispck); |
|
clk_disable_unprepare(isc->hclock); |
|
|
|
isc_clk_cleanup(isc); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused xisc_runtime_suspend(struct device *dev) |
|
{ |
|
struct isc_device *isc = dev_get_drvdata(dev); |
|
|
|
clk_disable_unprepare(isc->ispck); |
|
clk_disable_unprepare(isc->hclock); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused xisc_runtime_resume(struct device *dev) |
|
{ |
|
struct isc_device *isc = dev_get_drvdata(dev); |
|
int ret; |
|
|
|
ret = clk_prepare_enable(isc->hclock); |
|
if (ret) |
|
return ret; |
|
|
|
ret = clk_prepare_enable(isc->ispck); |
|
if (ret) |
|
clk_disable_unprepare(isc->hclock); |
|
|
|
return ret; |
|
} |
|
|
|
static const struct dev_pm_ops microchip_xisc_dev_pm_ops = { |
|
SET_RUNTIME_PM_OPS(xisc_runtime_suspend, xisc_runtime_resume, NULL) |
|
}; |
|
|
|
static const struct of_device_id microchip_xisc_of_match[] = { |
|
{ .compatible = "microchip,sama7g5-isc" }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, microchip_xisc_of_match); |
|
|
|
static struct platform_driver microchip_xisc_driver = { |
|
.probe = microchip_xisc_probe, |
|
.remove = microchip_xisc_remove, |
|
.driver = { |
|
.name = "microchip-sama7g5-xisc", |
|
.pm = µchip_xisc_dev_pm_ops, |
|
.of_match_table = of_match_ptr(microchip_xisc_of_match), |
|
}, |
|
}; |
|
|
|
module_platform_driver(microchip_xisc_driver); |
|
|
|
MODULE_AUTHOR("Eugen Hristev <[email protected]>"); |
|
MODULE_DESCRIPTION("The V4L2 driver for Microchip-XISC"); |
|
MODULE_LICENSE("GPL v2");
|
|
|