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128 lines
3.3 KiB
128 lines
3.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __MCB_INTERNAL |
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#define __MCB_INTERNAL |
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#include <linux/types.h> |
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#define PCI_VENDOR_ID_MEN 0x1a88 |
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#define PCI_DEVICE_ID_MEN_CHAMELEON 0x4d45 |
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#define CHAMELEONV2_MAGIC 0xabce |
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#define CHAM_HEADER_SIZE 0x200 |
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enum chameleon_descriptor_type { |
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CHAMELEON_DTYPE_GENERAL = 0x0, |
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CHAMELEON_DTYPE_BRIDGE = 0x1, |
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CHAMELEON_DTYPE_CPU = 0x2, |
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CHAMELEON_DTYPE_BAR = 0x3, |
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CHAMELEON_DTYPE_END = 0xf, |
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}; |
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enum chameleon_bus_type { |
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CHAMELEON_BUS_WISHBONE, |
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CHAMELEON_BUS_AVALON, |
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CHAMELEON_BUS_LPC, |
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CHAMELEON_BUS_ISA, |
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}; |
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/** |
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* struct chameleon_fpga_header |
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* |
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* @revision: Revison of Chameleon table in FPGA |
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* @model: Chameleon table model ASCII char |
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* @minor: Revision minor |
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* @bus_type: Bus type (usually %CHAMELEON_BUS_WISHBONE) |
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* @magic: Chameleon header magic number (0xabce for version 2) |
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* @reserved: Reserved |
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* @filename: Filename of FPGA bitstream |
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*/ |
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struct chameleon_fpga_header { |
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u8 revision; |
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char model; |
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u8 minor; |
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u8 bus_type; |
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u16 magic; |
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u16 reserved; |
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/* This one has no '\0' at the end!!! */ |
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char filename[CHAMELEON_FILENAME_LEN]; |
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} __packed; |
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#define HEADER_MAGIC_OFFSET 0x4 |
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/** |
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* struct chameleon_gdd - Chameleon General Device Descriptor |
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* |
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* @irq: the position in the FPGA's IRQ controller vector |
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* @rev: the revision of the variant's implementation |
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* @var: the variant of the IP core |
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* @dev: the device the IP core is |
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* @dtype: device descriptor type |
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* @bar: BAR offset that must be added to module offset |
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* @inst: the instance number of the device, 0 is first instance |
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* @group: the group the device belongs to (0 = no group) |
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* @reserved: reserved |
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* @offset: beginning of the address window of desired module |
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* @size: size of the module's address window |
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*/ |
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struct chameleon_gdd { |
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__le32 reg1; |
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__le32 reg2; |
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__le32 offset; |
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__le32 size; |
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} __packed; |
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/* GDD Register 1 fields */ |
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#define GDD_IRQ(x) ((x) & 0x1f) |
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#define GDD_REV(x) (((x) >> 5) & 0x3f) |
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#define GDD_VAR(x) (((x) >> 11) & 0x3f) |
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#define GDD_DEV(x) (((x) >> 18) & 0x3ff) |
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#define GDD_DTY(x) (((x) >> 28) & 0xf) |
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/* GDD Register 2 fields */ |
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#define GDD_BAR(x) ((x) & 0x7) |
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#define GDD_INS(x) (((x) >> 3) & 0x3f) |
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#define GDD_GRP(x) (((x) >> 9) & 0x3f) |
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/** |
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* struct chameleon_bdd - Chameleon Bridge Device Descriptor |
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* |
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* @irq: the position in the FPGA's IRQ controller vector |
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* @rev: the revision of the variant's implementation |
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* @var: the variant of the IP core |
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* @dev: the device the IP core is |
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* @dtype: device descriptor type |
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* @bar: BAR offset that must be added to module offset |
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* @inst: the instance number of the device, 0 is first instance |
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* @dbar: destination bar from the bus _behind_ the bridge |
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* @chamoff: offset within the BAR of the source bus |
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* @offset: |
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* @size: |
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*/ |
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struct chameleon_bdd { |
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unsigned int irq:6; |
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unsigned int rev:6; |
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unsigned int var:6; |
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unsigned int dev:10; |
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unsigned int dtype:4; |
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unsigned int bar:3; |
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unsigned int inst:6; |
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unsigned int dbar:3; |
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unsigned int group:6; |
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unsigned int reserved:14; |
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u32 chamoff; |
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u32 offset; |
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u32 size; |
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} __packed; |
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struct chameleon_bar { |
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u32 addr; |
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u32 size; |
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}; |
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#define BAR_CNT(x) ((x) & 0x07) |
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#define CHAMELEON_BAR_MAX 6 |
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#define BAR_DESC_SIZE(x) ((x) * sizeof(struct chameleon_bar) + sizeof(__le32)) |
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int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase, |
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void __iomem *base); |
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#endif
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