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393 lines
9.7 KiB
393 lines
9.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved |
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* Authors: Ludovic Barre <[email protected]> for STMicroelectronics. |
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* Fabien Dessenne <[email protected]> for STMicroelectronics. |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/mailbox_controller.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_wakeirq.h> |
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#define IPCC_XCR 0x000 |
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#define XCR_RXOIE BIT(0) |
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#define XCR_TXOIE BIT(16) |
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#define IPCC_XMR 0x004 |
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#define IPCC_XSCR 0x008 |
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#define IPCC_XTOYSR 0x00c |
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#define IPCC_PROC_OFFST 0x010 |
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#define IPCC_HWCFGR 0x3f0 |
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#define IPCFGR_CHAN_MASK GENMASK(7, 0) |
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#define IPCC_VER 0x3f4 |
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#define VER_MINREV_MASK GENMASK(3, 0) |
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#define VER_MAJREV_MASK GENMASK(7, 4) |
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#define RX_BIT_MASK GENMASK(15, 0) |
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#define RX_BIT_CHAN(chan) BIT(chan) |
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#define TX_BIT_SHIFT 16 |
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#define TX_BIT_MASK GENMASK(31, 16) |
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#define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan)) |
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#define STM32_MAX_PROCS 2 |
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enum { |
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IPCC_IRQ_RX, |
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IPCC_IRQ_TX, |
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IPCC_IRQ_NUM, |
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}; |
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struct stm32_ipcc { |
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struct mbox_controller controller; |
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void __iomem *reg_base; |
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void __iomem *reg_proc; |
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struct clk *clk; |
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spinlock_t lock; /* protect access to IPCC registers */ |
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int irqs[IPCC_IRQ_NUM]; |
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u32 proc_id; |
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u32 n_chans; |
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u32 xcr; |
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u32 xmr; |
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}; |
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static inline void stm32_ipcc_set_bits(spinlock_t *lock, void __iomem *reg, |
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u32 mask) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(lock, flags); |
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writel_relaxed(readl_relaxed(reg) | mask, reg); |
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spin_unlock_irqrestore(lock, flags); |
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} |
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static inline void stm32_ipcc_clr_bits(spinlock_t *lock, void __iomem *reg, |
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u32 mask) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(lock, flags); |
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writel_relaxed(readl_relaxed(reg) & ~mask, reg); |
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spin_unlock_irqrestore(lock, flags); |
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} |
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static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data) |
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{ |
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struct stm32_ipcc *ipcc = data; |
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struct device *dev = ipcc->controller.dev; |
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u32 status, mr, tosr, chan; |
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irqreturn_t ret = IRQ_NONE; |
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int proc_offset; |
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/* read 'channel occupied' status from other proc */ |
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proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST; |
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tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); |
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mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); |
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/* search for unmasked 'channel occupied' */ |
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status = tosr & FIELD_GET(RX_BIT_MASK, ~mr); |
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for (chan = 0; chan < ipcc->n_chans; chan++) { |
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if (!(status & (1 << chan))) |
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continue; |
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dev_dbg(dev, "%s: chan:%d rx\n", __func__, chan); |
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mbox_chan_received_data(&ipcc->controller.chans[chan], NULL); |
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stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR, |
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RX_BIT_CHAN(chan)); |
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ret = IRQ_HANDLED; |
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} |
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return ret; |
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} |
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static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data) |
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{ |
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struct stm32_ipcc *ipcc = data; |
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struct device *dev = ipcc->controller.dev; |
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u32 status, mr, tosr, chan; |
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irqreturn_t ret = IRQ_NONE; |
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tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR); |
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mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); |
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/* search for unmasked 'channel free' */ |
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status = ~tosr & FIELD_GET(TX_BIT_MASK, ~mr); |
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for (chan = 0; chan < ipcc->n_chans ; chan++) { |
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if (!(status & (1 << chan))) |
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continue; |
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dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan); |
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/* mask 'tx channel free' interrupt */ |
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stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, |
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TX_BIT_CHAN(chan)); |
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mbox_chan_txdone(&ipcc->controller.chans[chan], 0); |
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ret = IRQ_HANDLED; |
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} |
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return ret; |
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} |
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static int stm32_ipcc_send_data(struct mbox_chan *link, void *data) |
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{ |
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unsigned long chan = (unsigned long)link->con_priv; |
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struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc, |
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controller); |
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dev_dbg(ipcc->controller.dev, "%s: chan:%lu\n", __func__, chan); |
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/* set channel n occupied */ |
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stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR, |
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TX_BIT_CHAN(chan)); |
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/* unmask 'tx channel free' interrupt */ |
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stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, |
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TX_BIT_CHAN(chan)); |
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return 0; |
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} |
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static int stm32_ipcc_startup(struct mbox_chan *link) |
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{ |
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unsigned long chan = (unsigned long)link->con_priv; |
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struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc, |
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controller); |
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int ret; |
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ret = clk_prepare_enable(ipcc->clk); |
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if (ret) { |
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dev_err(ipcc->controller.dev, "can not enable the clock\n"); |
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return ret; |
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} |
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/* unmask 'rx channel occupied' interrupt */ |
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stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, |
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RX_BIT_CHAN(chan)); |
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return 0; |
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} |
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static void stm32_ipcc_shutdown(struct mbox_chan *link) |
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{ |
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unsigned long chan = (unsigned long)link->con_priv; |
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struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc, |
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controller); |
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/* mask rx/tx interrupt */ |
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stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, |
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RX_BIT_CHAN(chan) | TX_BIT_CHAN(chan)); |
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clk_disable_unprepare(ipcc->clk); |
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} |
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static const struct mbox_chan_ops stm32_ipcc_ops = { |
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.send_data = stm32_ipcc_send_data, |
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.startup = stm32_ipcc_startup, |
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.shutdown = stm32_ipcc_shutdown, |
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}; |
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static int stm32_ipcc_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *np = dev->of_node; |
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struct stm32_ipcc *ipcc; |
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struct resource *res; |
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unsigned long i; |
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int ret; |
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u32 ip_ver; |
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static const char * const irq_name[] = {"rx", "tx"}; |
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irq_handler_t irq_thread[] = {stm32_ipcc_rx_irq, stm32_ipcc_tx_irq}; |
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if (!np) { |
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dev_err(dev, "No DT found\n"); |
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return -ENODEV; |
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} |
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ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL); |
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if (!ipcc) |
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return -ENOMEM; |
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spin_lock_init(&ipcc->lock); |
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/* proc_id */ |
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if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) { |
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dev_err(dev, "Missing st,proc-id\n"); |
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return -ENODEV; |
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} |
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if (ipcc->proc_id >= STM32_MAX_PROCS) { |
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dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id); |
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return -EINVAL; |
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} |
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/* regs */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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ipcc->reg_base = devm_ioremap_resource(dev, res); |
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if (IS_ERR(ipcc->reg_base)) |
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return PTR_ERR(ipcc->reg_base); |
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ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; |
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/* clock */ |
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ipcc->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(ipcc->clk)) |
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return PTR_ERR(ipcc->clk); |
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ret = clk_prepare_enable(ipcc->clk); |
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if (ret) { |
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dev_err(dev, "can not enable the clock\n"); |
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return ret; |
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} |
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/* irq */ |
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for (i = 0; i < IPCC_IRQ_NUM; i++) { |
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ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]); |
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if (ipcc->irqs[i] < 0) { |
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ret = ipcc->irqs[i]; |
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goto err_clk; |
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} |
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ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL, |
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irq_thread[i], IRQF_ONESHOT, |
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dev_name(dev), ipcc); |
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if (ret) { |
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dev_err(dev, "failed to request irq %lu (%d)\n", i, ret); |
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goto err_clk; |
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} |
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} |
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/* mask and enable rx/tx irq */ |
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stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, |
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RX_BIT_MASK | TX_BIT_MASK); |
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stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XCR, |
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XCR_RXOIE | XCR_TXOIE); |
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/* wakeup */ |
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if (of_property_read_bool(np, "wakeup-source")) { |
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device_set_wakeup_capable(dev, true); |
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ret = dev_pm_set_wake_irq(dev, ipcc->irqs[IPCC_IRQ_RX]); |
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if (ret) { |
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dev_err(dev, "Failed to set wake up irq\n"); |
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goto err_init_wkp; |
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} |
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} |
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/* mailbox controller */ |
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ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR); |
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ipcc->n_chans &= IPCFGR_CHAN_MASK; |
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ipcc->controller.dev = dev; |
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ipcc->controller.txdone_irq = true; |
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ipcc->controller.ops = &stm32_ipcc_ops; |
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ipcc->controller.num_chans = ipcc->n_chans; |
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ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans, |
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sizeof(*ipcc->controller.chans), |
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GFP_KERNEL); |
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if (!ipcc->controller.chans) { |
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ret = -ENOMEM; |
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goto err_irq_wkp; |
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} |
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for (i = 0; i < ipcc->controller.num_chans; i++) |
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ipcc->controller.chans[i].con_priv = (void *)i; |
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ret = devm_mbox_controller_register(dev, &ipcc->controller); |
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if (ret) |
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goto err_irq_wkp; |
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platform_set_drvdata(pdev, ipcc); |
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ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER); |
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dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n", |
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FIELD_GET(VER_MAJREV_MASK, ip_ver), |
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FIELD_GET(VER_MINREV_MASK, ip_ver), |
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ipcc->controller.num_chans, ipcc->proc_id); |
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clk_disable_unprepare(ipcc->clk); |
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return 0; |
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err_irq_wkp: |
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if (of_property_read_bool(np, "wakeup-source")) |
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dev_pm_clear_wake_irq(dev); |
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err_init_wkp: |
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device_set_wakeup_capable(dev, false); |
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err_clk: |
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clk_disable_unprepare(ipcc->clk); |
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return ret; |
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} |
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static int stm32_ipcc_remove(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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if (of_property_read_bool(dev->of_node, "wakeup-source")) |
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dev_pm_clear_wake_irq(&pdev->dev); |
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device_set_wakeup_capable(dev, false); |
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return 0; |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int stm32_ipcc_suspend(struct device *dev) |
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{ |
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struct stm32_ipcc *ipcc = dev_get_drvdata(dev); |
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ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); |
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ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR); |
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return 0; |
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} |
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static int stm32_ipcc_resume(struct device *dev) |
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{ |
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struct stm32_ipcc *ipcc = dev_get_drvdata(dev); |
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writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR); |
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writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR); |
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return 0; |
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} |
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#endif |
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static SIMPLE_DEV_PM_OPS(stm32_ipcc_pm_ops, |
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stm32_ipcc_suspend, stm32_ipcc_resume); |
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static const struct of_device_id stm32_ipcc_of_match[] = { |
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{ .compatible = "st,stm32mp1-ipcc" }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, stm32_ipcc_of_match); |
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static struct platform_driver stm32_ipcc_driver = { |
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.driver = { |
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.name = "stm32-ipcc", |
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.pm = &stm32_ipcc_pm_ops, |
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.of_match_table = stm32_ipcc_of_match, |
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}, |
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.probe = stm32_ipcc_probe, |
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.remove = stm32_ipcc_remove, |
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}; |
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module_platform_driver(stm32_ipcc_driver); |
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MODULE_AUTHOR("Ludovic Barre <[email protected]>"); |
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MODULE_AUTHOR("Fabien Dessenne <[email protected]>"); |
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MODULE_DESCRIPTION("STM32 IPCC driver"); |
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MODULE_LICENSE("GPL v2");
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