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937 lines
22 KiB
937 lines
22 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* OMAP mailbox driver |
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* |
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* Copyright (C) 2006-2009 Nokia Corporation. All rights reserved. |
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* Copyright (C) 2013-2021 Texas Instruments Incorporated - https://www.ti.com |
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* |
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* Contact: Hiroshi DOYU <[email protected]> |
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* Suman Anna <[email protected]> |
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*/ |
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|
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#include <linux/interrupt.h> |
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#include <linux/spinlock.h> |
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#include <linux/mutex.h> |
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#include <linux/slab.h> |
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#include <linux/kfifo.h> |
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#include <linux/err.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/omap-mailbox.h> |
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#include <linux/mailbox_controller.h> |
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#include <linux/mailbox_client.h> |
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|
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#include "mailbox.h" |
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#define MAILBOX_REVISION 0x000 |
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#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) |
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#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) |
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#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) |
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#define OMAP2_MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u)) |
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#define OMAP2_MAILBOX_IRQENABLE(u) (0x104 + 8 * (u)) |
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#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u)) |
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#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u)) |
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#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u)) |
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#define MAILBOX_IRQSTATUS(type, u) (type ? OMAP4_MAILBOX_IRQSTATUS(u) : \ |
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OMAP2_MAILBOX_IRQSTATUS(u)) |
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#define MAILBOX_IRQENABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE(u) : \ |
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OMAP2_MAILBOX_IRQENABLE(u)) |
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#define MAILBOX_IRQDISABLE(type, u) (type ? OMAP4_MAILBOX_IRQENABLE_CLR(u) \ |
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: OMAP2_MAILBOX_IRQENABLE(u)) |
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#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) |
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#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) |
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|
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/* Interrupt register configuration types */ |
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#define MBOX_INTR_CFG_TYPE1 0 |
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#define MBOX_INTR_CFG_TYPE2 1 |
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struct omap_mbox_fifo { |
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unsigned long msg; |
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unsigned long fifo_stat; |
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unsigned long msg_stat; |
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unsigned long irqenable; |
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unsigned long irqstatus; |
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unsigned long irqdisable; |
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u32 intr_bit; |
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}; |
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struct omap_mbox_queue { |
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spinlock_t lock; |
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struct kfifo fifo; |
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struct work_struct work; |
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struct omap_mbox *mbox; |
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bool full; |
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}; |
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struct omap_mbox_match_data { |
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u32 intr_type; |
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}; |
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struct omap_mbox_device { |
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struct device *dev; |
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struct mutex cfg_lock; |
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void __iomem *mbox_base; |
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u32 *irq_ctx; |
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u32 num_users; |
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u32 num_fifos; |
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u32 intr_type; |
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struct omap_mbox **mboxes; |
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struct mbox_controller controller; |
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struct list_head elem; |
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}; |
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struct omap_mbox_fifo_info { |
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int tx_id; |
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int tx_usr; |
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int tx_irq; |
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int rx_id; |
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int rx_usr; |
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int rx_irq; |
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const char *name; |
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bool send_no_irq; |
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}; |
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struct omap_mbox { |
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const char *name; |
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int irq; |
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struct omap_mbox_queue *rxq; |
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struct device *dev; |
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struct omap_mbox_device *parent; |
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struct omap_mbox_fifo tx_fifo; |
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struct omap_mbox_fifo rx_fifo; |
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u32 intr_type; |
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struct mbox_chan *chan; |
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bool send_no_irq; |
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}; |
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|
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/* global variables for the mailbox devices */ |
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static DEFINE_MUTEX(omap_mbox_devices_lock); |
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static LIST_HEAD(omap_mbox_devices); |
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static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE; |
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module_param(mbox_kfifo_size, uint, S_IRUGO); |
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MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)"); |
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static struct omap_mbox *mbox_chan_to_omap_mbox(struct mbox_chan *chan) |
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{ |
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if (!chan || !chan->con_priv) |
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return NULL; |
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return (struct omap_mbox *)chan->con_priv; |
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} |
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static inline |
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unsigned int mbox_read_reg(struct omap_mbox_device *mdev, size_t ofs) |
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{ |
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return __raw_readl(mdev->mbox_base + ofs); |
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} |
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static inline |
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void mbox_write_reg(struct omap_mbox_device *mdev, u32 val, size_t ofs) |
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{ |
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__raw_writel(val, mdev->mbox_base + ofs); |
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} |
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/* Mailbox FIFO handle functions */ |
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static u32 mbox_fifo_read(struct omap_mbox *mbox) |
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{ |
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struct omap_mbox_fifo *fifo = &mbox->rx_fifo; |
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return mbox_read_reg(mbox->parent, fifo->msg); |
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} |
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static void mbox_fifo_write(struct omap_mbox *mbox, u32 msg) |
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{ |
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struct omap_mbox_fifo *fifo = &mbox->tx_fifo; |
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mbox_write_reg(mbox->parent, msg, fifo->msg); |
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} |
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static int mbox_fifo_empty(struct omap_mbox *mbox) |
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{ |
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struct omap_mbox_fifo *fifo = &mbox->rx_fifo; |
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return (mbox_read_reg(mbox->parent, fifo->msg_stat) == 0); |
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} |
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static int mbox_fifo_full(struct omap_mbox *mbox) |
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{ |
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struct omap_mbox_fifo *fifo = &mbox->tx_fifo; |
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return mbox_read_reg(mbox->parent, fifo->fifo_stat); |
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} |
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/* Mailbox IRQ handle functions */ |
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static void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
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{ |
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struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? |
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&mbox->tx_fifo : &mbox->rx_fifo; |
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u32 bit = fifo->intr_bit; |
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u32 irqstatus = fifo->irqstatus; |
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mbox_write_reg(mbox->parent, bit, irqstatus); |
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/* Flush posted write for irq status to avoid spurious interrupts */ |
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mbox_read_reg(mbox->parent, irqstatus); |
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} |
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static int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
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{ |
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struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? |
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&mbox->tx_fifo : &mbox->rx_fifo; |
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u32 bit = fifo->intr_bit; |
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u32 irqenable = fifo->irqenable; |
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u32 irqstatus = fifo->irqstatus; |
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u32 enable = mbox_read_reg(mbox->parent, irqenable); |
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u32 status = mbox_read_reg(mbox->parent, irqstatus); |
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return (int)(enable & status & bit); |
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} |
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static void _omap_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
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{ |
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u32 l; |
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struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? |
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&mbox->tx_fifo : &mbox->rx_fifo; |
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u32 bit = fifo->intr_bit; |
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u32 irqenable = fifo->irqenable; |
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l = mbox_read_reg(mbox->parent, irqenable); |
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l |= bit; |
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mbox_write_reg(mbox->parent, l, irqenable); |
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} |
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static void _omap_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) |
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{ |
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struct omap_mbox_fifo *fifo = (irq == IRQ_TX) ? |
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&mbox->tx_fifo : &mbox->rx_fifo; |
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u32 bit = fifo->intr_bit; |
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u32 irqdisable = fifo->irqdisable; |
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/* |
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* Read and update the interrupt configuration register for pre-OMAP4. |
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* OMAP4 and later SoCs have a dedicated interrupt disabling register. |
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*/ |
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if (!mbox->intr_type) |
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bit = mbox_read_reg(mbox->parent, irqdisable) & ~bit; |
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mbox_write_reg(mbox->parent, bit, irqdisable); |
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} |
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void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq) |
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{ |
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struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); |
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if (WARN_ON(!mbox)) |
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return; |
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_omap_mbox_enable_irq(mbox, irq); |
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} |
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EXPORT_SYMBOL(omap_mbox_enable_irq); |
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void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq) |
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{ |
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struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); |
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if (WARN_ON(!mbox)) |
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return; |
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_omap_mbox_disable_irq(mbox, irq); |
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} |
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EXPORT_SYMBOL(omap_mbox_disable_irq); |
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/* |
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* Message receiver(workqueue) |
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*/ |
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static void mbox_rx_work(struct work_struct *work) |
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{ |
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struct omap_mbox_queue *mq = |
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container_of(work, struct omap_mbox_queue, work); |
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mbox_msg_t data; |
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u32 msg; |
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int len; |
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while (kfifo_len(&mq->fifo) >= sizeof(msg)) { |
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len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); |
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WARN_ON(len != sizeof(msg)); |
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data = msg; |
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mbox_chan_received_data(mq->mbox->chan, (void *)data); |
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spin_lock_irq(&mq->lock); |
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if (mq->full) { |
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mq->full = false; |
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_omap_mbox_enable_irq(mq->mbox, IRQ_RX); |
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} |
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spin_unlock_irq(&mq->lock); |
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} |
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} |
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/* |
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* Mailbox interrupt handler |
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*/ |
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static void __mbox_tx_interrupt(struct omap_mbox *mbox) |
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{ |
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_omap_mbox_disable_irq(mbox, IRQ_TX); |
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ack_mbox_irq(mbox, IRQ_TX); |
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mbox_chan_txdone(mbox->chan, 0); |
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} |
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static void __mbox_rx_interrupt(struct omap_mbox *mbox) |
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{ |
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struct omap_mbox_queue *mq = mbox->rxq; |
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u32 msg; |
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int len; |
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while (!mbox_fifo_empty(mbox)) { |
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if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) { |
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_omap_mbox_disable_irq(mbox, IRQ_RX); |
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mq->full = true; |
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goto nomem; |
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} |
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msg = mbox_fifo_read(mbox); |
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len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg)); |
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WARN_ON(len != sizeof(msg)); |
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} |
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/* no more messages in the fifo. clear IRQ source. */ |
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ack_mbox_irq(mbox, IRQ_RX); |
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nomem: |
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schedule_work(&mbox->rxq->work); |
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} |
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static irqreturn_t mbox_interrupt(int irq, void *p) |
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{ |
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struct omap_mbox *mbox = p; |
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if (is_mbox_irq(mbox, IRQ_TX)) |
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__mbox_tx_interrupt(mbox); |
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if (is_mbox_irq(mbox, IRQ_RX)) |
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__mbox_rx_interrupt(mbox); |
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return IRQ_HANDLED; |
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} |
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static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, |
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void (*work)(struct work_struct *)) |
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{ |
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struct omap_mbox_queue *mq; |
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if (!work) |
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return NULL; |
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mq = kzalloc(sizeof(*mq), GFP_KERNEL); |
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if (!mq) |
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return NULL; |
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spin_lock_init(&mq->lock); |
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if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL)) |
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goto error; |
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INIT_WORK(&mq->work, work); |
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return mq; |
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error: |
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kfree(mq); |
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return NULL; |
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} |
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static void mbox_queue_free(struct omap_mbox_queue *q) |
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{ |
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kfifo_free(&q->fifo); |
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kfree(q); |
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} |
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static int omap_mbox_startup(struct omap_mbox *mbox) |
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{ |
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int ret = 0; |
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struct omap_mbox_queue *mq; |
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mq = mbox_queue_alloc(mbox, mbox_rx_work); |
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if (!mq) |
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return -ENOMEM; |
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mbox->rxq = mq; |
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mq->mbox = mbox; |
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ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED, |
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mbox->name, mbox); |
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if (unlikely(ret)) { |
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pr_err("failed to register mailbox interrupt:%d\n", ret); |
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goto fail_request_irq; |
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} |
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if (mbox->send_no_irq) |
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mbox->chan->txdone_method = TXDONE_BY_ACK; |
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_omap_mbox_enable_irq(mbox, IRQ_RX); |
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return 0; |
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fail_request_irq: |
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mbox_queue_free(mbox->rxq); |
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return ret; |
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} |
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static void omap_mbox_fini(struct omap_mbox *mbox) |
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{ |
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_omap_mbox_disable_irq(mbox, IRQ_RX); |
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free_irq(mbox->irq, mbox); |
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flush_work(&mbox->rxq->work); |
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mbox_queue_free(mbox->rxq); |
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} |
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static struct omap_mbox *omap_mbox_device_find(struct omap_mbox_device *mdev, |
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const char *mbox_name) |
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{ |
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struct omap_mbox *_mbox, *mbox = NULL; |
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struct omap_mbox **mboxes = mdev->mboxes; |
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int i; |
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if (!mboxes) |
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return NULL; |
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for (i = 0; (_mbox = mboxes[i]); i++) { |
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if (!strcmp(_mbox->name, mbox_name)) { |
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mbox = _mbox; |
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break; |
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} |
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} |
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return mbox; |
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} |
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struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl, |
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const char *chan_name) |
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{ |
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struct device *dev = cl->dev; |
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struct omap_mbox *mbox = NULL; |
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struct omap_mbox_device *mdev; |
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struct mbox_chan *chan; |
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unsigned long flags; |
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int ret; |
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if (!dev) |
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return ERR_PTR(-ENODEV); |
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if (dev->of_node) { |
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pr_err("%s: please use mbox_request_channel(), this API is supported only for OMAP non-DT usage\n", |
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__func__); |
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return ERR_PTR(-ENODEV); |
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} |
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mutex_lock(&omap_mbox_devices_lock); |
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list_for_each_entry(mdev, &omap_mbox_devices, elem) { |
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mbox = omap_mbox_device_find(mdev, chan_name); |
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if (mbox) |
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break; |
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} |
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mutex_unlock(&omap_mbox_devices_lock); |
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if (!mbox || !mbox->chan) |
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return ERR_PTR(-ENOENT); |
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chan = mbox->chan; |
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spin_lock_irqsave(&chan->lock, flags); |
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chan->msg_free = 0; |
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chan->msg_count = 0; |
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chan->active_req = NULL; |
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chan->cl = cl; |
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init_completion(&chan->tx_complete); |
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spin_unlock_irqrestore(&chan->lock, flags); |
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ret = chan->mbox->ops->startup(chan); |
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if (ret) { |
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pr_err("Unable to startup the chan (%d)\n", ret); |
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mbox_free_channel(chan); |
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chan = ERR_PTR(ret); |
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} |
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return chan; |
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} |
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EXPORT_SYMBOL(omap_mbox_request_channel); |
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static struct class omap_mbox_class = { .name = "mbox", }; |
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static int omap_mbox_register(struct omap_mbox_device *mdev) |
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{ |
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int ret; |
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int i; |
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struct omap_mbox **mboxes; |
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if (!mdev || !mdev->mboxes) |
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return -EINVAL; |
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mboxes = mdev->mboxes; |
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for (i = 0; mboxes[i]; i++) { |
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struct omap_mbox *mbox = mboxes[i]; |
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mbox->dev = device_create(&omap_mbox_class, mdev->dev, |
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0, mbox, "%s", mbox->name); |
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if (IS_ERR(mbox->dev)) { |
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ret = PTR_ERR(mbox->dev); |
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goto err_out; |
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} |
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} |
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mutex_lock(&omap_mbox_devices_lock); |
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list_add(&mdev->elem, &omap_mbox_devices); |
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mutex_unlock(&omap_mbox_devices_lock); |
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ret = devm_mbox_controller_register(mdev->dev, &mdev->controller); |
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err_out: |
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if (ret) { |
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while (i--) |
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device_unregister(mboxes[i]->dev); |
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} |
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return ret; |
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} |
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static int omap_mbox_unregister(struct omap_mbox_device *mdev) |
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{ |
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int i; |
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struct omap_mbox **mboxes; |
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if (!mdev || !mdev->mboxes) |
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return -EINVAL; |
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mutex_lock(&omap_mbox_devices_lock); |
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list_del(&mdev->elem); |
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mutex_unlock(&omap_mbox_devices_lock); |
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mboxes = mdev->mboxes; |
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for (i = 0; mboxes[i]; i++) |
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device_unregister(mboxes[i]->dev); |
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return 0; |
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} |
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static int omap_mbox_chan_startup(struct mbox_chan *chan) |
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{ |
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struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); |
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struct omap_mbox_device *mdev = mbox->parent; |
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int ret = 0; |
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mutex_lock(&mdev->cfg_lock); |
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pm_runtime_get_sync(mdev->dev); |
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ret = omap_mbox_startup(mbox); |
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if (ret) |
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pm_runtime_put_sync(mdev->dev); |
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mutex_unlock(&mdev->cfg_lock); |
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return ret; |
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} |
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static void omap_mbox_chan_shutdown(struct mbox_chan *chan) |
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{ |
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struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); |
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struct omap_mbox_device *mdev = mbox->parent; |
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mutex_lock(&mdev->cfg_lock); |
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omap_mbox_fini(mbox); |
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pm_runtime_put_sync(mdev->dev); |
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mutex_unlock(&mdev->cfg_lock); |
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} |
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static int omap_mbox_chan_send_noirq(struct omap_mbox *mbox, u32 msg) |
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{ |
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int ret = -EBUSY; |
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if (!mbox_fifo_full(mbox)) { |
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_omap_mbox_enable_irq(mbox, IRQ_RX); |
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mbox_fifo_write(mbox, msg); |
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ret = 0; |
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_omap_mbox_disable_irq(mbox, IRQ_RX); |
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/* we must read and ack the interrupt directly from here */ |
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mbox_fifo_read(mbox); |
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ack_mbox_irq(mbox, IRQ_RX); |
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} |
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return ret; |
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} |
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static int omap_mbox_chan_send(struct omap_mbox *mbox, u32 msg) |
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{ |
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int ret = -EBUSY; |
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if (!mbox_fifo_full(mbox)) { |
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mbox_fifo_write(mbox, msg); |
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ret = 0; |
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} |
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|
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/* always enable the interrupt */ |
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_omap_mbox_enable_irq(mbox, IRQ_TX); |
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return ret; |
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} |
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|
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static int omap_mbox_chan_send_data(struct mbox_chan *chan, void *data) |
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{ |
|
struct omap_mbox *mbox = mbox_chan_to_omap_mbox(chan); |
|
int ret; |
|
u32 msg = omap_mbox_message(data); |
|
|
|
if (!mbox) |
|
return -EINVAL; |
|
|
|
if (mbox->send_no_irq) |
|
ret = omap_mbox_chan_send_noirq(mbox, msg); |
|
else |
|
ret = omap_mbox_chan_send(mbox, msg); |
|
|
|
return ret; |
|
} |
|
|
|
static const struct mbox_chan_ops omap_mbox_chan_ops = { |
|
.startup = omap_mbox_chan_startup, |
|
.send_data = omap_mbox_chan_send_data, |
|
.shutdown = omap_mbox_chan_shutdown, |
|
}; |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int omap_mbox_suspend(struct device *dev) |
|
{ |
|
struct omap_mbox_device *mdev = dev_get_drvdata(dev); |
|
u32 usr, fifo, reg; |
|
|
|
if (pm_runtime_status_suspended(dev)) |
|
return 0; |
|
|
|
for (fifo = 0; fifo < mdev->num_fifos; fifo++) { |
|
if (mbox_read_reg(mdev, MAILBOX_MSGSTATUS(fifo))) { |
|
dev_err(mdev->dev, "fifo %d has unexpected unread messages\n", |
|
fifo); |
|
return -EBUSY; |
|
} |
|
} |
|
|
|
for (usr = 0; usr < mdev->num_users; usr++) { |
|
reg = MAILBOX_IRQENABLE(mdev->intr_type, usr); |
|
mdev->irq_ctx[usr] = mbox_read_reg(mdev, reg); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int omap_mbox_resume(struct device *dev) |
|
{ |
|
struct omap_mbox_device *mdev = dev_get_drvdata(dev); |
|
u32 usr, reg; |
|
|
|
if (pm_runtime_status_suspended(dev)) |
|
return 0; |
|
|
|
for (usr = 0; usr < mdev->num_users; usr++) { |
|
reg = MAILBOX_IRQENABLE(mdev->intr_type, usr); |
|
mbox_write_reg(mdev, mdev->irq_ctx[usr], reg); |
|
} |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
static const struct dev_pm_ops omap_mbox_pm_ops = { |
|
SET_SYSTEM_SLEEP_PM_OPS(omap_mbox_suspend, omap_mbox_resume) |
|
}; |
|
|
|
static const struct omap_mbox_match_data omap2_data = { MBOX_INTR_CFG_TYPE1 }; |
|
static const struct omap_mbox_match_data omap4_data = { MBOX_INTR_CFG_TYPE2 }; |
|
|
|
static const struct of_device_id omap_mailbox_of_match[] = { |
|
{ |
|
.compatible = "ti,omap2-mailbox", |
|
.data = &omap2_data, |
|
}, |
|
{ |
|
.compatible = "ti,omap3-mailbox", |
|
.data = &omap2_data, |
|
}, |
|
{ |
|
.compatible = "ti,omap4-mailbox", |
|
.data = &omap4_data, |
|
}, |
|
{ |
|
.compatible = "ti,am654-mailbox", |
|
.data = &omap4_data, |
|
}, |
|
{ |
|
.compatible = "ti,am64-mailbox", |
|
.data = &omap4_data, |
|
}, |
|
{ |
|
/* end */ |
|
}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, omap_mailbox_of_match); |
|
|
|
static struct mbox_chan *omap_mbox_of_xlate(struct mbox_controller *controller, |
|
const struct of_phandle_args *sp) |
|
{ |
|
phandle phandle = sp->args[0]; |
|
struct device_node *node; |
|
struct omap_mbox_device *mdev; |
|
struct omap_mbox *mbox; |
|
|
|
mdev = container_of(controller, struct omap_mbox_device, controller); |
|
if (WARN_ON(!mdev)) |
|
return ERR_PTR(-EINVAL); |
|
|
|
node = of_find_node_by_phandle(phandle); |
|
if (!node) { |
|
pr_err("%s: could not find node phandle 0x%x\n", |
|
__func__, phandle); |
|
return ERR_PTR(-ENODEV); |
|
} |
|
|
|
mbox = omap_mbox_device_find(mdev, node->name); |
|
of_node_put(node); |
|
return mbox ? mbox->chan : ERR_PTR(-ENOENT); |
|
} |
|
|
|
static int omap_mbox_probe(struct platform_device *pdev) |
|
{ |
|
struct resource *mem; |
|
int ret; |
|
struct mbox_chan *chnls; |
|
struct omap_mbox **list, *mbox, *mboxblk; |
|
struct omap_mbox_fifo_info *finfo, *finfoblk; |
|
struct omap_mbox_device *mdev; |
|
struct omap_mbox_fifo *fifo; |
|
struct device_node *node = pdev->dev.of_node; |
|
struct device_node *child; |
|
const struct omap_mbox_match_data *match_data; |
|
u32 intr_type, info_count; |
|
u32 num_users, num_fifos; |
|
u32 tmp[3]; |
|
u32 l; |
|
int i; |
|
|
|
if (!node) { |
|
pr_err("%s: only DT-based devices are supported\n", __func__); |
|
return -ENODEV; |
|
} |
|
|
|
match_data = of_device_get_match_data(&pdev->dev); |
|
if (!match_data) |
|
return -ENODEV; |
|
intr_type = match_data->intr_type; |
|
|
|
if (of_property_read_u32(node, "ti,mbox-num-users", &num_users)) |
|
return -ENODEV; |
|
|
|
if (of_property_read_u32(node, "ti,mbox-num-fifos", &num_fifos)) |
|
return -ENODEV; |
|
|
|
info_count = of_get_available_child_count(node); |
|
if (!info_count) { |
|
dev_err(&pdev->dev, "no available mbox devices found\n"); |
|
return -ENODEV; |
|
} |
|
|
|
finfoblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*finfoblk), |
|
GFP_KERNEL); |
|
if (!finfoblk) |
|
return -ENOMEM; |
|
|
|
finfo = finfoblk; |
|
child = NULL; |
|
for (i = 0; i < info_count; i++, finfo++) { |
|
child = of_get_next_available_child(node, child); |
|
ret = of_property_read_u32_array(child, "ti,mbox-tx", tmp, |
|
ARRAY_SIZE(tmp)); |
|
if (ret) |
|
return ret; |
|
finfo->tx_id = tmp[0]; |
|
finfo->tx_irq = tmp[1]; |
|
finfo->tx_usr = tmp[2]; |
|
|
|
ret = of_property_read_u32_array(child, "ti,mbox-rx", tmp, |
|
ARRAY_SIZE(tmp)); |
|
if (ret) |
|
return ret; |
|
finfo->rx_id = tmp[0]; |
|
finfo->rx_irq = tmp[1]; |
|
finfo->rx_usr = tmp[2]; |
|
|
|
finfo->name = child->name; |
|
|
|
if (of_find_property(child, "ti,mbox-send-noirq", NULL)) |
|
finfo->send_no_irq = true; |
|
|
|
if (finfo->tx_id >= num_fifos || finfo->rx_id >= num_fifos || |
|
finfo->tx_usr >= num_users || finfo->rx_usr >= num_users) |
|
return -EINVAL; |
|
} |
|
|
|
mdev = devm_kzalloc(&pdev->dev, sizeof(*mdev), GFP_KERNEL); |
|
if (!mdev) |
|
return -ENOMEM; |
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
mdev->mbox_base = devm_ioremap_resource(&pdev->dev, mem); |
|
if (IS_ERR(mdev->mbox_base)) |
|
return PTR_ERR(mdev->mbox_base); |
|
|
|
mdev->irq_ctx = devm_kcalloc(&pdev->dev, num_users, sizeof(u32), |
|
GFP_KERNEL); |
|
if (!mdev->irq_ctx) |
|
return -ENOMEM; |
|
|
|
/* allocate one extra for marking end of list */ |
|
list = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*list), |
|
GFP_KERNEL); |
|
if (!list) |
|
return -ENOMEM; |
|
|
|
chnls = devm_kcalloc(&pdev->dev, info_count + 1, sizeof(*chnls), |
|
GFP_KERNEL); |
|
if (!chnls) |
|
return -ENOMEM; |
|
|
|
mboxblk = devm_kcalloc(&pdev->dev, info_count, sizeof(*mbox), |
|
GFP_KERNEL); |
|
if (!mboxblk) |
|
return -ENOMEM; |
|
|
|
mbox = mboxblk; |
|
finfo = finfoblk; |
|
for (i = 0; i < info_count; i++, finfo++) { |
|
fifo = &mbox->tx_fifo; |
|
fifo->msg = MAILBOX_MESSAGE(finfo->tx_id); |
|
fifo->fifo_stat = MAILBOX_FIFOSTATUS(finfo->tx_id); |
|
fifo->intr_bit = MAILBOX_IRQ_NOTFULL(finfo->tx_id); |
|
fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->tx_usr); |
|
fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->tx_usr); |
|
fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->tx_usr); |
|
|
|
fifo = &mbox->rx_fifo; |
|
fifo->msg = MAILBOX_MESSAGE(finfo->rx_id); |
|
fifo->msg_stat = MAILBOX_MSGSTATUS(finfo->rx_id); |
|
fifo->intr_bit = MAILBOX_IRQ_NEWMSG(finfo->rx_id); |
|
fifo->irqenable = MAILBOX_IRQENABLE(intr_type, finfo->rx_usr); |
|
fifo->irqstatus = MAILBOX_IRQSTATUS(intr_type, finfo->rx_usr); |
|
fifo->irqdisable = MAILBOX_IRQDISABLE(intr_type, finfo->rx_usr); |
|
|
|
mbox->send_no_irq = finfo->send_no_irq; |
|
mbox->intr_type = intr_type; |
|
|
|
mbox->parent = mdev; |
|
mbox->name = finfo->name; |
|
mbox->irq = platform_get_irq(pdev, finfo->tx_irq); |
|
if (mbox->irq < 0) |
|
return mbox->irq; |
|
mbox->chan = &chnls[i]; |
|
chnls[i].con_priv = mbox; |
|
list[i] = mbox++; |
|
} |
|
|
|
mutex_init(&mdev->cfg_lock); |
|
mdev->dev = &pdev->dev; |
|
mdev->num_users = num_users; |
|
mdev->num_fifos = num_fifos; |
|
mdev->intr_type = intr_type; |
|
mdev->mboxes = list; |
|
|
|
/* |
|
* OMAP/K3 Mailbox IP does not have a Tx-Done IRQ, but rather a Tx-Ready |
|
* IRQ and is needed to run the Tx state machine |
|
*/ |
|
mdev->controller.txdone_irq = true; |
|
mdev->controller.dev = mdev->dev; |
|
mdev->controller.ops = &omap_mbox_chan_ops; |
|
mdev->controller.chans = chnls; |
|
mdev->controller.num_chans = info_count; |
|
mdev->controller.of_xlate = omap_mbox_of_xlate; |
|
ret = omap_mbox_register(mdev); |
|
if (ret) |
|
return ret; |
|
|
|
platform_set_drvdata(pdev, mdev); |
|
pm_runtime_enable(mdev->dev); |
|
|
|
ret = pm_runtime_get_sync(mdev->dev); |
|
if (ret < 0) { |
|
pm_runtime_put_noidle(mdev->dev); |
|
goto unregister; |
|
} |
|
|
|
/* |
|
* just print the raw revision register, the format is not |
|
* uniform across all SoCs |
|
*/ |
|
l = mbox_read_reg(mdev, MAILBOX_REVISION); |
|
dev_info(mdev->dev, "omap mailbox rev 0x%x\n", l); |
|
|
|
ret = pm_runtime_put_sync(mdev->dev); |
|
if (ret < 0 && ret != -ENOSYS) |
|
goto unregister; |
|
|
|
devm_kfree(&pdev->dev, finfoblk); |
|
return 0; |
|
|
|
unregister: |
|
pm_runtime_disable(mdev->dev); |
|
omap_mbox_unregister(mdev); |
|
return ret; |
|
} |
|
|
|
static int omap_mbox_remove(struct platform_device *pdev) |
|
{ |
|
struct omap_mbox_device *mdev = platform_get_drvdata(pdev); |
|
|
|
pm_runtime_disable(mdev->dev); |
|
omap_mbox_unregister(mdev); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver omap_mbox_driver = { |
|
.probe = omap_mbox_probe, |
|
.remove = omap_mbox_remove, |
|
.driver = { |
|
.name = "omap-mailbox", |
|
.pm = &omap_mbox_pm_ops, |
|
.of_match_table = of_match_ptr(omap_mailbox_of_match), |
|
}, |
|
}; |
|
|
|
static int __init omap_mbox_init(void) |
|
{ |
|
int err; |
|
|
|
err = class_register(&omap_mbox_class); |
|
if (err) |
|
return err; |
|
|
|
/* kfifo size sanity check: alignment and minimal size */ |
|
mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(u32)); |
|
mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(u32)); |
|
|
|
err = platform_driver_register(&omap_mbox_driver); |
|
if (err) |
|
class_unregister(&omap_mbox_class); |
|
|
|
return err; |
|
} |
|
subsys_initcall(omap_mbox_init); |
|
|
|
static void __exit omap_mbox_exit(void) |
|
{ |
|
platform_driver_unregister(&omap_mbox_driver); |
|
class_unregister(&omap_mbox_class); |
|
} |
|
module_exit(omap_mbox_exit); |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); |
|
MODULE_AUTHOR("Toshihiro Kobayashi"); |
|
MODULE_AUTHOR("Hiroshi DOYU");
|
|
|