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161 lines
4.3 KiB
161 lines
4.3 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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// Copyright 2021 Jonathan Neuschäfer |
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#include <linux/irqchip.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/printk.h> |
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#include <asm/exception.h> |
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#define AIC_SCR(x) ((x)*4) /* Source control registers */ |
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#define AIC_GEN 0x84 /* Interrupt group enable control register */ |
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#define AIC_GRSR 0x88 /* Interrupt group raw status register */ |
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#define AIC_IRSR 0x100 /* Interrupt raw status register */ |
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#define AIC_IASR 0x104 /* Interrupt active status register */ |
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#define AIC_ISR 0x108 /* Interrupt status register */ |
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#define AIC_IPER 0x10c /* Interrupt priority encoding register */ |
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#define AIC_ISNR 0x110 /* Interrupt source number register */ |
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#define AIC_IMR 0x114 /* Interrupt mask register */ |
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#define AIC_OISR 0x118 /* Output interrupt status register */ |
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#define AIC_MECR 0x120 /* Mask enable command register */ |
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#define AIC_MDCR 0x124 /* Mask disable command register */ |
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#define AIC_SSCR 0x128 /* Source set command register */ |
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#define AIC_SCCR 0x12c /* Source clear command register */ |
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#define AIC_EOSCR 0x130 /* End of service command register */ |
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#define AIC_SCR_SRCTYPE_LOW_LEVEL (0 << 6) |
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#define AIC_SCR_SRCTYPE_HIGH_LEVEL (1 << 6) |
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#define AIC_SCR_SRCTYPE_NEG_EDGE (2 << 6) |
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#define AIC_SCR_SRCTYPE_POS_EDGE (3 << 6) |
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#define AIC_SCR_PRIORITY(x) (x) |
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#define AIC_SCR_PRIORITY_MASK 0x7 |
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#define AIC_NUM_IRQS 32 |
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struct wpcm450_aic { |
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void __iomem *regs; |
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struct irq_domain *domain; |
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}; |
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static struct wpcm450_aic *aic; |
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static void wpcm450_aic_init_hw(void) |
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{ |
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int i; |
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/* Disable (mask) all interrupts */ |
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writel(0xffffffff, aic->regs + AIC_MDCR); |
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/* |
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* Make sure the interrupt controller is ready to serve new interrupts. |
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* Reading from IPER indicates that the nIRQ signal may be deasserted, |
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* and writing to EOSCR indicates that interrupt handling has finished. |
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*/ |
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readl(aic->regs + AIC_IPER); |
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writel(0, aic->regs + AIC_EOSCR); |
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/* Initialize trigger mode and priority of each interrupt source */ |
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for (i = 0; i < AIC_NUM_IRQS; i++) |
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writel(AIC_SCR_SRCTYPE_HIGH_LEVEL | AIC_SCR_PRIORITY(7), |
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aic->regs + AIC_SCR(i)); |
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} |
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static void __exception_irq_entry wpcm450_aic_handle_irq(struct pt_regs *regs) |
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{ |
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int hwirq; |
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/* Determine the interrupt source */ |
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/* Read IPER to signal that nIRQ can be de-asserted */ |
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hwirq = readl(aic->regs + AIC_IPER) / 4; |
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handle_domain_irq(aic->domain, hwirq, regs); |
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} |
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static void wpcm450_aic_eoi(struct irq_data *d) |
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{ |
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/* Signal end-of-service */ |
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writel(0, aic->regs + AIC_EOSCR); |
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} |
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static void wpcm450_aic_mask(struct irq_data *d) |
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{ |
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unsigned int mask = BIT(d->hwirq); |
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/* Disable (mask) the interrupt */ |
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writel(mask, aic->regs + AIC_MDCR); |
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} |
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static void wpcm450_aic_unmask(struct irq_data *d) |
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{ |
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unsigned int mask = BIT(d->hwirq); |
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/* Enable (unmask) the interrupt */ |
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writel(mask, aic->regs + AIC_MECR); |
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} |
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static int wpcm450_aic_set_type(struct irq_data *d, unsigned int flow_type) |
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{ |
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/* |
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* The hardware supports high/low level, as well as rising/falling edge |
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* modes, and the DT binding accommodates for that, but as long as |
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* other modes than high level mode are not used and can't be tested, |
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* they are rejected in this driver. |
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*/ |
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if ((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_HIGH) |
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return -EINVAL; |
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return 0; |
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} |
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static struct irq_chip wpcm450_aic_chip = { |
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.name = "wpcm450-aic", |
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.irq_eoi = wpcm450_aic_eoi, |
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.irq_mask = wpcm450_aic_mask, |
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.irq_unmask = wpcm450_aic_unmask, |
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.irq_set_type = wpcm450_aic_set_type, |
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}; |
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static int wpcm450_aic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) |
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{ |
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if (hwirq >= AIC_NUM_IRQS) |
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return -EPERM; |
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irq_set_chip_and_handler(irq, &wpcm450_aic_chip, handle_fasteoi_irq); |
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irq_set_chip_data(irq, aic); |
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irq_set_probe(irq); |
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return 0; |
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} |
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static const struct irq_domain_ops wpcm450_aic_ops = { |
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.map = wpcm450_aic_map, |
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.xlate = irq_domain_xlate_twocell, |
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}; |
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static int __init wpcm450_aic_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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if (parent) |
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return -EINVAL; |
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aic = kzalloc(sizeof(*aic), GFP_KERNEL); |
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if (!aic) |
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return -ENOMEM; |
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aic->regs = of_iomap(node, 0); |
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if (!aic->regs) { |
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pr_err("Failed to map WPCM450 AIC registers\n"); |
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return -ENOMEM; |
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} |
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wpcm450_aic_init_hw(); |
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set_handle_irq(wpcm450_aic_handle_irq); |
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aic->domain = irq_domain_add_linear(node, AIC_NUM_IRQS, &wpcm450_aic_ops, aic); |
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return 0; |
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} |
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IRQCHIP_DECLARE(wpcm450_aic, "nuvoton,wpcm450-aic", wpcm450_aic_of_init);
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