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359 lines
8.8 KiB
359 lines
8.8 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Actions Semi Owl SoCs SIRQ interrupt controller driver |
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* |
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* Copyright (C) 2014 Actions Semi Inc. |
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* David Liu <[email protected]> |
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* |
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* Author: Parthiban Nallathambi <[email protected]> |
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* Author: Saravanan Sekar <[email protected]> |
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* Author: Cristian Ciocaltea <[email protected]> |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/interrupt.h> |
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#include <linux/irqchip.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#define NUM_SIRQ 3 |
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#define INTC_EXTCTL_PENDING BIT(0) |
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#define INTC_EXTCTL_CLK_SEL BIT(4) |
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#define INTC_EXTCTL_EN BIT(5) |
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#define INTC_EXTCTL_TYPE_MASK GENMASK(7, 6) |
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#define INTC_EXTCTL_TYPE_HIGH 0 |
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#define INTC_EXTCTL_TYPE_LOW BIT(6) |
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#define INTC_EXTCTL_TYPE_RISING BIT(7) |
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#define INTC_EXTCTL_TYPE_FALLING (BIT(6) | BIT(7)) |
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/* S500 & S700 SIRQ control register masks */ |
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#define INTC_EXTCTL_SIRQ0_MASK GENMASK(23, 16) |
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#define INTC_EXTCTL_SIRQ1_MASK GENMASK(15, 8) |
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#define INTC_EXTCTL_SIRQ2_MASK GENMASK(7, 0) |
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/* S900 SIRQ control register offsets, relative to controller base address */ |
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#define INTC_EXTCTL0 0x0000 |
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#define INTC_EXTCTL1 0x0328 |
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#define INTC_EXTCTL2 0x032c |
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struct owl_sirq_params { |
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/* INTC_EXTCTL reg shared for all three SIRQ lines */ |
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bool reg_shared; |
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/* INTC_EXTCTL reg offsets relative to controller base address */ |
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u16 reg_offset[NUM_SIRQ]; |
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}; |
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struct owl_sirq_chip_data { |
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const struct owl_sirq_params *params; |
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void __iomem *base; |
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raw_spinlock_t lock; |
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u32 ext_irqs[NUM_SIRQ]; |
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}; |
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/* S500 & S700 SoCs */ |
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static const struct owl_sirq_params owl_sirq_s500_params = { |
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.reg_shared = true, |
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.reg_offset = { 0, 0, 0 }, |
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}; |
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/* S900 SoC */ |
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static const struct owl_sirq_params owl_sirq_s900_params = { |
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.reg_shared = false, |
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.reg_offset = { INTC_EXTCTL0, INTC_EXTCTL1, INTC_EXTCTL2 }, |
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}; |
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static u32 owl_field_get(u32 val, u32 index) |
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{ |
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switch (index) { |
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case 0: |
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return FIELD_GET(INTC_EXTCTL_SIRQ0_MASK, val); |
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case 1: |
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return FIELD_GET(INTC_EXTCTL_SIRQ1_MASK, val); |
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case 2: |
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default: |
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return FIELD_GET(INTC_EXTCTL_SIRQ2_MASK, val); |
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} |
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} |
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static u32 owl_field_prep(u32 val, u32 index) |
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{ |
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switch (index) { |
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case 0: |
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return FIELD_PREP(INTC_EXTCTL_SIRQ0_MASK, val); |
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case 1: |
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return FIELD_PREP(INTC_EXTCTL_SIRQ1_MASK, val); |
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case 2: |
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default: |
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return FIELD_PREP(INTC_EXTCTL_SIRQ2_MASK, val); |
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} |
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} |
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static u32 owl_sirq_read_extctl(struct owl_sirq_chip_data *data, u32 index) |
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{ |
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u32 val; |
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val = readl_relaxed(data->base + data->params->reg_offset[index]); |
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if (data->params->reg_shared) |
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val = owl_field_get(val, index); |
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return val; |
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} |
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static void owl_sirq_write_extctl(struct owl_sirq_chip_data *data, |
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u32 extctl, u32 index) |
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{ |
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u32 val; |
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if (data->params->reg_shared) { |
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val = readl_relaxed(data->base + data->params->reg_offset[index]); |
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val &= ~owl_field_prep(0xff, index); |
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extctl = owl_field_prep(extctl, index) | val; |
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} |
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writel_relaxed(extctl, data->base + data->params->reg_offset[index]); |
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} |
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static void owl_sirq_clear_set_extctl(struct owl_sirq_chip_data *d, |
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u32 clear, u32 set, u32 index) |
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{ |
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unsigned long flags; |
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u32 val; |
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raw_spin_lock_irqsave(&d->lock, flags); |
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val = owl_sirq_read_extctl(d, index); |
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val &= ~clear; |
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val |= set; |
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owl_sirq_write_extctl(d, val, index); |
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raw_spin_unlock_irqrestore(&d->lock, flags); |
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} |
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static void owl_sirq_eoi(struct irq_data *data) |
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{ |
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struct owl_sirq_chip_data *chip_data = irq_data_get_irq_chip_data(data); |
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/* |
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* Software must clear external interrupt pending, when interrupt type |
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* is edge triggered, so we need per SIRQ based clearing. |
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*/ |
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if (!irqd_is_level_type(data)) |
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owl_sirq_clear_set_extctl(chip_data, 0, INTC_EXTCTL_PENDING, |
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data->hwirq); |
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irq_chip_eoi_parent(data); |
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} |
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static void owl_sirq_mask(struct irq_data *data) |
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{ |
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struct owl_sirq_chip_data *chip_data = irq_data_get_irq_chip_data(data); |
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owl_sirq_clear_set_extctl(chip_data, INTC_EXTCTL_EN, 0, data->hwirq); |
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irq_chip_mask_parent(data); |
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} |
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static void owl_sirq_unmask(struct irq_data *data) |
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{ |
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struct owl_sirq_chip_data *chip_data = irq_data_get_irq_chip_data(data); |
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owl_sirq_clear_set_extctl(chip_data, 0, INTC_EXTCTL_EN, data->hwirq); |
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irq_chip_unmask_parent(data); |
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} |
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/* |
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* GIC does not handle falling edge or active low, hence SIRQ shall be |
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* programmed to convert falling edge to rising edge signal and active |
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* low to active high signal. |
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*/ |
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static int owl_sirq_set_type(struct irq_data *data, unsigned int type) |
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{ |
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struct owl_sirq_chip_data *chip_data = irq_data_get_irq_chip_data(data); |
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u32 sirq_type; |
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switch (type) { |
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case IRQ_TYPE_LEVEL_LOW: |
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sirq_type = INTC_EXTCTL_TYPE_LOW; |
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type = IRQ_TYPE_LEVEL_HIGH; |
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break; |
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case IRQ_TYPE_LEVEL_HIGH: |
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sirq_type = INTC_EXTCTL_TYPE_HIGH; |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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sirq_type = INTC_EXTCTL_TYPE_FALLING; |
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type = IRQ_TYPE_EDGE_RISING; |
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break; |
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case IRQ_TYPE_EDGE_RISING: |
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sirq_type = INTC_EXTCTL_TYPE_RISING; |
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break; |
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default: |
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return -EINVAL; |
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} |
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owl_sirq_clear_set_extctl(chip_data, INTC_EXTCTL_TYPE_MASK, sirq_type, |
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data->hwirq); |
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return irq_chip_set_type_parent(data, type); |
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} |
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static struct irq_chip owl_sirq_chip = { |
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.name = "owl-sirq", |
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.irq_mask = owl_sirq_mask, |
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.irq_unmask = owl_sirq_unmask, |
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.irq_eoi = owl_sirq_eoi, |
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.irq_set_type = owl_sirq_set_type, |
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.irq_retrigger = irq_chip_retrigger_hierarchy, |
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#ifdef CONFIG_SMP |
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.irq_set_affinity = irq_chip_set_affinity_parent, |
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#endif |
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}; |
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static int owl_sirq_domain_translate(struct irq_domain *d, |
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struct irq_fwspec *fwspec, |
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unsigned long *hwirq, |
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unsigned int *type) |
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{ |
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if (!is_of_node(fwspec->fwnode)) |
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return -EINVAL; |
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if (fwspec->param_count != 2 || fwspec->param[0] >= NUM_SIRQ) |
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return -EINVAL; |
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*hwirq = fwspec->param[0]; |
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*type = fwspec->param[1]; |
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return 0; |
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} |
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static int owl_sirq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
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unsigned int nr_irqs, void *data) |
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{ |
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struct owl_sirq_chip_data *chip_data = domain->host_data; |
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struct irq_fwspec *fwspec = data; |
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struct irq_fwspec parent_fwspec; |
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irq_hw_number_t hwirq; |
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unsigned int type; |
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int ret; |
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if (WARN_ON(nr_irqs != 1)) |
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return -EINVAL; |
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ret = owl_sirq_domain_translate(domain, fwspec, &hwirq, &type); |
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if (ret) |
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return ret; |
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switch (type) { |
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case IRQ_TYPE_EDGE_RISING: |
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case IRQ_TYPE_LEVEL_HIGH: |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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type = IRQ_TYPE_EDGE_RISING; |
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break; |
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case IRQ_TYPE_LEVEL_LOW: |
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type = IRQ_TYPE_LEVEL_HIGH; |
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break; |
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default: |
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return -EINVAL; |
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} |
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irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &owl_sirq_chip, |
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chip_data); |
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parent_fwspec.fwnode = domain->parent->fwnode; |
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parent_fwspec.param_count = 3; |
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parent_fwspec.param[0] = GIC_SPI; |
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parent_fwspec.param[1] = chip_data->ext_irqs[hwirq]; |
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parent_fwspec.param[2] = type; |
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return irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec); |
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} |
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static const struct irq_domain_ops owl_sirq_domain_ops = { |
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.translate = owl_sirq_domain_translate, |
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.alloc = owl_sirq_domain_alloc, |
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.free = irq_domain_free_irqs_common, |
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}; |
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static int __init owl_sirq_init(const struct owl_sirq_params *params, |
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struct device_node *node, |
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struct device_node *parent) |
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{ |
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struct irq_domain *domain, *parent_domain; |
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struct owl_sirq_chip_data *chip_data; |
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int ret, i; |
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parent_domain = irq_find_host(parent); |
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if (!parent_domain) { |
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pr_err("%pOF: failed to find sirq parent domain\n", node); |
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return -ENXIO; |
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} |
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chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL); |
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if (!chip_data) |
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return -ENOMEM; |
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raw_spin_lock_init(&chip_data->lock); |
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chip_data->params = params; |
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chip_data->base = of_iomap(node, 0); |
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if (!chip_data->base) { |
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pr_err("%pOF: failed to map sirq registers\n", node); |
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ret = -ENXIO; |
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goto out_free; |
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} |
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for (i = 0; i < NUM_SIRQ; i++) { |
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struct of_phandle_args irq; |
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ret = of_irq_parse_one(node, i, &irq); |
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if (ret) { |
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pr_err("%pOF: failed to parse interrupt %d\n", node, i); |
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goto out_unmap; |
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} |
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if (WARN_ON(irq.args_count != 3)) { |
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ret = -EINVAL; |
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goto out_unmap; |
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} |
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chip_data->ext_irqs[i] = irq.args[1]; |
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/* Set 24MHz external interrupt clock freq */ |
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owl_sirq_clear_set_extctl(chip_data, 0, INTC_EXTCTL_CLK_SEL, i); |
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} |
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domain = irq_domain_add_hierarchy(parent_domain, 0, NUM_SIRQ, node, |
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&owl_sirq_domain_ops, chip_data); |
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if (!domain) { |
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pr_err("%pOF: failed to add domain\n", node); |
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ret = -ENOMEM; |
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goto out_unmap; |
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} |
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return 0; |
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out_unmap: |
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iounmap(chip_data->base); |
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out_free: |
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kfree(chip_data); |
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return ret; |
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} |
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static int __init owl_sirq_s500_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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return owl_sirq_init(&owl_sirq_s500_params, node, parent); |
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} |
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IRQCHIP_DECLARE(owl_sirq_s500, "actions,s500-sirq", owl_sirq_s500_of_init); |
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IRQCHIP_DECLARE(owl_sirq_s700, "actions,s700-sirq", owl_sirq_s500_of_init); |
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static int __init owl_sirq_s900_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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return owl_sirq_init(&owl_sirq_s900_params, node, parent); |
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} |
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IRQCHIP_DECLARE(owl_sirq_s900, "actions,s900-sirq", owl_sirq_s900_of_init);
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