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206 lines
5.7 KiB
206 lines
5.7 KiB
/* |
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* Marvell Orion SoCs IRQ chip driver. |
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* |
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* Sebastian Hesselbarth <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <asm/exception.h> |
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#include <asm/mach/irq.h> |
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/* |
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* Orion SoC main interrupt controller |
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*/ |
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#define ORION_IRQS_PER_CHIP 32 |
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#define ORION_IRQ_CAUSE 0x00 |
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#define ORION_IRQ_MASK 0x04 |
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#define ORION_IRQ_FIQ_MASK 0x08 |
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#define ORION_IRQ_ENDP_MASK 0x0c |
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static struct irq_domain *orion_irq_domain; |
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static void |
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__exception_irq_entry orion_handle_irq(struct pt_regs *regs) |
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{ |
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struct irq_domain_chip_generic *dgc = orion_irq_domain->gc; |
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int n, base = 0; |
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for (n = 0; n < dgc->num_chips; n++, base += ORION_IRQS_PER_CHIP) { |
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struct irq_chip_generic *gc = |
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irq_get_domain_generic_chip(orion_irq_domain, base); |
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u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) & |
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gc->mask_cache; |
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while (stat) { |
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u32 hwirq = __fls(stat); |
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handle_domain_irq(orion_irq_domain, |
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gc->irq_base + hwirq, regs); |
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stat &= ~(1 << hwirq); |
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} |
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} |
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} |
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static int __init orion_irq_init(struct device_node *np, |
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struct device_node *parent) |
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{ |
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
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int n, ret, base, num_chips = 0; |
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struct resource r; |
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/* count number of irq chips by valid reg addresses */ |
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while (of_address_to_resource(np, num_chips, &r) == 0) |
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num_chips++; |
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orion_irq_domain = irq_domain_add_linear(np, |
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num_chips * ORION_IRQS_PER_CHIP, |
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&irq_generic_chip_ops, NULL); |
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if (!orion_irq_domain) |
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panic("%pOFn: unable to add irq domain\n", np); |
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ret = irq_alloc_domain_generic_chips(orion_irq_domain, |
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ORION_IRQS_PER_CHIP, 1, np->full_name, |
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handle_level_irq, clr, 0, |
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IRQ_GC_INIT_MASK_CACHE); |
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if (ret) |
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panic("%pOFn: unable to alloc irq domain gc\n", np); |
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for (n = 0, base = 0; n < num_chips; n++, base += ORION_IRQS_PER_CHIP) { |
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struct irq_chip_generic *gc = |
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irq_get_domain_generic_chip(orion_irq_domain, base); |
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of_address_to_resource(np, n, &r); |
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if (!request_mem_region(r.start, resource_size(&r), np->name)) |
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panic("%pOFn: unable to request mem region %d", |
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np, n); |
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gc->reg_base = ioremap(r.start, resource_size(&r)); |
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if (!gc->reg_base) |
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panic("%pOFn: unable to map resource %d", np, n); |
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gc->chip_types[0].regs.mask = ORION_IRQ_MASK; |
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; |
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; |
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/* mask all interrupts */ |
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writel(0, gc->reg_base + ORION_IRQ_MASK); |
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} |
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set_handle_irq(orion_handle_irq); |
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return 0; |
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} |
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IRQCHIP_DECLARE(orion_intc, "marvell,orion-intc", orion_irq_init); |
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/* |
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* Orion SoC bridge interrupt controller |
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*/ |
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#define ORION_BRIDGE_IRQ_CAUSE 0x00 |
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#define ORION_BRIDGE_IRQ_MASK 0x04 |
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static void orion_bridge_irq_handler(struct irq_desc *desc) |
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{ |
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struct irq_domain *d = irq_desc_get_handler_data(desc); |
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struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0); |
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u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) & |
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gc->mask_cache; |
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while (stat) { |
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u32 hwirq = __fls(stat); |
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generic_handle_domain_irq(d, gc->irq_base + hwirq); |
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stat &= ~(1 << hwirq); |
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} |
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} |
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/* |
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* Bridge IRQ_CAUSE is asserted regardless of IRQ_MASK register. |
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* To avoid interrupt events on stale irqs, we clear them before unmask. |
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*/ |
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static unsigned int orion_bridge_irq_startup(struct irq_data *d) |
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{ |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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ct->chip.irq_ack(d); |
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ct->chip.irq_unmask(d); |
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return 0; |
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} |
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static int __init orion_bridge_irq_init(struct device_node *np, |
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struct device_node *parent) |
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{ |
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
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struct resource r; |
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struct irq_domain *domain; |
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struct irq_chip_generic *gc; |
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int ret, irq, nrirqs = 32; |
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/* get optional number of interrupts provided */ |
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of_property_read_u32(np, "marvell,#interrupts", &nrirqs); |
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domain = irq_domain_add_linear(np, nrirqs, |
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&irq_generic_chip_ops, NULL); |
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if (!domain) { |
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pr_err("%pOFn: unable to add irq domain\n", np); |
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return -ENOMEM; |
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} |
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ret = irq_alloc_domain_generic_chips(domain, nrirqs, 1, np->name, |
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handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE); |
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if (ret) { |
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pr_err("%pOFn: unable to alloc irq domain gc\n", np); |
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return ret; |
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} |
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ret = of_address_to_resource(np, 0, &r); |
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if (ret) { |
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pr_err("%pOFn: unable to get resource\n", np); |
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return ret; |
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} |
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if (!request_mem_region(r.start, resource_size(&r), np->name)) { |
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pr_err("%s: unable to request mem region\n", np->name); |
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return -ENOMEM; |
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} |
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/* Map the parent interrupt for the chained handler */ |
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irq = irq_of_parse_and_map(np, 0); |
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if (irq <= 0) { |
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pr_err("%pOFn: unable to parse irq\n", np); |
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return -EINVAL; |
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} |
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gc = irq_get_domain_generic_chip(domain, 0); |
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gc->reg_base = ioremap(r.start, resource_size(&r)); |
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if (!gc->reg_base) { |
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pr_err("%pOFn: unable to map resource\n", np); |
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return -ENOMEM; |
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} |
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gc->chip_types[0].regs.ack = ORION_BRIDGE_IRQ_CAUSE; |
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gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK; |
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gc->chip_types[0].chip.irq_startup = orion_bridge_irq_startup; |
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gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit; |
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; |
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; |
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/* mask and clear all interrupts */ |
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writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK); |
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writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE); |
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irq_set_chained_handler_and_data(irq, orion_bridge_irq_handler, |
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domain); |
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return 0; |
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} |
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IRQCHIP_DECLARE(orion_bridge_intc, |
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"marvell,orion-bridge-intc", orion_bridge_irq_init);
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