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163 lines
4.7 KiB
163 lines
4.7 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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// |
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// Copyright (C) 2006, 2019 Texas Instruments. |
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// |
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// Interrupt handler for DaVinci boards. |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip/irq-davinci-aintc.h> |
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#include <linux/io.h> |
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#include <linux/irqdomain.h> |
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#include <asm/exception.h> |
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#define DAVINCI_AINTC_FIQ_REG0 0x00 |
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#define DAVINCI_AINTC_FIQ_REG1 0x04 |
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#define DAVINCI_AINTC_IRQ_REG0 0x08 |
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#define DAVINCI_AINTC_IRQ_REG1 0x0c |
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#define DAVINCI_AINTC_IRQ_IRQENTRY 0x14 |
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#define DAVINCI_AINTC_IRQ_ENT_REG0 0x18 |
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#define DAVINCI_AINTC_IRQ_ENT_REG1 0x1c |
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#define DAVINCI_AINTC_IRQ_INCTL_REG 0x20 |
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#define DAVINCI_AINTC_IRQ_EABASE_REG 0x24 |
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#define DAVINCI_AINTC_IRQ_INTPRI0_REG 0x30 |
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#define DAVINCI_AINTC_IRQ_INTPRI7_REG 0x4c |
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static void __iomem *davinci_aintc_base; |
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static struct irq_domain *davinci_aintc_irq_domain; |
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static inline void davinci_aintc_writel(unsigned long value, int offset) |
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{ |
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writel_relaxed(value, davinci_aintc_base + offset); |
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} |
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static inline unsigned long davinci_aintc_readl(int offset) |
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{ |
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return readl_relaxed(davinci_aintc_base + offset); |
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} |
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static __init void |
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davinci_aintc_setup_gc(void __iomem *base, |
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unsigned int irq_start, unsigned int num) |
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{ |
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struct irq_chip_generic *gc; |
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struct irq_chip_type *ct; |
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gc = irq_get_domain_generic_chip(davinci_aintc_irq_domain, irq_start); |
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gc->reg_base = base; |
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gc->irq_base = irq_start; |
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ct = gc->chip_types; |
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ct->chip.irq_ack = irq_gc_ack_set_bit; |
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ct->chip.irq_mask = irq_gc_mask_clr_bit; |
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ct->chip.irq_unmask = irq_gc_mask_set_bit; |
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ct->regs.ack = DAVINCI_AINTC_IRQ_REG0; |
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ct->regs.mask = DAVINCI_AINTC_IRQ_ENT_REG0; |
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, |
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IRQ_NOREQUEST | IRQ_NOPROBE, 0); |
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} |
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static asmlinkage void __exception_irq_entry |
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davinci_aintc_handle_irq(struct pt_regs *regs) |
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{ |
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int irqnr = davinci_aintc_readl(DAVINCI_AINTC_IRQ_IRQENTRY); |
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/* |
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* Use the formula for entry vector index generation from section |
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* 8.3.3 of the manual. |
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*/ |
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irqnr >>= 2; |
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irqnr -= 1; |
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handle_domain_irq(davinci_aintc_irq_domain, irqnr, regs); |
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} |
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/* ARM Interrupt Controller Initialization */ |
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void __init davinci_aintc_init(const struct davinci_aintc_config *config) |
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{ |
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unsigned int irq_off, reg_off, prio, shift; |
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void __iomem *req; |
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int ret, irq_base; |
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const u8 *prios; |
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req = request_mem_region(config->reg.start, |
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resource_size(&config->reg), |
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"davinci-cp-intc"); |
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if (!req) { |
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pr_err("%s: register range busy\n", __func__); |
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return; |
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} |
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davinci_aintc_base = ioremap(config->reg.start, |
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resource_size(&config->reg)); |
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if (!davinci_aintc_base) { |
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pr_err("%s: unable to ioremap register range\n", __func__); |
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return; |
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} |
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/* Clear all interrupt requests */ |
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0); |
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1); |
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0); |
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1); |
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/* Disable all interrupts */ |
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davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG0); |
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davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG1); |
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/* Interrupts disabled immediately, IRQ entry reflects all */ |
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davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_INCTL_REG); |
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/* we don't use the hardware vector table, just its entry addresses */ |
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davinci_aintc_writel(0, DAVINCI_AINTC_IRQ_EABASE_REG); |
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/* Clear all interrupt requests */ |
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0); |
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1); |
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0); |
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davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1); |
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prios = config->prios; |
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for (reg_off = DAVINCI_AINTC_IRQ_INTPRI0_REG; |
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reg_off <= DAVINCI_AINTC_IRQ_INTPRI7_REG; reg_off += 4) { |
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for (shift = 0, prio = 0; shift < 32; shift += 4, prios++) |
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prio |= (*prios & 0x07) << shift; |
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davinci_aintc_writel(prio, reg_off); |
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} |
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irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0); |
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if (irq_base < 0) { |
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pr_err("%s: unable to allocate interrupt descriptors: %d\n", |
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__func__, irq_base); |
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return; |
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} |
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davinci_aintc_irq_domain = irq_domain_add_legacy(NULL, |
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config->num_irqs, irq_base, 0, |
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&irq_domain_simple_ops, NULL); |
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if (!davinci_aintc_irq_domain) { |
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pr_err("%s: unable to create interrupt domain\n", __func__); |
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return; |
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} |
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ret = irq_alloc_domain_generic_chips(davinci_aintc_irq_domain, 32, 1, |
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"AINTC", handle_edge_irq, |
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IRQ_NOREQUEST | IRQ_NOPROBE, 0, 0); |
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if (ret) { |
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pr_err("%s: unable to allocate generic irq chips for domain\n", |
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__func__); |
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return; |
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} |
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for (irq_off = 0, reg_off = 0; |
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irq_off < config->num_irqs; |
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irq_off += 32, reg_off += 0x04) |
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davinci_aintc_setup_gc(davinci_aintc_base + reg_off, |
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irq_base + irq_off, 32); |
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set_handle_irq(davinci_aintc_handle_irq); |
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}
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