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274 lines
7.0 KiB
274 lines
7.0 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* omap iommu: main structures |
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* |
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* Copyright (C) 2008-2009 Nokia Corporation |
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* |
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* Written by Hiroshi DOYU <[email protected]> |
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*/ |
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#ifndef _OMAP_IOMMU_H |
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#define _OMAP_IOMMU_H |
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#include <linux/bitops.h> |
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#include <linux/iommu.h> |
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#define for_each_iotlb_cr(obj, n, __i, cr) \ |
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for (__i = 0; \ |
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(__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \ |
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__i++) |
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struct iotlb_entry { |
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u32 da; |
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u32 pa; |
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u32 pgsz, prsvd, valid; |
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u32 endian, elsz, mixed; |
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}; |
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/** |
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* struct omap_iommu_device - omap iommu device data |
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* @pgtable: page table used by an omap iommu attached to a domain |
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* @iommu_dev: pointer to store an omap iommu instance attached to a domain |
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*/ |
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struct omap_iommu_device { |
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u32 *pgtable; |
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struct omap_iommu *iommu_dev; |
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}; |
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/** |
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* struct omap_iommu_domain - omap iommu domain |
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* @num_iommus: number of iommus in this domain |
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* @iommus: omap iommu device data for all iommus in this domain |
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* @dev: Device using this domain. |
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* @lock: domain lock, should be taken when attaching/detaching |
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* @domain: generic domain handle used by iommu core code |
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*/ |
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struct omap_iommu_domain { |
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u32 num_iommus; |
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struct omap_iommu_device *iommus; |
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struct device *dev; |
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spinlock_t lock; |
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struct iommu_domain domain; |
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}; |
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struct omap_iommu { |
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const char *name; |
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void __iomem *regbase; |
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struct regmap *syscfg; |
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struct device *dev; |
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struct iommu_domain *domain; |
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struct dentry *debug_dir; |
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spinlock_t iommu_lock; /* global for this whole object */ |
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/* |
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* We don't change iopgd for a situation like pgd for a task, |
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* but share it globally for each iommu. |
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*/ |
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u32 *iopgd; |
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spinlock_t page_table_lock; /* protect iopgd */ |
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dma_addr_t pd_dma; |
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int nr_tlb_entries; |
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void *ctx; /* iommu context: registres saved area */ |
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struct cr_regs *cr_ctx; |
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u32 num_cr_ctx; |
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int has_bus_err_back; |
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u32 id; |
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struct iommu_device iommu; |
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struct iommu_group *group; |
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u8 pwrst; |
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}; |
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/** |
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* struct omap_iommu_arch_data - omap iommu private data |
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* @iommu_dev: handle of the OMAP iommu device |
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* @dev: handle of the iommu device |
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* |
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* This is an omap iommu private data object, which binds an iommu user |
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* to its iommu device. This object should be placed at the iommu user's |
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* dev_archdata so generic IOMMU API can be used without having to |
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* utilize omap-specific plumbing anymore. |
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*/ |
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struct omap_iommu_arch_data { |
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struct omap_iommu *iommu_dev; |
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struct device *dev; |
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}; |
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struct cr_regs { |
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u32 cam; |
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u32 ram; |
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}; |
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struct iotlb_lock { |
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short base; |
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short vict; |
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}; |
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/* |
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* MMU Register offsets |
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*/ |
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#define MMU_REVISION 0x00 |
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#define MMU_IRQSTATUS 0x18 |
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#define MMU_IRQENABLE 0x1c |
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#define MMU_WALKING_ST 0x40 |
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#define MMU_CNTL 0x44 |
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#define MMU_FAULT_AD 0x48 |
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#define MMU_TTB 0x4c |
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#define MMU_LOCK 0x50 |
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#define MMU_LD_TLB 0x54 |
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#define MMU_CAM 0x58 |
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#define MMU_RAM 0x5c |
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#define MMU_GFLUSH 0x60 |
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#define MMU_FLUSH_ENTRY 0x64 |
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#define MMU_READ_CAM 0x68 |
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#define MMU_READ_RAM 0x6c |
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#define MMU_EMU_FAULT_AD 0x70 |
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#define MMU_GP_REG 0x88 |
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#define MMU_REG_SIZE 256 |
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/* |
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* MMU Register bit definitions |
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*/ |
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/* IRQSTATUS & IRQENABLE */ |
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#define MMU_IRQ_MULTIHITFAULT BIT(4) |
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#define MMU_IRQ_TABLEWALKFAULT BIT(3) |
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#define MMU_IRQ_EMUMISS BIT(2) |
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#define MMU_IRQ_TRANSLATIONFAULT BIT(1) |
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#define MMU_IRQ_TLBMISS BIT(0) |
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#define __MMU_IRQ_FAULT \ |
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(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT) |
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#define MMU_IRQ_MASK \ |
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(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS) |
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#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT) |
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#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS) |
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/* MMU_CNTL */ |
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#define MMU_CNTL_SHIFT 1 |
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#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT) |
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#define MMU_CNTL_EML_TLB BIT(3) |
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#define MMU_CNTL_TWL_EN BIT(2) |
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#define MMU_CNTL_MMU_EN BIT(1) |
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/* CAM */ |
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#define MMU_CAM_VATAG_SHIFT 12 |
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#define MMU_CAM_VATAG_MASK \ |
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((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT) |
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#define MMU_CAM_P BIT(3) |
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#define MMU_CAM_V BIT(2) |
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#define MMU_CAM_PGSZ_MASK 3 |
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#define MMU_CAM_PGSZ_1M (0 << 0) |
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#define MMU_CAM_PGSZ_64K (1 << 0) |
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#define MMU_CAM_PGSZ_4K (2 << 0) |
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#define MMU_CAM_PGSZ_16M (3 << 0) |
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/* RAM */ |
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#define MMU_RAM_PADDR_SHIFT 12 |
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#define MMU_RAM_PADDR_MASK \ |
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((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT) |
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#define MMU_RAM_ENDIAN_SHIFT 9 |
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#define MMU_RAM_ENDIAN_MASK BIT(MMU_RAM_ENDIAN_SHIFT) |
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#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT) |
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#define MMU_RAM_ENDIAN_BIG BIT(MMU_RAM_ENDIAN_SHIFT) |
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#define MMU_RAM_ELSZ_SHIFT 7 |
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#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT) |
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#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT) |
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#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT) |
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#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT) |
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#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT) |
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#define MMU_RAM_MIXED_SHIFT 6 |
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#define MMU_RAM_MIXED_MASK BIT(MMU_RAM_MIXED_SHIFT) |
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#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK |
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#define MMU_GP_REG_BUS_ERR_BACK_EN 0x1 |
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#define get_cam_va_mask(pgsz) \ |
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(((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \ |
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((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \ |
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((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ |
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((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) |
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/* |
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* DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP) |
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*/ |
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#define DSP_SYS_REVISION 0x00 |
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#define DSP_SYS_MMU_CONFIG 0x18 |
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#define DSP_SYS_MMU_CONFIG_EN_SHIFT 4 |
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/* |
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* utilities for super page(16MB, 1MB, 64KB and 4KB) |
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*/ |
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#define iopgsz_max(bytes) \ |
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(((bytes) >= SZ_16M) ? SZ_16M : \ |
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((bytes) >= SZ_1M) ? SZ_1M : \ |
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((bytes) >= SZ_64K) ? SZ_64K : \ |
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((bytes) >= SZ_4K) ? SZ_4K : 0) |
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#define bytes_to_iopgsz(bytes) \ |
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(((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \ |
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((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \ |
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((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \ |
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((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1) |
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#define iopgsz_to_bytes(iopgsz) \ |
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(((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \ |
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((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \ |
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((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \ |
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((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0) |
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#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0) |
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/* |
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* global functions |
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*/ |
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struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n); |
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void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l); |
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void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l); |
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#ifdef CONFIG_OMAP_IOMMU_DEBUG |
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void omap_iommu_debugfs_init(void); |
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void omap_iommu_debugfs_exit(void); |
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void omap_iommu_debugfs_add(struct omap_iommu *obj); |
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void omap_iommu_debugfs_remove(struct omap_iommu *obj); |
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#else |
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static inline void omap_iommu_debugfs_init(void) { } |
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static inline void omap_iommu_debugfs_exit(void) { } |
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static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { } |
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static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { } |
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#endif |
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/* |
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* register accessors |
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*/ |
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static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs) |
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{ |
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return __raw_readl(obj->regbase + offs); |
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} |
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static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs) |
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{ |
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__raw_writel(val, obj->regbase + offs); |
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} |
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static inline int iotlb_cr_valid(struct cr_regs *cr) |
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{ |
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if (!cr) |
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return -EINVAL; |
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return cr->cam & MMU_CAM_V; |
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} |
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#endif /* _OMAP_IOMMU_H */
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