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343 lines
9.9 KiB
343 lines
9.9 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04 |
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* IDE driver for Linux. |
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* |
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* Copyright (c) 2000-2002 Vojtech Pavlik |
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* Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz |
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* |
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* Based on the work of: |
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* Andre Hedrick |
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*/ |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/ide.h> |
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#define DRV_NAME "amd74xx" |
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enum { |
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AMD_IDE_CONFIG = 0x41, |
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AMD_CABLE_DETECT = 0x42, |
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AMD_DRIVE_TIMING = 0x48, |
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AMD_8BIT_TIMING = 0x4e, |
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AMD_ADDRESS_SETUP = 0x4c, |
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AMD_UDMA_TIMING = 0x50, |
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}; |
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static unsigned int amd_80w; |
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static unsigned int amd_clock; |
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static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" }; |
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static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 }; |
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static inline u8 amd_offset(struct pci_dev *dev) |
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{ |
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return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0; |
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} |
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/* |
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* amd_set_speed() writes timing values to the chipset registers |
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*/ |
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static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask, |
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struct ide_timing *timing) |
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{ |
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u8 t = 0, offset = amd_offset(dev); |
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pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t); |
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t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); |
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pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t); |
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pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)), |
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((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); |
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pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn), |
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((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); |
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switch (udma_mask) { |
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case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; |
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case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break; |
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case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break; |
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case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break; |
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default: return; |
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} |
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if (timing->udma) |
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pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + 3 - dn, t); |
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} |
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/* |
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* amd_set_drive() computes timing values and configures the chipset |
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* to a desired transfer mode. It also can be called by upper layers. |
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*/ |
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static void amd_set_drive(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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ide_drive_t *peer = ide_get_pair_dev(drive); |
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struct ide_timing t, p; |
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int T, UT; |
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u8 udma_mask = hwif->ultra_mask; |
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const u8 speed = drive->dma_mode; |
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T = 1000000000 / amd_clock; |
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UT = (udma_mask == ATA_UDMA2) ? T : (T / 2); |
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ide_timing_compute(drive, speed, &t, T, UT); |
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if (peer) { |
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ide_timing_compute(peer, peer->pio_mode, &p, T, UT); |
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ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); |
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} |
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if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1; |
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if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15; |
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amd_set_speed(dev, drive->dn, udma_mask, &t); |
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} |
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/* |
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* amd_set_pio_mode() is a callback from upper layers for PIO-only tuning. |
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*/ |
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static void amd_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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drive->dma_mode = drive->pio_mode; |
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amd_set_drive(hwif, drive); |
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} |
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static void amd7409_cable_detect(struct pci_dev *dev) |
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{ |
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/* no host side cable detection */ |
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amd_80w = 0x03; |
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} |
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static void amd7411_cable_detect(struct pci_dev *dev) |
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{ |
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int i; |
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u32 u = 0; |
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u8 t = 0, offset = amd_offset(dev); |
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pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t); |
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pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u); |
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amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0); |
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for (i = 24; i >= 0; i -= 8) |
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if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) { |
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printk(KERN_WARNING DRV_NAME " %s: BIOS didn't set " |
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"cable bits correctly. Enabling workaround.\n", |
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pci_name(dev)); |
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amd_80w |= (1 << (1 - (i >> 4))); |
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} |
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} |
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/* |
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* The initialization callback. Initialize drive independent registers. |
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*/ |
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static int init_chipset_amd74xx(struct pci_dev *dev) |
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{ |
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u8 t = 0, offset = amd_offset(dev); |
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/* |
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* Check 80-wire cable presence. |
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*/ |
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if (dev->vendor == PCI_VENDOR_ID_AMD && |
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dev->device == PCI_DEVICE_ID_AMD_COBRA_7401) |
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; /* no UDMA > 2 */ |
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else if (dev->vendor == PCI_VENDOR_ID_AMD && |
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dev->device == PCI_DEVICE_ID_AMD_VIPER_7409) |
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amd7409_cable_detect(dev); |
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else |
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amd7411_cable_detect(dev); |
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/* |
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* Take care of prefetch & postwrite. |
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*/ |
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pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t); |
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/* |
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* Check for broken FIFO support. |
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*/ |
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if (dev->vendor == PCI_VENDOR_ID_AMD && |
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dev->device == PCI_DEVICE_ID_AMD_VIPER_7411) |
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t &= 0x0f; |
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else |
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t |= 0xf0; |
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pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t); |
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return 0; |
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} |
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static u8 amd_cable_detect(ide_hwif_t *hwif) |
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{ |
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if ((amd_80w >> hwif->channel) & 1) |
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return ATA_CBL_PATA80; |
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else |
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return ATA_CBL_PATA40; |
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} |
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static const struct ide_port_ops amd_port_ops = { |
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.set_pio_mode = amd_set_pio_mode, |
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.set_dma_mode = amd_set_drive, |
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.cable_detect = amd_cable_detect, |
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}; |
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#define IDE_HFLAGS_AMD \ |
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(IDE_HFLAG_PIO_NO_BLACKLIST | \ |
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IDE_HFLAG_POST_SET_MODE | \ |
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IDE_HFLAG_IO_32BIT | \ |
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IDE_HFLAG_UNMASK_IRQS) |
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#define DECLARE_AMD_DEV(swdma, udma) \ |
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{ \ |
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.name = DRV_NAME, \ |
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.init_chipset = init_chipset_amd74xx, \ |
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.enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \ |
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.port_ops = &amd_port_ops, \ |
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.host_flags = IDE_HFLAGS_AMD, \ |
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.pio_mask = ATA_PIO5, \ |
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.swdma_mask = swdma, \ |
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.mwdma_mask = ATA_MWDMA2, \ |
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.udma_mask = udma, \ |
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} |
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#define DECLARE_NV_DEV(udma) \ |
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{ \ |
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.name = DRV_NAME, \ |
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.init_chipset = init_chipset_amd74xx, \ |
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.enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \ |
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.port_ops = &amd_port_ops, \ |
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.host_flags = IDE_HFLAGS_AMD, \ |
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.pio_mask = ATA_PIO5, \ |
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.swdma_mask = ATA_SWDMA2, \ |
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.mwdma_mask = ATA_MWDMA2, \ |
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.udma_mask = udma, \ |
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} |
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static const struct ide_port_info amd74xx_chipsets[] = { |
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/* 0: AMD7401 */ DECLARE_AMD_DEV(0x00, ATA_UDMA2), |
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/* 1: AMD7409 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA4), |
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/* 2: AMD7411/7441 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5), |
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/* 3: AMD8111 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA6), |
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/* 4: NFORCE */ DECLARE_NV_DEV(ATA_UDMA5), |
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/* 5: >= NFORCE2 */ DECLARE_NV_DEV(ATA_UDMA6), |
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/* 6: AMD5536 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5), |
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}; |
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static int amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id) |
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{ |
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struct ide_port_info d; |
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u8 idx = id->driver_data; |
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d = amd74xx_chipsets[idx]; |
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/* |
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* Check for bad SWDMA and incorrectly wired Serenade mainboards. |
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*/ |
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if (idx == 1) { |
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if (dev->revision <= 7) |
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d.swdma_mask = 0; |
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d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX; |
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} else if (idx == 3) { |
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if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD && |
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dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE) |
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d.udma_mask = ATA_UDMA5; |
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} |
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/* |
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* It seems that on some nVidia controllers using AltStatus |
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* register can be unreliable so default to Status register |
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* if the device is in Compatibility Mode. |
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*/ |
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if (dev->vendor == PCI_VENDOR_ID_NVIDIA && |
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ide_pci_is_in_compatibility_mode(dev)) |
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d.host_flags |= IDE_HFLAG_BROKEN_ALTSTATUS; |
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printk(KERN_INFO "%s %s: UDMA%s controller\n", |
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d.name, pci_name(dev), amd_dma[fls(d.udma_mask) - 1]); |
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/* |
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* Determine the system bus clock. |
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*/ |
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amd_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000; |
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switch (amd_clock) { |
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case 33000: amd_clock = 33333; break; |
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case 37000: amd_clock = 37500; break; |
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case 41000: amd_clock = 41666; break; |
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} |
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if (amd_clock < 20000 || amd_clock > 50000) { |
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printk(KERN_WARNING "%s: User given PCI clock speed impossible" |
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" (%d), using 33 MHz instead.\n", |
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d.name, amd_clock); |
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amd_clock = 33333; |
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} |
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return ide_pci_init_one(dev, &d, NULL); |
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} |
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static const struct pci_device_id amd74xx_pci_tbl[] = { |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 2 }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 3 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 4 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 5 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 5 }, |
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#ifdef CONFIG_BLK_DEV_IDE_SATA |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 5 }, |
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#endif |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 5 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 5 }, |
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#ifdef CONFIG_BLK_DEV_IDE_SATA |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 5 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 5 }, |
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#endif |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 5 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 5 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 5 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 5 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 5 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 5 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 5 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 5 }, |
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{ PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 5 }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 6 }, |
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{ 0, }, |
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}; |
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MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl); |
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static struct pci_driver amd74xx_pci_driver = { |
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.name = "AMD_IDE", |
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.id_table = amd74xx_pci_tbl, |
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.probe = amd74xx_probe, |
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.remove = ide_pci_remove, |
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.suspend = ide_pci_suspend, |
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.resume = ide_pci_resume, |
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}; |
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static int __init amd74xx_ide_init(void) |
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{ |
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return ide_pci_register_driver(&amd74xx_pci_driver); |
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} |
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static void __exit amd74xx_ide_exit(void) |
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{ |
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pci_unregister_driver(&amd74xx_pci_driver); |
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} |
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module_init(amd74xx_ide_init); |
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module_exit(amd74xx_ide_exit); |
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MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz"); |
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MODULE_DESCRIPTION("AMD PCI IDE driver"); |
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MODULE_LICENSE("GPL");
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