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939 lines
25 KiB
939 lines
25 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* i2c-xiic.c |
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* Copyright (c) 2002-2007 Xilinx Inc. |
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* Copyright (c) 2009-2010 Intel Corporation |
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* |
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* This code was implemented by Mocean Laboratories AB when porting linux |
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* to the automotive development board Russellville. The copyright holder |
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* as seen in the header is Intel corporation. |
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* Mocean Laboratories forked off the GNU/Linux platform work into a |
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* separate company called Pelagicore AB, which committed the code to the |
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* kernel. |
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*/ |
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|
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/* Supports: |
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* Xilinx IIC |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/errno.h> |
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#include <linux/err.h> |
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#include <linux/delay.h> |
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#include <linux/platform_device.h> |
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#include <linux/i2c.h> |
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#include <linux/interrupt.h> |
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#include <linux/wait.h> |
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#include <linux/platform_data/i2c-xiic.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/of.h> |
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#include <linux/clk.h> |
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#include <linux/pm_runtime.h> |
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#define DRIVER_NAME "xiic-i2c" |
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|
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enum xilinx_i2c_state { |
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STATE_DONE, |
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STATE_ERROR, |
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STATE_START |
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}; |
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|
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enum xiic_endian { |
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LITTLE, |
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BIG |
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}; |
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/** |
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* struct xiic_i2c - Internal representation of the XIIC I2C bus |
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* @dev: Pointer to device structure |
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* @base: Memory base of the HW registers |
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* @wait: Wait queue for callers |
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* @adap: Kernel adapter representation |
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* @tx_msg: Messages from above to be sent |
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* @lock: Mutual exclusion |
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* @tx_pos: Current pos in TX message |
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* @nmsgs: Number of messages in tx_msg |
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* @rx_msg: Current RX message |
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* @rx_pos: Position within current RX message |
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* @endianness: big/little-endian byte order |
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* @clk: Pointer to AXI4-lite input clock |
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* @state: See STATE_ |
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* @singlemaster: Indicates bus is single master |
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*/ |
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struct xiic_i2c { |
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struct device *dev; |
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void __iomem *base; |
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wait_queue_head_t wait; |
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struct i2c_adapter adap; |
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struct i2c_msg *tx_msg; |
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struct mutex lock; |
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unsigned int tx_pos; |
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unsigned int nmsgs; |
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struct i2c_msg *rx_msg; |
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int rx_pos; |
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enum xiic_endian endianness; |
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struct clk *clk; |
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enum xilinx_i2c_state state; |
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bool singlemaster; |
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}; |
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#define XIIC_MSB_OFFSET 0 |
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#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) |
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|
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/* |
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* Register offsets in bytes from RegisterBase. Three is added to the |
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* base offset to access LSB (IBM style) of the word |
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*/ |
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#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ |
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#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ |
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#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ |
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#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ |
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#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ |
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#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ |
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#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ |
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#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ |
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#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ |
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#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ |
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|
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/* Control Register masks */ |
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#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ |
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#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ |
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#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ |
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#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ |
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#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ |
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#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ |
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#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ |
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|
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/* Status Register masks */ |
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#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ |
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#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ |
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#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ |
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#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ |
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#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ |
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#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ |
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#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ |
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#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ |
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|
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/* Interrupt Status Register masks Interrupt occurs when... */ |
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#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ |
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#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ |
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#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ |
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#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ |
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#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ |
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#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ |
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#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ |
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#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ |
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|
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/* The following constants specify the depth of the FIFOs */ |
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#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ |
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#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ |
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|
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/* The following constants specify groups of interrupts that are typically |
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* enabled or disables at the same time |
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*/ |
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#define XIIC_TX_INTERRUPTS \ |
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(XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) |
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|
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#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) |
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|
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/* |
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* Tx Fifo upper bit masks. |
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*/ |
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#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ |
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#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ |
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/* |
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* The following constants define the register offsets for the Interrupt |
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* registers. There are some holes in the memory map for reserved addresses |
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* to allow other registers to be added and still match the memory map of the |
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* interrupt controller registers |
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*/ |
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#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ |
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#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ |
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#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ |
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#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ |
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#define XIIC_RESET_MASK 0xAUL |
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|
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#define XIIC_PM_TIMEOUT 1000 /* ms */ |
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/* timeout waiting for the controller to respond */ |
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#define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) |
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/* |
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* The following constant is used for the device global interrupt enable |
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* register, to enable all interrupts for the device, this is the only bit |
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* in the register |
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*/ |
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#define XIIC_GINTR_ENABLE_MASK 0x80000000UL |
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#define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) |
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#define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) |
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static int xiic_start_xfer(struct xiic_i2c *i2c); |
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static void __xiic_start_xfer(struct xiic_i2c *i2c); |
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|
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/* |
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* For the register read and write functions, a little-endian and big-endian |
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* version are necessary. Endianness is detected during the probe function. |
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* Only the least significant byte [doublet] of the register are ever |
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* accessed. This requires an offset of 3 [2] from the base address for |
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* big-endian systems. |
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*/ |
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static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) |
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{ |
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if (i2c->endianness == LITTLE) |
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iowrite8(value, i2c->base + reg); |
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else |
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iowrite8(value, i2c->base + reg + 3); |
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} |
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static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) |
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{ |
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u8 ret; |
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if (i2c->endianness == LITTLE) |
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ret = ioread8(i2c->base + reg); |
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else |
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ret = ioread8(i2c->base + reg + 3); |
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return ret; |
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} |
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static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) |
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{ |
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if (i2c->endianness == LITTLE) |
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iowrite16(value, i2c->base + reg); |
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else |
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iowrite16be(value, i2c->base + reg + 2); |
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} |
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static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) |
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{ |
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if (i2c->endianness == LITTLE) |
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iowrite32(value, i2c->base + reg); |
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else |
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iowrite32be(value, i2c->base + reg); |
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} |
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static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) |
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{ |
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u32 ret; |
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if (i2c->endianness == LITTLE) |
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ret = ioread32(i2c->base + reg); |
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else |
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ret = ioread32be(i2c->base + reg); |
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return ret; |
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} |
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static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) |
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{ |
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u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); |
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xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); |
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} |
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static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) |
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{ |
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u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); |
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xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); |
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} |
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static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) |
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{ |
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u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); |
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xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); |
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} |
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static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) |
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{ |
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xiic_irq_clr(i2c, mask); |
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xiic_irq_en(i2c, mask); |
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} |
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static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) |
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{ |
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u8 sr; |
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unsigned long timeout; |
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timeout = jiffies + XIIC_I2C_TIMEOUT; |
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for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); |
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!(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); |
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sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { |
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xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); |
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if (time_after(jiffies, timeout)) { |
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dev_err(i2c->dev, "Failed to clear rx fifo\n"); |
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return -ETIMEDOUT; |
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} |
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} |
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return 0; |
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} |
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static int xiic_reinit(struct xiic_i2c *i2c) |
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{ |
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int ret; |
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xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); |
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/* Set receive Fifo depth to maximum (zero based). */ |
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xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); |
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/* Reset Tx Fifo. */ |
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xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); |
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/* Enable IIC Device, remove Tx Fifo reset & disable general call. */ |
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xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); |
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/* make sure RX fifo is empty */ |
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ret = xiic_clear_rx_fifo(i2c); |
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if (ret) |
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return ret; |
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/* Enable interrupts */ |
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xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); |
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xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); |
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return 0; |
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} |
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static void xiic_deinit(struct xiic_i2c *i2c) |
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{ |
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u8 cr; |
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xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); |
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/* Disable IIC Device. */ |
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cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); |
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xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); |
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} |
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static void xiic_read_rx(struct xiic_i2c *i2c) |
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{ |
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u8 bytes_in_fifo; |
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int i; |
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bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; |
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dev_dbg(i2c->adap.dev.parent, |
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"%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", |
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__func__, bytes_in_fifo, xiic_rx_space(i2c), |
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xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), |
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xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); |
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if (bytes_in_fifo > xiic_rx_space(i2c)) |
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bytes_in_fifo = xiic_rx_space(i2c); |
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for (i = 0; i < bytes_in_fifo; i++) |
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i2c->rx_msg->buf[i2c->rx_pos++] = |
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xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); |
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xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, |
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(xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? |
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IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); |
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} |
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static int xiic_tx_fifo_space(struct xiic_i2c *i2c) |
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{ |
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/* return the actual space left in the FIFO */ |
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return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; |
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} |
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static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) |
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{ |
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u8 fifo_space = xiic_tx_fifo_space(i2c); |
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int len = xiic_tx_space(i2c); |
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len = (len > fifo_space) ? fifo_space : len; |
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dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", |
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__func__, len, fifo_space); |
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|
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while (len--) { |
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u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; |
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if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { |
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/* last message in transfer -> STOP */ |
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data |= XIIC_TX_DYN_STOP_MASK; |
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dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); |
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} |
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xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); |
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} |
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} |
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|
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static void xiic_wakeup(struct xiic_i2c *i2c, int code) |
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{ |
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i2c->tx_msg = NULL; |
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i2c->rx_msg = NULL; |
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i2c->nmsgs = 0; |
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i2c->state = code; |
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wake_up(&i2c->wait); |
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} |
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|
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static irqreturn_t xiic_process(int irq, void *dev_id) |
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{ |
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struct xiic_i2c *i2c = dev_id; |
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u32 pend, isr, ier; |
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u32 clr = 0; |
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|
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/* Get the interrupt Status from the IPIF. There is no clearing of |
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* interrupts in the IPIF. Interrupts must be cleared at the source. |
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* To find which interrupts are pending; AND interrupts pending with |
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* interrupts masked. |
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*/ |
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mutex_lock(&i2c->lock); |
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isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); |
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ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); |
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pend = isr & ier; |
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|
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dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", |
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__func__, ier, isr, pend); |
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dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", |
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__func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), |
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i2c->tx_msg, i2c->nmsgs); |
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|
|
|
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/* Service requesting interrupt */ |
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if ((pend & XIIC_INTR_ARB_LOST_MASK) || |
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((pend & XIIC_INTR_TX_ERROR_MASK) && |
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!(pend & XIIC_INTR_RX_FULL_MASK))) { |
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/* bus arbritration lost, or... |
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* Transmit error _OR_ RX completed |
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* if this happens when RX_FULL is not set |
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* this is probably a TX error |
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*/ |
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|
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dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); |
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|
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/* dynamic mode seem to suffer from problems if we just flushes |
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* fifos and the next message is a TX with len 0 (only addr) |
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* reset the IP instead of just flush fifos |
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*/ |
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xiic_reinit(i2c); |
|
|
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if (i2c->rx_msg) |
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xiic_wakeup(i2c, STATE_ERROR); |
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if (i2c->tx_msg) |
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xiic_wakeup(i2c, STATE_ERROR); |
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} |
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if (pend & XIIC_INTR_RX_FULL_MASK) { |
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/* Receive register/FIFO is full */ |
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|
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clr |= XIIC_INTR_RX_FULL_MASK; |
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if (!i2c->rx_msg) { |
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dev_dbg(i2c->adap.dev.parent, |
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"%s unexpected RX IRQ\n", __func__); |
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xiic_clear_rx_fifo(i2c); |
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goto out; |
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} |
|
|
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xiic_read_rx(i2c); |
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if (xiic_rx_space(i2c) == 0) { |
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/* this is the last part of the message */ |
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i2c->rx_msg = NULL; |
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|
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/* also clear TX error if there (RX complete) */ |
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clr |= (isr & XIIC_INTR_TX_ERROR_MASK); |
|
|
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dev_dbg(i2c->adap.dev.parent, |
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"%s end of message, nmsgs: %d\n", |
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__func__, i2c->nmsgs); |
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|
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/* send next message if this wasn't the last, |
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* otherwise the transfer will be finialise when |
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* receiving the bus not busy interrupt |
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*/ |
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if (i2c->nmsgs > 1) { |
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i2c->nmsgs--; |
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i2c->tx_msg++; |
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dev_dbg(i2c->adap.dev.parent, |
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"%s will start next...\n", __func__); |
|
|
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__xiic_start_xfer(i2c); |
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} |
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} |
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} |
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if (pend & XIIC_INTR_BNB_MASK) { |
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/* IIC bus has transitioned to not busy */ |
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clr |= XIIC_INTR_BNB_MASK; |
|
|
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/* The bus is not busy, disable BusNotBusy interrupt */ |
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xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); |
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|
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if (!i2c->tx_msg) |
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goto out; |
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|
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if ((i2c->nmsgs == 1) && !i2c->rx_msg && |
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xiic_tx_space(i2c) == 0) |
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xiic_wakeup(i2c, STATE_DONE); |
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else |
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xiic_wakeup(i2c, STATE_ERROR); |
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} |
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if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { |
|
/* Transmit register/FIFO is empty or ½ empty */ |
|
|
|
clr |= (pend & |
|
(XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); |
|
|
|
if (!i2c->tx_msg) { |
|
dev_dbg(i2c->adap.dev.parent, |
|
"%s unexpected TX IRQ\n", __func__); |
|
goto out; |
|
} |
|
|
|
xiic_fill_tx_fifo(i2c); |
|
|
|
/* current message sent and there is space in the fifo */ |
|
if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { |
|
dev_dbg(i2c->adap.dev.parent, |
|
"%s end of message sent, nmsgs: %d\n", |
|
__func__, i2c->nmsgs); |
|
if (i2c->nmsgs > 1) { |
|
i2c->nmsgs--; |
|
i2c->tx_msg++; |
|
__xiic_start_xfer(i2c); |
|
} else { |
|
xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); |
|
|
|
dev_dbg(i2c->adap.dev.parent, |
|
"%s Got TX IRQ but no more to do...\n", |
|
__func__); |
|
} |
|
} else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) |
|
/* current frame is sent and is last, |
|
* make sure to disable tx half |
|
*/ |
|
xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); |
|
} |
|
out: |
|
dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); |
|
|
|
xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); |
|
mutex_unlock(&i2c->lock); |
|
return IRQ_HANDLED; |
|
} |
|
|
|
static int xiic_bus_busy(struct xiic_i2c *i2c) |
|
{ |
|
u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); |
|
|
|
return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; |
|
} |
|
|
|
static int xiic_busy(struct xiic_i2c *i2c) |
|
{ |
|
int tries = 3; |
|
int err; |
|
|
|
if (i2c->tx_msg) |
|
return -EBUSY; |
|
|
|
/* In single master mode bus can only be busy, when in use by this |
|
* driver. If the register indicates bus being busy for some reason we |
|
* should ignore it, since bus will never be released and i2c will be |
|
* stuck forever. |
|
*/ |
|
if (i2c->singlemaster) { |
|
return 0; |
|
} |
|
|
|
/* for instance if previous transfer was terminated due to TX error |
|
* it might be that the bus is on it's way to become available |
|
* give it at most 3 ms to wake |
|
*/ |
|
err = xiic_bus_busy(i2c); |
|
while (err && tries--) { |
|
msleep(1); |
|
err = xiic_bus_busy(i2c); |
|
} |
|
|
|
return err; |
|
} |
|
|
|
static void xiic_start_recv(struct xiic_i2c *i2c) |
|
{ |
|
u8 rx_watermark; |
|
struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; |
|
unsigned long flags; |
|
|
|
/* Clear and enable Rx full interrupt. */ |
|
xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); |
|
|
|
/* we want to get all but last byte, because the TX_ERROR IRQ is used |
|
* to inidicate error ACK on the address, and negative ack on the last |
|
* received byte, so to not mix them receive all but last. |
|
* In the case where there is only one byte to receive |
|
* we can check if ERROR and RX full is set at the same time |
|
*/ |
|
rx_watermark = msg->len; |
|
if (rx_watermark > IIC_RX_FIFO_DEPTH) |
|
rx_watermark = IIC_RX_FIFO_DEPTH; |
|
xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); |
|
|
|
local_irq_save(flags); |
|
if (!(msg->flags & I2C_M_NOSTART)) |
|
/* write the address */ |
|
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, |
|
i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK); |
|
|
|
xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); |
|
|
|
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, |
|
msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); |
|
local_irq_restore(flags); |
|
|
|
if (i2c->nmsgs == 1) |
|
/* very last, enable bus not busy as well */ |
|
xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); |
|
|
|
/* the message is tx:ed */ |
|
i2c->tx_pos = msg->len; |
|
} |
|
|
|
static void xiic_start_send(struct xiic_i2c *i2c) |
|
{ |
|
struct i2c_msg *msg = i2c->tx_msg; |
|
|
|
xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); |
|
|
|
dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", |
|
__func__, msg, msg->len); |
|
dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", |
|
__func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), |
|
xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); |
|
|
|
if (!(msg->flags & I2C_M_NOSTART)) { |
|
/* write the address */ |
|
u16 data = i2c_8bit_addr_from_msg(msg) | |
|
XIIC_TX_DYN_START_MASK; |
|
if ((i2c->nmsgs == 1) && msg->len == 0) |
|
/* no data and last message -> add STOP */ |
|
data |= XIIC_TX_DYN_STOP_MASK; |
|
|
|
xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); |
|
} |
|
|
|
xiic_fill_tx_fifo(i2c); |
|
|
|
/* Clear any pending Tx empty, Tx Error and then enable them. */ |
|
xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | |
|
XIIC_INTR_BNB_MASK); |
|
} |
|
|
|
static irqreturn_t xiic_isr(int irq, void *dev_id) |
|
{ |
|
struct xiic_i2c *i2c = dev_id; |
|
u32 pend, isr, ier; |
|
irqreturn_t ret = IRQ_NONE; |
|
/* Do not processes a devices interrupts if the device has no |
|
* interrupts pending |
|
*/ |
|
|
|
dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); |
|
|
|
isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); |
|
ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); |
|
pend = isr & ier; |
|
if (pend) |
|
ret = IRQ_WAKE_THREAD; |
|
|
|
return ret; |
|
} |
|
|
|
static void __xiic_start_xfer(struct xiic_i2c *i2c) |
|
{ |
|
int first = 1; |
|
int fifo_space = xiic_tx_fifo_space(i2c); |
|
dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", |
|
__func__, i2c->tx_msg, fifo_space); |
|
|
|
if (!i2c->tx_msg) |
|
return; |
|
|
|
i2c->rx_pos = 0; |
|
i2c->tx_pos = 0; |
|
i2c->state = STATE_START; |
|
while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) { |
|
if (!first) { |
|
i2c->nmsgs--; |
|
i2c->tx_msg++; |
|
i2c->tx_pos = 0; |
|
} else |
|
first = 0; |
|
|
|
if (i2c->tx_msg->flags & I2C_M_RD) { |
|
/* we dont date putting several reads in the FIFO */ |
|
xiic_start_recv(i2c); |
|
return; |
|
} else { |
|
xiic_start_send(i2c); |
|
if (xiic_tx_space(i2c) != 0) { |
|
/* the message could not be completely sent */ |
|
break; |
|
} |
|
} |
|
|
|
fifo_space = xiic_tx_fifo_space(i2c); |
|
} |
|
|
|
/* there are more messages or the current one could not be completely |
|
* put into the FIFO, also enable the half empty interrupt |
|
*/ |
|
if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) |
|
xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); |
|
|
|
} |
|
|
|
static int xiic_start_xfer(struct xiic_i2c *i2c) |
|
{ |
|
int ret; |
|
mutex_lock(&i2c->lock); |
|
|
|
ret = xiic_reinit(i2c); |
|
if (!ret) |
|
__xiic_start_xfer(i2c); |
|
|
|
mutex_unlock(&i2c->lock); |
|
|
|
return ret; |
|
} |
|
|
|
static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) |
|
{ |
|
struct xiic_i2c *i2c = i2c_get_adapdata(adap); |
|
int err; |
|
|
|
dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, |
|
xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); |
|
|
|
err = pm_runtime_resume_and_get(i2c->dev); |
|
if (err < 0) |
|
return err; |
|
|
|
err = xiic_busy(i2c); |
|
if (err) |
|
goto out; |
|
|
|
i2c->tx_msg = msgs; |
|
i2c->nmsgs = num; |
|
|
|
err = xiic_start_xfer(i2c); |
|
if (err < 0) { |
|
dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); |
|
goto out; |
|
} |
|
|
|
if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || |
|
(i2c->state == STATE_DONE), HZ)) { |
|
err = (i2c->state == STATE_DONE) ? num : -EIO; |
|
goto out; |
|
} else { |
|
i2c->tx_msg = NULL; |
|
i2c->rx_msg = NULL; |
|
i2c->nmsgs = 0; |
|
err = -ETIMEDOUT; |
|
goto out; |
|
} |
|
out: |
|
pm_runtime_mark_last_busy(i2c->dev); |
|
pm_runtime_put_autosuspend(i2c->dev); |
|
return err; |
|
} |
|
|
|
static u32 xiic_func(struct i2c_adapter *adap) |
|
{ |
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
|
} |
|
|
|
static const struct i2c_algorithm xiic_algorithm = { |
|
.master_xfer = xiic_xfer, |
|
.functionality = xiic_func, |
|
}; |
|
|
|
static const struct i2c_adapter_quirks xiic_quirks = { |
|
.max_read_len = 255, |
|
}; |
|
|
|
static const struct i2c_adapter xiic_adapter = { |
|
.owner = THIS_MODULE, |
|
.name = DRIVER_NAME, |
|
.class = I2C_CLASS_DEPRECATED, |
|
.algo = &xiic_algorithm, |
|
.quirks = &xiic_quirks, |
|
}; |
|
|
|
|
|
static int xiic_i2c_probe(struct platform_device *pdev) |
|
{ |
|
struct xiic_i2c *i2c; |
|
struct xiic_i2c_platform_data *pdata; |
|
struct resource *res; |
|
int ret, irq; |
|
u8 i; |
|
u32 sr; |
|
|
|
i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); |
|
if (!i2c) |
|
return -ENOMEM; |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
i2c->base = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(i2c->base)) |
|
return PTR_ERR(i2c->base); |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) |
|
return irq; |
|
|
|
pdata = dev_get_platdata(&pdev->dev); |
|
|
|
/* hook up driver to tree */ |
|
platform_set_drvdata(pdev, i2c); |
|
i2c->adap = xiic_adapter; |
|
i2c_set_adapdata(&i2c->adap, i2c); |
|
i2c->adap.dev.parent = &pdev->dev; |
|
i2c->adap.dev.of_node = pdev->dev.of_node; |
|
|
|
mutex_init(&i2c->lock); |
|
init_waitqueue_head(&i2c->wait); |
|
|
|
i2c->clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(i2c->clk)) |
|
return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), |
|
"input clock not found.\n"); |
|
|
|
ret = clk_prepare_enable(i2c->clk); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Unable to enable clock.\n"); |
|
return ret; |
|
} |
|
i2c->dev = &pdev->dev; |
|
pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); |
|
pm_runtime_use_autosuspend(i2c->dev); |
|
pm_runtime_set_active(i2c->dev); |
|
pm_runtime_enable(i2c->dev); |
|
ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr, |
|
xiic_process, IRQF_ONESHOT, |
|
pdev->name, i2c); |
|
|
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Cannot claim IRQ\n"); |
|
goto err_clk_dis; |
|
} |
|
|
|
i2c->singlemaster = |
|
of_property_read_bool(pdev->dev.of_node, "single-master"); |
|
|
|
/* |
|
* Detect endianness |
|
* Try to reset the TX FIFO. Then check the EMPTY flag. If it is not |
|
* set, assume that the endianness was wrong and swap. |
|
*/ |
|
i2c->endianness = LITTLE; |
|
xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); |
|
/* Reset is cleared in xiic_reinit */ |
|
sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); |
|
if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) |
|
i2c->endianness = BIG; |
|
|
|
ret = xiic_reinit(i2c); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Cannot xiic_reinit\n"); |
|
goto err_clk_dis; |
|
} |
|
|
|
/* add i2c adapter to i2c tree */ |
|
ret = i2c_add_adapter(&i2c->adap); |
|
if (ret) { |
|
xiic_deinit(i2c); |
|
goto err_clk_dis; |
|
} |
|
|
|
if (pdata) { |
|
/* add in known devices to the bus */ |
|
for (i = 0; i < pdata->num_devices; i++) |
|
i2c_new_client_device(&i2c->adap, pdata->devices + i); |
|
} |
|
|
|
return 0; |
|
|
|
err_clk_dis: |
|
pm_runtime_set_suspended(&pdev->dev); |
|
pm_runtime_disable(&pdev->dev); |
|
clk_disable_unprepare(i2c->clk); |
|
return ret; |
|
} |
|
|
|
static int xiic_i2c_remove(struct platform_device *pdev) |
|
{ |
|
struct xiic_i2c *i2c = platform_get_drvdata(pdev); |
|
int ret; |
|
|
|
/* remove adapter & data */ |
|
i2c_del_adapter(&i2c->adap); |
|
|
|
ret = pm_runtime_resume_and_get(i2c->dev); |
|
if (ret < 0) |
|
return ret; |
|
|
|
xiic_deinit(i2c); |
|
pm_runtime_put_sync(i2c->dev); |
|
clk_disable_unprepare(i2c->clk); |
|
pm_runtime_disable(&pdev->dev); |
|
pm_runtime_set_suspended(&pdev->dev); |
|
pm_runtime_dont_use_autosuspend(&pdev->dev); |
|
|
|
return 0; |
|
} |
|
|
|
#if defined(CONFIG_OF) |
|
static const struct of_device_id xiic_of_match[] = { |
|
{ .compatible = "xlnx,xps-iic-2.00.a", }, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, xiic_of_match); |
|
#endif |
|
|
|
static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) |
|
{ |
|
struct xiic_i2c *i2c = dev_get_drvdata(dev); |
|
|
|
clk_disable(i2c->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) |
|
{ |
|
struct xiic_i2c *i2c = dev_get_drvdata(dev); |
|
int ret; |
|
|
|
ret = clk_enable(i2c->clk); |
|
if (ret) { |
|
dev_err(dev, "Cannot enable clock.\n"); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops xiic_dev_pm_ops = { |
|
SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend, |
|
xiic_i2c_runtime_resume, NULL) |
|
}; |
|
static struct platform_driver xiic_i2c_driver = { |
|
.probe = xiic_i2c_probe, |
|
.remove = xiic_i2c_remove, |
|
.driver = { |
|
.name = DRIVER_NAME, |
|
.of_match_table = of_match_ptr(xiic_of_match), |
|
.pm = &xiic_dev_pm_ops, |
|
}, |
|
}; |
|
|
|
module_platform_driver(xiic_i2c_driver); |
|
|
|
MODULE_AUTHOR("[email protected]"); |
|
MODULE_DESCRIPTION("Xilinx I2C bus driver"); |
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_ALIAS("platform:"DRIVER_NAME);
|
|
|