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1015 lines
25 KiB
1015 lines
25 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
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* |
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* Description: CoreSight System Trace Macrocell driver |
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* |
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* Initial implementation by Pratik Patel |
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* (C) 2014-2015 Pratik Patel <[email protected]> |
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* |
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* Serious refactoring, code cleanup and upgrading to the Coresight upstream |
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* framework by Mathieu Poirier |
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* (C) 2015-2016 Mathieu Poirier <[email protected]> |
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* |
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* Guaranteed timing and support for various packet type coming from the |
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* generic STM API by Chunyan Zhang |
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* (C) 2015-2016 Chunyan Zhang <[email protected]> |
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*/ |
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#include <asm/local.h> |
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#include <linux/acpi.h> |
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#include <linux/amba/bus.h> |
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#include <linux/bitmap.h> |
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#include <linux/clk.h> |
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#include <linux/coresight.h> |
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#include <linux/coresight-stm.h> |
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#include <linux/err.h> |
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#include <linux/kernel.h> |
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#include <linux/moduleparam.h> |
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#include <linux/of_address.h> |
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#include <linux/perf_event.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/stm.h> |
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|
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#include "coresight-priv.h" |
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|
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#define STMDMASTARTR 0xc04 |
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#define STMDMASTOPR 0xc08 |
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#define STMDMASTATR 0xc0c |
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#define STMDMACTLR 0xc10 |
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#define STMDMAIDR 0xcfc |
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#define STMHEER 0xd00 |
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#define STMHETER 0xd20 |
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#define STMHEBSR 0xd60 |
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#define STMHEMCR 0xd64 |
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#define STMHEMASTR 0xdf4 |
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#define STMHEFEAT1R 0xdf8 |
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#define STMHEIDR 0xdfc |
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#define STMSPER 0xe00 |
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#define STMSPTER 0xe20 |
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#define STMPRIVMASKR 0xe40 |
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#define STMSPSCR 0xe60 |
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#define STMSPMSCR 0xe64 |
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#define STMSPOVERRIDER 0xe68 |
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#define STMSPMOVERRIDER 0xe6c |
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#define STMSPTRIGCSR 0xe70 |
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#define STMTCSR 0xe80 |
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#define STMTSSTIMR 0xe84 |
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#define STMTSFREQR 0xe8c |
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#define STMSYNCR 0xe90 |
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#define STMAUXCR 0xe94 |
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#define STMSPFEAT1R 0xea0 |
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#define STMSPFEAT2R 0xea4 |
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#define STMSPFEAT3R 0xea8 |
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#define STMITTRIGGER 0xee8 |
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#define STMITATBDATA0 0xeec |
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#define STMITATBCTR2 0xef0 |
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#define STMITATBID 0xef4 |
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#define STMITATBCTR0 0xef8 |
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|
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#define STM_32_CHANNEL 32 |
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#define BYTES_PER_CHANNEL 256 |
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#define STM_TRACE_BUF_SIZE 4096 |
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#define STM_SW_MASTER_END 127 |
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|
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/* Register bit definition */ |
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#define STMTCSR_BUSY_BIT 23 |
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/* Reserve the first 10 channels for kernel usage */ |
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#define STM_CHANNEL_OFFSET 0 |
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|
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enum stm_pkt_type { |
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STM_PKT_TYPE_DATA = 0x98, |
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STM_PKT_TYPE_FLAG = 0xE8, |
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STM_PKT_TYPE_TRIG = 0xF8, |
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}; |
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#define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \ |
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(ch * BYTES_PER_CHANNEL)) |
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#define stm_channel_off(type, opts) (type & ~opts) |
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|
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static int boot_nr_channel; |
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|
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/* |
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* Not really modular but using module_param is the easiest way to |
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* remain consistent with existing use cases for now. |
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*/ |
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module_param_named( |
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boot_nr_channel, boot_nr_channel, int, S_IRUGO |
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); |
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|
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/* |
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* struct channel_space - central management entity for extended ports |
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* @base: memory mapped base address where channels start. |
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* @phys: physical base address of channel region. |
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* @guaraneed: is the channel delivery guaranteed. |
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*/ |
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struct channel_space { |
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void __iomem *base; |
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phys_addr_t phys; |
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unsigned long *guaranteed; |
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}; |
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DEFINE_CORESIGHT_DEVLIST(stm_devs, "stm"); |
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|
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/** |
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* struct stm_drvdata - specifics associated to an STM component |
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* @base: memory mapped base address for this component. |
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* @atclk: optional clock for the core parts of the STM. |
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* @csdev: component vitals needed by the framework. |
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* @spinlock: only one at a time pls. |
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* @chs: the channels accociated to this STM. |
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* @stm: structure associated to the generic STM interface. |
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* @mode: this tracer's mode, i.e sysFS, or disabled. |
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* @traceid: value of the current ID for this component. |
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* @write_bytes: Maximus bytes this STM can write at a time. |
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* @stmsper: settings for register STMSPER. |
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* @stmspscr: settings for register STMSPSCR. |
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* @numsp: the total number of stimulus port support by this STM. |
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* @stmheer: settings for register STMHEER. |
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* @stmheter: settings for register STMHETER. |
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* @stmhebsr: settings for register STMHEBSR. |
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*/ |
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struct stm_drvdata { |
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void __iomem *base; |
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struct clk *atclk; |
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struct coresight_device *csdev; |
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spinlock_t spinlock; |
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struct channel_space chs; |
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struct stm_data stm; |
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local_t mode; |
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u8 traceid; |
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u32 write_bytes; |
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u32 stmsper; |
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u32 stmspscr; |
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u32 numsp; |
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u32 stmheer; |
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u32 stmheter; |
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u32 stmhebsr; |
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}; |
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|
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static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata) |
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{ |
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CS_UNLOCK(drvdata->base); |
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|
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writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR); |
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writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER); |
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writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER); |
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writel_relaxed(0x01 | /* Enable HW event tracing */ |
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0x04, /* Error detection on event tracing */ |
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drvdata->base + STMHEMCR); |
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|
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CS_LOCK(drvdata->base); |
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} |
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|
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static void stm_port_enable_hw(struct stm_drvdata *drvdata) |
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{ |
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CS_UNLOCK(drvdata->base); |
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/* ATB trigger enable on direct writes to TRIG locations */ |
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writel_relaxed(0x10, |
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drvdata->base + STMSPTRIGCSR); |
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writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR); |
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writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER); |
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|
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CS_LOCK(drvdata->base); |
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} |
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static void stm_enable_hw(struct stm_drvdata *drvdata) |
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{ |
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if (drvdata->stmheer) |
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stm_hwevent_enable_hw(drvdata); |
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|
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stm_port_enable_hw(drvdata); |
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CS_UNLOCK(drvdata->base); |
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|
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/* 4096 byte between synchronisation packets */ |
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writel_relaxed(0xFFF, drvdata->base + STMSYNCR); |
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writel_relaxed((drvdata->traceid << 16 | /* trace id */ |
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0x02 | /* timestamp enable */ |
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0x01), /* global STM enable */ |
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drvdata->base + STMTCSR); |
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|
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CS_LOCK(drvdata->base); |
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} |
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|
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static int stm_enable(struct coresight_device *csdev, |
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struct perf_event *event, u32 mode) |
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{ |
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u32 val; |
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struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
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|
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if (mode != CS_MODE_SYSFS) |
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return -EINVAL; |
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val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); |
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/* Someone is already using the tracer */ |
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if (val) |
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return -EBUSY; |
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pm_runtime_get_sync(csdev->dev.parent); |
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spin_lock(&drvdata->spinlock); |
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stm_enable_hw(drvdata); |
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spin_unlock(&drvdata->spinlock); |
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dev_dbg(&csdev->dev, "STM tracing enabled\n"); |
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return 0; |
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} |
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static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata) |
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{ |
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CS_UNLOCK(drvdata->base); |
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|
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writel_relaxed(0x0, drvdata->base + STMHEMCR); |
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writel_relaxed(0x0, drvdata->base + STMHEER); |
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writel_relaxed(0x0, drvdata->base + STMHETER); |
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CS_LOCK(drvdata->base); |
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} |
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static void stm_port_disable_hw(struct stm_drvdata *drvdata) |
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{ |
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CS_UNLOCK(drvdata->base); |
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|
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writel_relaxed(0x0, drvdata->base + STMSPER); |
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writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR); |
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CS_LOCK(drvdata->base); |
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} |
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static void stm_disable_hw(struct stm_drvdata *drvdata) |
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{ |
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u32 val; |
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CS_UNLOCK(drvdata->base); |
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val = readl_relaxed(drvdata->base + STMTCSR); |
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val &= ~0x1; /* clear global STM enable [0] */ |
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writel_relaxed(val, drvdata->base + STMTCSR); |
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CS_LOCK(drvdata->base); |
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stm_port_disable_hw(drvdata); |
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if (drvdata->stmheer) |
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stm_hwevent_disable_hw(drvdata); |
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} |
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static void stm_disable(struct coresight_device *csdev, |
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struct perf_event *event) |
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{ |
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struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
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struct csdev_access *csa = &csdev->access; |
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|
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/* |
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* For as long as the tracer isn't disabled another entity can't |
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* change its status. As such we can read the status here without |
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* fearing it will change under us. |
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*/ |
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if (local_read(&drvdata->mode) == CS_MODE_SYSFS) { |
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spin_lock(&drvdata->spinlock); |
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stm_disable_hw(drvdata); |
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spin_unlock(&drvdata->spinlock); |
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|
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/* Wait until the engine has completely stopped */ |
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coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0); |
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pm_runtime_put(csdev->dev.parent); |
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local_set(&drvdata->mode, CS_MODE_DISABLED); |
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dev_dbg(&csdev->dev, "STM tracing disabled\n"); |
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} |
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} |
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static int stm_trace_id(struct coresight_device *csdev) |
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{ |
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struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); |
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return drvdata->traceid; |
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} |
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static const struct coresight_ops_source stm_source_ops = { |
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.trace_id = stm_trace_id, |
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.enable = stm_enable, |
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.disable = stm_disable, |
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}; |
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static const struct coresight_ops stm_cs_ops = { |
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.source_ops = &stm_source_ops, |
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}; |
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static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes) |
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{ |
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return ((unsigned long)addr & (write_bytes - 1)); |
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} |
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static void stm_send(void __iomem *addr, const void *data, |
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u32 size, u8 write_bytes) |
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{ |
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u8 paload[8]; |
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|
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if (stm_addr_unaligned(data, write_bytes)) { |
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memcpy(paload, data, size); |
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data = paload; |
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} |
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|
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/* now we are 64bit/32bit aligned */ |
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switch (size) { |
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#ifdef CONFIG_64BIT |
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case 8: |
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writeq_relaxed(*(u64 *)data, addr); |
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break; |
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#endif |
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case 4: |
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writel_relaxed(*(u32 *)data, addr); |
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break; |
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case 2: |
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writew_relaxed(*(u16 *)data, addr); |
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break; |
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case 1: |
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writeb_relaxed(*(u8 *)data, addr); |
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break; |
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default: |
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break; |
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} |
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} |
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static int stm_generic_link(struct stm_data *stm_data, |
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unsigned int master, unsigned int channel) |
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{ |
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struct stm_drvdata *drvdata = container_of(stm_data, |
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struct stm_drvdata, stm); |
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if (!drvdata || !drvdata->csdev) |
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return -EINVAL; |
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return coresight_enable(drvdata->csdev); |
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} |
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static void stm_generic_unlink(struct stm_data *stm_data, |
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unsigned int master, unsigned int channel) |
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{ |
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struct stm_drvdata *drvdata = container_of(stm_data, |
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struct stm_drvdata, stm); |
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if (!drvdata || !drvdata->csdev) |
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return; |
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coresight_disable(drvdata->csdev); |
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} |
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static phys_addr_t |
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stm_mmio_addr(struct stm_data *stm_data, unsigned int master, |
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unsigned int channel, unsigned int nr_chans) |
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{ |
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struct stm_drvdata *drvdata = container_of(stm_data, |
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struct stm_drvdata, stm); |
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phys_addr_t addr; |
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addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL; |
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if (offset_in_page(addr) || |
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offset_in_page(nr_chans * BYTES_PER_CHANNEL)) |
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return 0; |
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return addr; |
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} |
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static long stm_generic_set_options(struct stm_data *stm_data, |
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unsigned int master, |
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unsigned int channel, |
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unsigned int nr_chans, |
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unsigned long options) |
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{ |
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struct stm_drvdata *drvdata = container_of(stm_data, |
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struct stm_drvdata, stm); |
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if (!(drvdata && local_read(&drvdata->mode))) |
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return -EINVAL; |
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|
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if (channel >= drvdata->numsp) |
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return -EINVAL; |
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switch (options) { |
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case STM_OPTION_GUARANTEED: |
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set_bit(channel, drvdata->chs.guaranteed); |
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break; |
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|
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case STM_OPTION_INVARIANT: |
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clear_bit(channel, drvdata->chs.guaranteed); |
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break; |
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|
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static ssize_t notrace stm_generic_packet(struct stm_data *stm_data, |
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unsigned int master, |
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unsigned int channel, |
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unsigned int packet, |
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unsigned int flags, |
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unsigned int size, |
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const unsigned char *payload) |
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{ |
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void __iomem *ch_addr; |
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struct stm_drvdata *drvdata = container_of(stm_data, |
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struct stm_drvdata, stm); |
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unsigned int stm_flags; |
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|
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if (!(drvdata && local_read(&drvdata->mode))) |
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return -EACCES; |
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|
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if (channel >= drvdata->numsp) |
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return -EINVAL; |
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ch_addr = stm_channel_addr(drvdata, channel); |
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|
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stm_flags = (flags & STP_PACKET_TIMESTAMPED) ? |
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STM_FLAG_TIMESTAMPED : 0; |
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stm_flags |= test_bit(channel, drvdata->chs.guaranteed) ? |
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STM_FLAG_GUARANTEED : 0; |
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|
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if (size > drvdata->write_bytes) |
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size = drvdata->write_bytes; |
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else |
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size = rounddown_pow_of_two(size); |
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|
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switch (packet) { |
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case STP_PACKET_FLAG: |
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ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, stm_flags); |
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|
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/* |
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* The generic STM core sets a size of '0' on flag packets. |
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* As such send a flag packet of size '1' and tell the |
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* core we did so. |
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*/ |
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stm_send(ch_addr, payload, 1, drvdata->write_bytes); |
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size = 1; |
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break; |
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|
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case STP_PACKET_DATA: |
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stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0; |
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ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, stm_flags); |
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stm_send(ch_addr, payload, size, |
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drvdata->write_bytes); |
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break; |
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|
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default: |
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return -ENOTSUPP; |
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} |
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|
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return size; |
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} |
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|
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static ssize_t hwevent_enable_show(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); |
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unsigned long val = drvdata->stmheer; |
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|
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return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); |
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} |
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|
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static ssize_t hwevent_enable_store(struct device *dev, |
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struct device_attribute *attr, |
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const char *buf, size_t size) |
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{ |
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struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); |
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unsigned long val; |
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int ret = 0; |
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|
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ret = kstrtoul(buf, 16, &val); |
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if (ret) |
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return -EINVAL; |
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|
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drvdata->stmheer = val; |
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/* HW event enable and trigger go hand in hand */ |
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drvdata->stmheter = val; |
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|
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return size; |
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} |
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static DEVICE_ATTR_RW(hwevent_enable); |
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|
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static ssize_t hwevent_select_show(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); |
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unsigned long val = drvdata->stmhebsr; |
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|
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return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); |
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} |
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|
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static ssize_t hwevent_select_store(struct device *dev, |
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struct device_attribute *attr, |
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const char *buf, size_t size) |
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{ |
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struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); |
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unsigned long val; |
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int ret = 0; |
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|
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ret = kstrtoul(buf, 16, &val); |
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if (ret) |
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return -EINVAL; |
|
|
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drvdata->stmhebsr = val; |
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|
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return size; |
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} |
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static DEVICE_ATTR_RW(hwevent_select); |
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|
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static ssize_t port_select_show(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); |
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unsigned long val; |
|
|
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if (!local_read(&drvdata->mode)) { |
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val = drvdata->stmspscr; |
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} else { |
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spin_lock(&drvdata->spinlock); |
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val = readl_relaxed(drvdata->base + STMSPSCR); |
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spin_unlock(&drvdata->spinlock); |
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} |
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|
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return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); |
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} |
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|
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static ssize_t port_select_store(struct device *dev, |
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struct device_attribute *attr, |
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const char *buf, size_t size) |
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{ |
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struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); |
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unsigned long val, stmsper; |
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int ret = 0; |
|
|
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ret = kstrtoul(buf, 16, &val); |
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if (ret) |
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return ret; |
|
|
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spin_lock(&drvdata->spinlock); |
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drvdata->stmspscr = val; |
|
|
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if (local_read(&drvdata->mode)) { |
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CS_UNLOCK(drvdata->base); |
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/* Process as per ARM's TRM recommendation */ |
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stmsper = readl_relaxed(drvdata->base + STMSPER); |
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writel_relaxed(0x0, drvdata->base + STMSPER); |
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writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR); |
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writel_relaxed(stmsper, drvdata->base + STMSPER); |
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CS_LOCK(drvdata->base); |
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} |
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spin_unlock(&drvdata->spinlock); |
|
|
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return size; |
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} |
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static DEVICE_ATTR_RW(port_select); |
|
|
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static ssize_t port_enable_show(struct device *dev, |
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struct device_attribute *attr, char *buf) |
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{ |
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struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); |
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unsigned long val; |
|
|
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if (!local_read(&drvdata->mode)) { |
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val = drvdata->stmsper; |
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} else { |
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spin_lock(&drvdata->spinlock); |
|
val = readl_relaxed(drvdata->base + STMSPER); |
|
spin_unlock(&drvdata->spinlock); |
|
} |
|
|
|
return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); |
|
} |
|
|
|
static ssize_t port_enable_store(struct device *dev, |
|
struct device_attribute *attr, |
|
const char *buf, size_t size) |
|
{ |
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); |
|
unsigned long val; |
|
int ret = 0; |
|
|
|
ret = kstrtoul(buf, 16, &val); |
|
if (ret) |
|
return ret; |
|
|
|
spin_lock(&drvdata->spinlock); |
|
drvdata->stmsper = val; |
|
|
|
if (local_read(&drvdata->mode)) { |
|
CS_UNLOCK(drvdata->base); |
|
writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER); |
|
CS_LOCK(drvdata->base); |
|
} |
|
spin_unlock(&drvdata->spinlock); |
|
|
|
return size; |
|
} |
|
static DEVICE_ATTR_RW(port_enable); |
|
|
|
static ssize_t traceid_show(struct device *dev, |
|
struct device_attribute *attr, char *buf) |
|
{ |
|
unsigned long val; |
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); |
|
|
|
val = drvdata->traceid; |
|
return sprintf(buf, "%#lx\n", val); |
|
} |
|
|
|
static ssize_t traceid_store(struct device *dev, |
|
struct device_attribute *attr, |
|
const char *buf, size_t size) |
|
{ |
|
int ret; |
|
unsigned long val; |
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); |
|
|
|
ret = kstrtoul(buf, 16, &val); |
|
if (ret) |
|
return ret; |
|
|
|
/* traceid field is 7bit wide on STM32 */ |
|
drvdata->traceid = val & 0x7f; |
|
return size; |
|
} |
|
static DEVICE_ATTR_RW(traceid); |
|
|
|
#define coresight_stm_reg(name, offset) \ |
|
coresight_simple_reg32(struct stm_drvdata, name, offset) |
|
|
|
coresight_stm_reg(tcsr, STMTCSR); |
|
coresight_stm_reg(tsfreqr, STMTSFREQR); |
|
coresight_stm_reg(syncr, STMSYNCR); |
|
coresight_stm_reg(sper, STMSPER); |
|
coresight_stm_reg(spter, STMSPTER); |
|
coresight_stm_reg(privmaskr, STMPRIVMASKR); |
|
coresight_stm_reg(spscr, STMSPSCR); |
|
coresight_stm_reg(spmscr, STMSPMSCR); |
|
coresight_stm_reg(spfeat1r, STMSPFEAT1R); |
|
coresight_stm_reg(spfeat2r, STMSPFEAT2R); |
|
coresight_stm_reg(spfeat3r, STMSPFEAT3R); |
|
coresight_stm_reg(devid, CORESIGHT_DEVID); |
|
|
|
static struct attribute *coresight_stm_attrs[] = { |
|
&dev_attr_hwevent_enable.attr, |
|
&dev_attr_hwevent_select.attr, |
|
&dev_attr_port_enable.attr, |
|
&dev_attr_port_select.attr, |
|
&dev_attr_traceid.attr, |
|
NULL, |
|
}; |
|
|
|
static struct attribute *coresight_stm_mgmt_attrs[] = { |
|
&dev_attr_tcsr.attr, |
|
&dev_attr_tsfreqr.attr, |
|
&dev_attr_syncr.attr, |
|
&dev_attr_sper.attr, |
|
&dev_attr_spter.attr, |
|
&dev_attr_privmaskr.attr, |
|
&dev_attr_spscr.attr, |
|
&dev_attr_spmscr.attr, |
|
&dev_attr_spfeat1r.attr, |
|
&dev_attr_spfeat2r.attr, |
|
&dev_attr_spfeat3r.attr, |
|
&dev_attr_devid.attr, |
|
NULL, |
|
}; |
|
|
|
static const struct attribute_group coresight_stm_group = { |
|
.attrs = coresight_stm_attrs, |
|
}; |
|
|
|
static const struct attribute_group coresight_stm_mgmt_group = { |
|
.attrs = coresight_stm_mgmt_attrs, |
|
.name = "mgmt", |
|
}; |
|
|
|
static const struct attribute_group *coresight_stm_groups[] = { |
|
&coresight_stm_group, |
|
&coresight_stm_mgmt_group, |
|
NULL, |
|
}; |
|
|
|
#ifdef CONFIG_OF |
|
static int of_stm_get_stimulus_area(struct device *dev, struct resource *res) |
|
{ |
|
const char *name = NULL; |
|
int index = 0, found = 0; |
|
struct device_node *np = dev->of_node; |
|
|
|
while (!of_property_read_string_index(np, "reg-names", index, &name)) { |
|
if (strcmp("stm-stimulus-base", name)) { |
|
index++; |
|
continue; |
|
} |
|
|
|
/* We have a match and @index is where it's at */ |
|
found = 1; |
|
break; |
|
} |
|
|
|
if (!found) |
|
return -EINVAL; |
|
|
|
return of_address_to_resource(np, index, res); |
|
} |
|
#else |
|
static inline int of_stm_get_stimulus_area(struct device *dev, |
|
struct resource *res) |
|
{ |
|
return -ENOENT; |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_ACPI |
|
static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res) |
|
{ |
|
int rc; |
|
bool found_base = false; |
|
struct resource_entry *rent; |
|
LIST_HEAD(res_list); |
|
|
|
struct acpi_device *adev = ACPI_COMPANION(dev); |
|
|
|
rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL); |
|
if (rc < 0) |
|
return rc; |
|
|
|
/* |
|
* The stimulus base for STM device must be listed as the second memory |
|
* resource, followed by the programming base address as described in |
|
* "Section 2.3 Resources" in ACPI for CoreSightTM 1.0 Platform Design |
|
* document (DEN0067). |
|
*/ |
|
rc = -ENOENT; |
|
list_for_each_entry(rent, &res_list, node) { |
|
if (resource_type(rent->res) != IORESOURCE_MEM) |
|
continue; |
|
if (found_base) { |
|
*res = *rent->res; |
|
rc = 0; |
|
break; |
|
} |
|
|
|
found_base = true; |
|
} |
|
|
|
acpi_dev_free_resource_list(&res_list); |
|
return rc; |
|
} |
|
#else |
|
static inline int acpi_stm_get_stimulus_area(struct device *dev, |
|
struct resource *res) |
|
{ |
|
return -ENOENT; |
|
} |
|
#endif |
|
|
|
static int stm_get_stimulus_area(struct device *dev, struct resource *res) |
|
{ |
|
struct fwnode_handle *fwnode = dev_fwnode(dev); |
|
|
|
if (is_of_node(fwnode)) |
|
return of_stm_get_stimulus_area(dev, res); |
|
else if (is_acpi_node(fwnode)) |
|
return acpi_stm_get_stimulus_area(dev, res); |
|
return -ENOENT; |
|
} |
|
|
|
static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata) |
|
{ |
|
u32 stmspfeat2r; |
|
|
|
if (!IS_ENABLED(CONFIG_64BIT)) |
|
return 4; |
|
|
|
stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R); |
|
|
|
/* |
|
* bit[15:12] represents the fundamental data size |
|
* 0 - 32-bit data |
|
* 1 - 64-bit data |
|
*/ |
|
return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4; |
|
} |
|
|
|
static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata) |
|
{ |
|
u32 numsp; |
|
|
|
numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID); |
|
/* |
|
* NUMPS in STMDEVID is 17 bit long and if equal to 0x0, |
|
* 32 stimulus ports are supported. |
|
*/ |
|
numsp &= 0x1ffff; |
|
if (!numsp) |
|
numsp = STM_32_CHANNEL; |
|
return numsp; |
|
} |
|
|
|
static void stm_init_default_data(struct stm_drvdata *drvdata) |
|
{ |
|
/* Don't use port selection */ |
|
drvdata->stmspscr = 0x0; |
|
/* |
|
* Enable all channel regardless of their number. When port |
|
* selection isn't used (see above) STMSPER applies to all |
|
* 32 channel group available, hence setting all 32 bits to 1 |
|
*/ |
|
drvdata->stmsper = ~0x0; |
|
|
|
/* |
|
* The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and |
|
* anything equal to or higher than 0x70 is reserved. Since 0x00 is |
|
* also reserved the STM trace ID needs to be higher than 0x00 and |
|
* lowner than 0x10. |
|
*/ |
|
drvdata->traceid = 0x1; |
|
|
|
/* Set invariant transaction timing on all channels */ |
|
bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp); |
|
} |
|
|
|
static void stm_init_generic_data(struct stm_drvdata *drvdata, |
|
const char *name) |
|
{ |
|
drvdata->stm.name = name; |
|
|
|
/* |
|
* MasterIDs are assigned at HW design phase. As such the core is |
|
* using a single master for interaction with this device. |
|
*/ |
|
drvdata->stm.sw_start = 1; |
|
drvdata->stm.sw_end = 1; |
|
drvdata->stm.hw_override = true; |
|
drvdata->stm.sw_nchannels = drvdata->numsp; |
|
drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL; |
|
drvdata->stm.packet = stm_generic_packet; |
|
drvdata->stm.mmio_addr = stm_mmio_addr; |
|
drvdata->stm.link = stm_generic_link; |
|
drvdata->stm.unlink = stm_generic_unlink; |
|
drvdata->stm.set_options = stm_generic_set_options; |
|
} |
|
|
|
static int stm_probe(struct amba_device *adev, const struct amba_id *id) |
|
{ |
|
int ret; |
|
void __iomem *base; |
|
unsigned long *guaranteed; |
|
struct device *dev = &adev->dev; |
|
struct coresight_platform_data *pdata = NULL; |
|
struct stm_drvdata *drvdata; |
|
struct resource *res = &adev->res; |
|
struct resource ch_res; |
|
size_t bitmap_size; |
|
struct coresight_desc desc = { 0 }; |
|
|
|
desc.name = coresight_alloc_device_name(&stm_devs, dev); |
|
if (!desc.name) |
|
return -ENOMEM; |
|
|
|
drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); |
|
if (!drvdata) |
|
return -ENOMEM; |
|
|
|
drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ |
|
if (!IS_ERR(drvdata->atclk)) { |
|
ret = clk_prepare_enable(drvdata->atclk); |
|
if (ret) |
|
return ret; |
|
} |
|
dev_set_drvdata(dev, drvdata); |
|
|
|
base = devm_ioremap_resource(dev, res); |
|
if (IS_ERR(base)) |
|
return PTR_ERR(base); |
|
drvdata->base = base; |
|
desc.access = CSDEV_ACCESS_IOMEM(base); |
|
|
|
ret = stm_get_stimulus_area(dev, &ch_res); |
|
if (ret) |
|
return ret; |
|
drvdata->chs.phys = ch_res.start; |
|
|
|
base = devm_ioremap_resource(dev, &ch_res); |
|
if (IS_ERR(base)) |
|
return PTR_ERR(base); |
|
drvdata->chs.base = base; |
|
|
|
drvdata->write_bytes = stm_fundamental_data_size(drvdata); |
|
|
|
if (boot_nr_channel) |
|
drvdata->numsp = boot_nr_channel; |
|
else |
|
drvdata->numsp = stm_num_stimulus_port(drvdata); |
|
|
|
bitmap_size = BITS_TO_LONGS(drvdata->numsp) * sizeof(long); |
|
|
|
guaranteed = devm_kzalloc(dev, bitmap_size, GFP_KERNEL); |
|
if (!guaranteed) |
|
return -ENOMEM; |
|
drvdata->chs.guaranteed = guaranteed; |
|
|
|
spin_lock_init(&drvdata->spinlock); |
|
|
|
stm_init_default_data(drvdata); |
|
stm_init_generic_data(drvdata, desc.name); |
|
|
|
if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) { |
|
dev_info(dev, |
|
"%s : stm_register_device failed, probing deferred\n", |
|
desc.name); |
|
return -EPROBE_DEFER; |
|
} |
|
|
|
pdata = coresight_get_platform_data(dev); |
|
if (IS_ERR(pdata)) { |
|
ret = PTR_ERR(pdata); |
|
goto stm_unregister; |
|
} |
|
adev->dev.platform_data = pdata; |
|
|
|
desc.type = CORESIGHT_DEV_TYPE_SOURCE; |
|
desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE; |
|
desc.ops = &stm_cs_ops; |
|
desc.pdata = pdata; |
|
desc.dev = dev; |
|
desc.groups = coresight_stm_groups; |
|
drvdata->csdev = coresight_register(&desc); |
|
if (IS_ERR(drvdata->csdev)) { |
|
ret = PTR_ERR(drvdata->csdev); |
|
goto stm_unregister; |
|
} |
|
|
|
pm_runtime_put(&adev->dev); |
|
|
|
dev_info(&drvdata->csdev->dev, "%s initialized\n", |
|
(char *)coresight_get_uci_data(id)); |
|
return 0; |
|
|
|
stm_unregister: |
|
stm_unregister_device(&drvdata->stm); |
|
return ret; |
|
} |
|
|
|
static void stm_remove(struct amba_device *adev) |
|
{ |
|
struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev); |
|
|
|
coresight_unregister(drvdata->csdev); |
|
|
|
stm_unregister_device(&drvdata->stm); |
|
} |
|
|
|
#ifdef CONFIG_PM |
|
static int stm_runtime_suspend(struct device *dev) |
|
{ |
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev); |
|
|
|
if (drvdata && !IS_ERR(drvdata->atclk)) |
|
clk_disable_unprepare(drvdata->atclk); |
|
|
|
return 0; |
|
} |
|
|
|
static int stm_runtime_resume(struct device *dev) |
|
{ |
|
struct stm_drvdata *drvdata = dev_get_drvdata(dev); |
|
|
|
if (drvdata && !IS_ERR(drvdata->atclk)) |
|
clk_prepare_enable(drvdata->atclk); |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
static const struct dev_pm_ops stm_dev_pm_ops = { |
|
SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL) |
|
}; |
|
|
|
static const struct amba_id stm_ids[] = { |
|
CS_AMBA_ID_DATA(0x000bb962, "STM32"), |
|
CS_AMBA_ID_DATA(0x000bb963, "STM500"), |
|
{ 0, 0}, |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(amba, stm_ids); |
|
|
|
static struct amba_driver stm_driver = { |
|
.drv = { |
|
.name = "coresight-stm", |
|
.owner = THIS_MODULE, |
|
.pm = &stm_dev_pm_ops, |
|
.suppress_bind_attrs = true, |
|
}, |
|
.probe = stm_probe, |
|
.remove = stm_remove, |
|
.id_table = stm_ids, |
|
}; |
|
|
|
module_amba_driver(stm_driver); |
|
|
|
MODULE_AUTHOR("Pratik Patel <[email protected]>"); |
|
MODULE_DESCRIPTION("Arm CoreSight System Trace Macrocell driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|