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513 lines
14 KiB
513 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h/17h |
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* processor hardware monitoring |
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* |
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* Copyright (c) 2009 Clemens Ladisch <[email protected]> |
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* Copyright (c) 2020 Guenter Roeck <[email protected]> |
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* |
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* Implementation notes: |
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* - CCD register address information as well as the calculation to |
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* convert raw register values is from https://github.com/ocerman/zenpower. |
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* The information is not confirmed from chip datasheets, but experiments |
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* suggest that it provides reasonable temperature values. |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/err.h> |
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#include <linux/hwmon.h> |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/pci_ids.h> |
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#include <asm/amd_nb.h> |
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#include <asm/processor.h> |
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MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor"); |
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MODULE_AUTHOR("Clemens Ladisch <[email protected]>"); |
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MODULE_LICENSE("GPL"); |
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static bool force; |
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module_param(force, bool, 0444); |
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MODULE_PARM_DESC(force, "force loading on processors with erratum 319"); |
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/* Provide lock for writing to NB_SMU_IND_ADDR */ |
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static DEFINE_MUTEX(nb_smu_ind_mutex); |
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#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 |
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#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3 |
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#endif |
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/* CPUID function 0x80000001, ebx */ |
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#define CPUID_PKGTYPE_MASK GENMASK(31, 28) |
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#define CPUID_PKGTYPE_F 0x00000000 |
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#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000 |
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/* DRAM controller (PCI function 2) */ |
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#define REG_DCT0_CONFIG_HIGH 0x094 |
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#define DDR3_MODE BIT(8) |
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/* miscellaneous (PCI function 3) */ |
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#define REG_HARDWARE_THERMAL_CONTROL 0x64 |
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#define HTC_ENABLE BIT(0) |
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#define REG_REPORTED_TEMPERATURE 0xa4 |
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#define REG_NORTHBRIDGE_CAPABILITIES 0xe8 |
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#define NB_CAP_HTC BIT(10) |
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/* |
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* For F15h M60h and M70h, REG_HARDWARE_THERMAL_CONTROL |
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* and REG_REPORTED_TEMPERATURE have been moved to |
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* D0F0xBC_xD820_0C64 [Hardware Temperature Control] |
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* D0F0xBC_xD820_0CA4 [Reported Temperature Control] |
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*/ |
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#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 |
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#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 |
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/* Common for Zen CPU families (Family 17h and 18h and 19h) */ |
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#define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800 |
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#define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \ |
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(offset) + ((x) * 4)) |
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#define ZEN_CCD_TEMP_VALID BIT(11) |
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#define ZEN_CCD_TEMP_MASK GENMASK(10, 0) |
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#define ZEN_CUR_TEMP_SHIFT 21 |
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#define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19) |
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#define ZEN_SVI_BASE 0x0005A000 |
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/* F17h thermal registers through SMN */ |
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#define F17H_M01H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0xc) |
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#define F17H_M01H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) |
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#define F17H_M31H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14) |
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#define F17H_M31H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) |
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#define F17H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */ |
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#define F17H_M01H_CFACTOR_ISOC 250000 /* 0.25A / LSB */ |
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#define F17H_M31H_CFACTOR_ICORE 1000000 /* 1A / LSB */ |
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#define F17H_M31H_CFACTOR_ISOC 310000 /* 0.31A / LSB */ |
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/* F19h thermal registers through SMN */ |
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#define F19H_M01_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14) |
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#define F19H_M01_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10) |
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#define F19H_M01H_CFACTOR_ICORE 1000000 /* 1A / LSB */ |
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#define F19H_M01H_CFACTOR_ISOC 310000 /* 0.31A / LSB */ |
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struct k10temp_data { |
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struct pci_dev *pdev; |
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void (*read_htcreg)(struct pci_dev *pdev, u32 *regval); |
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void (*read_tempreg)(struct pci_dev *pdev, u32 *regval); |
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int temp_offset; |
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u32 temp_adjust_mask; |
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u32 show_temp; |
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bool is_zen; |
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u32 ccd_offset; |
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}; |
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#define TCTL_BIT 0 |
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#define TDIE_BIT 1 |
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#define TCCD_BIT(x) ((x) + 2) |
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#define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel)) |
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#define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT) |
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struct tctl_offset { |
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u8 model; |
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char const *id; |
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int offset; |
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}; |
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static const struct tctl_offset tctl_offset_table[] = { |
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{ 0x17, "AMD Ryzen 5 1600X", 20000 }, |
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{ 0x17, "AMD Ryzen 7 1700X", 20000 }, |
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{ 0x17, "AMD Ryzen 7 1800X", 20000 }, |
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{ 0x17, "AMD Ryzen 7 2700X", 10000 }, |
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{ 0x17, "AMD Ryzen Threadripper 19", 27000 }, /* 19{00,20,50}X */ |
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{ 0x17, "AMD Ryzen Threadripper 29", 27000 }, /* 29{20,50,70,90}[W]X */ |
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}; |
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static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval) |
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{ |
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pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval); |
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} |
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static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval) |
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{ |
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pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval); |
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} |
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static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn, |
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unsigned int base, int offset, u32 *val) |
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{ |
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mutex_lock(&nb_smu_ind_mutex); |
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pci_bus_write_config_dword(pdev->bus, devfn, |
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base, offset); |
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pci_bus_read_config_dword(pdev->bus, devfn, |
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base + 4, val); |
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mutex_unlock(&nb_smu_ind_mutex); |
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} |
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static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval) |
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{ |
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amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, |
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F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval); |
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} |
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static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval) |
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{ |
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amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8, |
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F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval); |
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} |
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static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval) |
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{ |
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amd_smn_read(amd_pci_dev_to_node_id(pdev), |
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ZEN_REPORTED_TEMP_CTRL_BASE, regval); |
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} |
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static long get_raw_temp(struct k10temp_data *data) |
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{ |
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u32 regval; |
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long temp; |
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data->read_tempreg(data->pdev, ®val); |
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temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125; |
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if (regval & data->temp_adjust_mask) |
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temp -= 49000; |
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return temp; |
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} |
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static const char *k10temp_temp_label[] = { |
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"Tctl", |
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"Tdie", |
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"Tccd1", |
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"Tccd2", |
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"Tccd3", |
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"Tccd4", |
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"Tccd5", |
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"Tccd6", |
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"Tccd7", |
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"Tccd8", |
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}; |
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static int k10temp_read_labels(struct device *dev, |
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enum hwmon_sensor_types type, |
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u32 attr, int channel, const char **str) |
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{ |
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switch (type) { |
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case hwmon_temp: |
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*str = k10temp_temp_label[channel]; |
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break; |
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default: |
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return -EOPNOTSUPP; |
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} |
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return 0; |
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} |
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static int k10temp_read_temp(struct device *dev, u32 attr, int channel, |
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long *val) |
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{ |
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struct k10temp_data *data = dev_get_drvdata(dev); |
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u32 regval; |
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switch (attr) { |
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case hwmon_temp_input: |
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switch (channel) { |
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case 0: /* Tctl */ |
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*val = get_raw_temp(data); |
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if (*val < 0) |
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*val = 0; |
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break; |
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case 1: /* Tdie */ |
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*val = get_raw_temp(data) - data->temp_offset; |
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if (*val < 0) |
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*val = 0; |
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break; |
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case 2 ... 9: /* Tccd{1-8} */ |
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amd_smn_read(amd_pci_dev_to_node_id(data->pdev), |
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ZEN_CCD_TEMP(data->ccd_offset, channel - 2), |
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®val); |
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*val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000; |
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break; |
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default: |
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return -EOPNOTSUPP; |
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} |
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break; |
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case hwmon_temp_max: |
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*val = 70 * 1000; |
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break; |
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case hwmon_temp_crit: |
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data->read_htcreg(data->pdev, ®val); |
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*val = ((regval >> 16) & 0x7f) * 500 + 52000; |
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break; |
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case hwmon_temp_crit_hyst: |
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data->read_htcreg(data->pdev, ®val); |
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*val = (((regval >> 16) & 0x7f) |
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- ((regval >> 24) & 0xf)) * 500 + 52000; |
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break; |
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default: |
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return -EOPNOTSUPP; |
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} |
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return 0; |
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} |
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static int k10temp_read(struct device *dev, enum hwmon_sensor_types type, |
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u32 attr, int channel, long *val) |
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{ |
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switch (type) { |
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case hwmon_temp: |
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return k10temp_read_temp(dev, attr, channel, val); |
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default: |
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return -EOPNOTSUPP; |
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} |
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} |
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static umode_t k10temp_is_visible(const void *_data, |
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enum hwmon_sensor_types type, |
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u32 attr, int channel) |
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{ |
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const struct k10temp_data *data = _data; |
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struct pci_dev *pdev = data->pdev; |
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u32 reg; |
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switch (type) { |
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case hwmon_temp: |
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switch (attr) { |
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case hwmon_temp_input: |
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if (!HAVE_TEMP(data, channel)) |
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return 0; |
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break; |
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case hwmon_temp_max: |
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if (channel || data->is_zen) |
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return 0; |
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break; |
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case hwmon_temp_crit: |
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case hwmon_temp_crit_hyst: |
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if (channel || !data->read_htcreg) |
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return 0; |
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pci_read_config_dword(pdev, |
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REG_NORTHBRIDGE_CAPABILITIES, |
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®); |
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if (!(reg & NB_CAP_HTC)) |
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return 0; |
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data->read_htcreg(data->pdev, ®); |
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if (!(reg & HTC_ENABLE)) |
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return 0; |
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break; |
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case hwmon_temp_label: |
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/* Show temperature labels only on Zen CPUs */ |
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if (!data->is_zen || !HAVE_TEMP(data, channel)) |
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return 0; |
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break; |
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default: |
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return 0; |
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} |
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break; |
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default: |
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return 0; |
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} |
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return 0444; |
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} |
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static bool has_erratum_319(struct pci_dev *pdev) |
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{ |
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u32 pkg_type, reg_dram_cfg; |
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if (boot_cpu_data.x86 != 0x10) |
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return false; |
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/* |
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* Erratum 319: The thermal sensor of Socket F/AM2+ processors |
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* may be unreliable. |
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*/ |
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pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK; |
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if (pkg_type == CPUID_PKGTYPE_F) |
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return true; |
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if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3) |
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return false; |
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/* DDR3 memory implies socket AM3, which is good */ |
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pci_bus_read_config_dword(pdev->bus, |
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PCI_DEVFN(PCI_SLOT(pdev->devfn), 2), |
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REG_DCT0_CONFIG_HIGH, ®_dram_cfg); |
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if (reg_dram_cfg & DDR3_MODE) |
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return false; |
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/* |
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* Unfortunately it is possible to run a socket AM3 CPU with DDR2 |
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* memory. We blacklist all the cores which do exist in socket AM2+ |
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* format. It still isn't perfect, as RB-C2 cores exist in both AM2+ |
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* and AM3 formats, but that's the best we can do. |
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*/ |
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return boot_cpu_data.x86_model < 4 || |
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(boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2); |
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} |
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static const struct hwmon_channel_info *k10temp_info[] = { |
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HWMON_CHANNEL_INFO(temp, |
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HWMON_T_INPUT | HWMON_T_MAX | |
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HWMON_T_CRIT | HWMON_T_CRIT_HYST | |
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HWMON_T_LABEL, |
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HWMON_T_INPUT | HWMON_T_LABEL, |
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HWMON_T_INPUT | HWMON_T_LABEL, |
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HWMON_T_INPUT | HWMON_T_LABEL, |
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HWMON_T_INPUT | HWMON_T_LABEL, |
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HWMON_T_INPUT | HWMON_T_LABEL, |
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HWMON_T_INPUT | HWMON_T_LABEL, |
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HWMON_T_INPUT | HWMON_T_LABEL, |
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HWMON_T_INPUT | HWMON_T_LABEL, |
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HWMON_T_INPUT | HWMON_T_LABEL), |
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NULL |
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}; |
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static const struct hwmon_ops k10temp_hwmon_ops = { |
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.is_visible = k10temp_is_visible, |
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.read = k10temp_read, |
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.read_string = k10temp_read_labels, |
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}; |
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static const struct hwmon_chip_info k10temp_chip_info = { |
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.ops = &k10temp_hwmon_ops, |
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.info = k10temp_info, |
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}; |
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static void k10temp_get_ccd_support(struct pci_dev *pdev, |
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struct k10temp_data *data, int limit) |
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{ |
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u32 regval; |
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int i; |
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for (i = 0; i < limit; i++) { |
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amd_smn_read(amd_pci_dev_to_node_id(pdev), |
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ZEN_CCD_TEMP(data->ccd_offset, i), ®val); |
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if (regval & ZEN_CCD_TEMP_VALID) |
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data->show_temp |= BIT(TCCD_BIT(i)); |
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} |
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} |
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static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
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{ |
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int unreliable = has_erratum_319(pdev); |
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struct device *dev = &pdev->dev; |
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struct k10temp_data *data; |
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struct device *hwmon_dev; |
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int i; |
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if (unreliable) { |
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if (!force) { |
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dev_err(dev, |
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"unreliable CPU thermal sensor; monitoring disabled\n"); |
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return -ENODEV; |
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} |
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dev_warn(dev, |
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"unreliable CPU thermal sensor; check erratum 319\n"); |
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} |
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
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if (!data) |
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return -ENOMEM; |
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data->pdev = pdev; |
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data->show_temp |= BIT(TCTL_BIT); /* Always show Tctl */ |
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if (boot_cpu_data.x86 == 0x15 && |
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((boot_cpu_data.x86_model & 0xf0) == 0x60 || |
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(boot_cpu_data.x86_model & 0xf0) == 0x70)) { |
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data->read_htcreg = read_htcreg_nb_f15; |
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data->read_tempreg = read_tempreg_nb_f15; |
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} else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) { |
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data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; |
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data->read_tempreg = read_tempreg_nb_zen; |
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data->is_zen = true; |
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switch (boot_cpu_data.x86_model) { |
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case 0x1: /* Zen */ |
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case 0x8: /* Zen+ */ |
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case 0x11: /* Zen APU */ |
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case 0x18: /* Zen+ APU */ |
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data->ccd_offset = 0x154; |
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k10temp_get_ccd_support(pdev, data, 4); |
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break; |
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case 0x31: /* Zen2 Threadripper */ |
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case 0x60: /* Renoir */ |
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case 0x68: /* Lucienne */ |
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case 0x71: /* Zen2 */ |
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data->ccd_offset = 0x154; |
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k10temp_get_ccd_support(pdev, data, 8); |
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break; |
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} |
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} else if (boot_cpu_data.x86 == 0x19) { |
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data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; |
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data->read_tempreg = read_tempreg_nb_zen; |
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data->is_zen = true; |
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switch (boot_cpu_data.x86_model) { |
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case 0x0 ... 0x1: /* Zen3 SP3/TR */ |
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case 0x21: /* Zen3 Ryzen Desktop */ |
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case 0x50 ... 0x5f: /* Green Sardine */ |
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data->ccd_offset = 0x154; |
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k10temp_get_ccd_support(pdev, data, 8); |
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break; |
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case 0x40 ... 0x4f: /* Yellow Carp */ |
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data->ccd_offset = 0x300; |
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k10temp_get_ccd_support(pdev, data, 8); |
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break; |
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} |
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} else { |
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data->read_htcreg = read_htcreg_pci; |
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data->read_tempreg = read_tempreg_pci; |
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} |
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for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) { |
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const struct tctl_offset *entry = &tctl_offset_table[i]; |
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|
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if (boot_cpu_data.x86 == entry->model && |
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strstr(boot_cpu_data.x86_model_id, entry->id)) { |
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data->show_temp |= BIT(TDIE_BIT); /* show Tdie */ |
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data->temp_offset = entry->offset; |
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break; |
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} |
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} |
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hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data, |
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&k10temp_chip_info, |
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NULL); |
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return PTR_ERR_OR_ZERO(hwmon_dev); |
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} |
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static const struct pci_device_id k10temp_id_table[] = { |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) }, |
|
{ PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(pci, k10temp_id_table); |
|
|
|
static struct pci_driver k10temp_driver = { |
|
.name = "k10temp", |
|
.id_table = k10temp_id_table, |
|
.probe = k10temp_probe, |
|
}; |
|
|
|
module_pci_driver(k10temp_driver);
|
|
|