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216 lines
5.7 KiB
216 lines
5.7 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* GPIO controller in LSI ZEVIO SoCs. |
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* |
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* Author: Fabian Vogt <[email protected]> |
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*/ |
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#include <linux/spinlock.h> |
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#include <linux/errno.h> |
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#include <linux/init.h> |
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#include <linux/bitops.h> |
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#include <linux/io.h> |
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#include <linux/of_device.h> |
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#include <linux/of_gpio.h> |
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#include <linux/slab.h> |
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#include <linux/gpio/driver.h> |
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/* |
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* Memory layout: |
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* This chip has four gpio sections, each controls 8 GPIOs. |
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* Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10. |
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* Disclaimer: Reverse engineered! |
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* For more information refer to: |
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* http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29 |
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* |
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* 0x00-0x3F: Section 0 |
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* +0x00: Masked interrupt status (read-only) |
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* +0x04: R: Interrupt status W: Reset interrupt status |
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* +0x08: R: Interrupt mask W: Mask interrupt |
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* +0x0C: W: Unmask interrupt (write-only) |
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* +0x10: Direction: I/O=1/0 |
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* +0x14: Output |
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* +0x18: Input (read-only) |
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* +0x20: R: Level interrupt W: Set as level interrupt |
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* 0x40-0x7F: Section 1 |
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* 0x80-0xBF: Section 2 |
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* 0xC0-0xFF: Section 3 |
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*/ |
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#define ZEVIO_GPIO_SECTION_SIZE 0x40 |
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/* Offsets to various registers */ |
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#define ZEVIO_GPIO_INT_MASKED_STATUS 0x00 |
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#define ZEVIO_GPIO_INT_STATUS 0x04 |
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#define ZEVIO_GPIO_INT_UNMASK 0x08 |
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#define ZEVIO_GPIO_INT_MASK 0x0C |
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#define ZEVIO_GPIO_DIRECTION 0x10 |
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#define ZEVIO_GPIO_OUTPUT 0x14 |
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#define ZEVIO_GPIO_INPUT 0x18 |
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#define ZEVIO_GPIO_INT_STICKY 0x20 |
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/* Bit number of GPIO in its section */ |
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#define ZEVIO_GPIO_BIT(gpio) (gpio&7) |
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struct zevio_gpio { |
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spinlock_t lock; |
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struct of_mm_gpio_chip chip; |
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}; |
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static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin, |
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unsigned port_offset) |
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{ |
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unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; |
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return readl(IOMEM(c->chip.regs + section_offset + port_offset)); |
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} |
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static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin, |
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unsigned port_offset, u32 val) |
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{ |
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unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE; |
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writel(val, IOMEM(c->chip.regs + section_offset + port_offset)); |
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} |
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/* Functions for struct gpio_chip */ |
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static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin) |
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{ |
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struct zevio_gpio *controller = gpiochip_get_data(chip); |
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u32 val, dir; |
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spin_lock(&controller->lock); |
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dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); |
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if (dir & BIT(ZEVIO_GPIO_BIT(pin))) |
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val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT); |
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else |
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val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); |
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spin_unlock(&controller->lock); |
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return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1; |
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} |
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static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value) |
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{ |
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struct zevio_gpio *controller = gpiochip_get_data(chip); |
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u32 val; |
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spin_lock(&controller->lock); |
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val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); |
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if (value) |
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val |= BIT(ZEVIO_GPIO_BIT(pin)); |
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else |
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val &= ~BIT(ZEVIO_GPIO_BIT(pin)); |
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zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); |
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spin_unlock(&controller->lock); |
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} |
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static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin) |
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{ |
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struct zevio_gpio *controller = gpiochip_get_data(chip); |
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u32 val; |
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spin_lock(&controller->lock); |
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val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); |
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val |= BIT(ZEVIO_GPIO_BIT(pin)); |
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zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val); |
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spin_unlock(&controller->lock); |
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return 0; |
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} |
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static int zevio_gpio_direction_output(struct gpio_chip *chip, |
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unsigned pin, int value) |
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{ |
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struct zevio_gpio *controller = gpiochip_get_data(chip); |
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u32 val; |
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spin_lock(&controller->lock); |
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val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); |
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if (value) |
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val |= BIT(ZEVIO_GPIO_BIT(pin)); |
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else |
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val &= ~BIT(ZEVIO_GPIO_BIT(pin)); |
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zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); |
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val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); |
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val &= ~BIT(ZEVIO_GPIO_BIT(pin)); |
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zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val); |
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spin_unlock(&controller->lock); |
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return 0; |
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} |
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static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin) |
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{ |
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/* |
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* TODO: Implement IRQs. |
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* Not implemented yet due to weird lockups |
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*/ |
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return -ENXIO; |
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} |
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static const struct gpio_chip zevio_gpio_chip = { |
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.direction_input = zevio_gpio_direction_input, |
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.direction_output = zevio_gpio_direction_output, |
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.set = zevio_gpio_set, |
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.get = zevio_gpio_get, |
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.to_irq = zevio_gpio_to_irq, |
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.base = 0, |
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.owner = THIS_MODULE, |
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.ngpio = 32, |
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.of_gpio_n_cells = 2, |
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}; |
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/* Initialization */ |
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static int zevio_gpio_probe(struct platform_device *pdev) |
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{ |
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struct zevio_gpio *controller; |
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int status, i; |
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controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL); |
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if (!controller) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, controller); |
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/* Copy our reference */ |
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controller->chip.gc = zevio_gpio_chip; |
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controller->chip.gc.parent = &pdev->dev; |
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status = of_mm_gpiochip_add_data(pdev->dev.of_node, |
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&(controller->chip), |
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controller); |
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if (status) { |
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dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status); |
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return status; |
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} |
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spin_lock_init(&controller->lock); |
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/* Disable interrupts, they only cause errors */ |
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for (i = 0; i < controller->chip.gc.ngpio; i += 8) |
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zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF); |
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dev_dbg(controller->chip.gc.parent, "ZEVIO GPIO controller set up!\n"); |
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return 0; |
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} |
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static const struct of_device_id zevio_gpio_of_match[] = { |
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{ .compatible = "lsi,zevio-gpio", }, |
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{ }, |
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}; |
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static struct platform_driver zevio_gpio_driver = { |
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.driver = { |
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.name = "gpio-zevio", |
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.of_match_table = zevio_gpio_of_match, |
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.suppress_bind_attrs = true, |
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}, |
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.probe = zevio_gpio_probe, |
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}; |
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builtin_platform_driver(zevio_gpio_driver);
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