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443 lines
12 KiB
443 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2003-2015 Broadcom Corporation |
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* All Rights Reserved |
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*/ |
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#include <linux/gpio/driver.h> |
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#include <linux/platform_device.h> |
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#include <linux/of_device.h> |
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#include <linux/module.h> |
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#include <linux/irq.h> |
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#include <linux/interrupt.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/acpi.h> |
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/* |
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* XLP GPIO has multiple 32 bit registers for each feature where each register |
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* controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96 |
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* require 3 32-bit registers for each feature. |
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* Here we only define offset of the first register for each feature. Offset of |
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* the registers for pins greater than 32 can be calculated as following(Use |
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* GPIO_INT_STAT as example): |
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* |
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* offset = (gpio / XLP_GPIO_REGSZ) * 4; |
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* reg_addr = addr + offset; |
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* |
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* where addr is base address of the that feature register and gpio is the pin. |
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*/ |
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#define GPIO_OUTPUT_EN 0x00 |
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#define GPIO_PADDRV 0x08 |
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#define GPIO_INT_EN00 0x18 |
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#define GPIO_INT_EN10 0x20 |
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#define GPIO_INT_EN20 0x28 |
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#define GPIO_INT_EN30 0x30 |
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#define GPIO_INT_POL 0x38 |
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#define GPIO_INT_TYPE 0x40 |
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#define GPIO_INT_STAT 0x48 |
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#define GPIO_9XX_BYTESWAP 0X00 |
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#define GPIO_9XX_CTRL 0X04 |
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#define GPIO_9XX_OUTPUT_EN 0x14 |
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#define GPIO_9XX_PADDRV 0x24 |
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/* |
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* Only for 4 interrupt enable reg are defined for now, |
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* total reg available are 12. |
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*/ |
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#define GPIO_9XX_INT_EN00 0x44 |
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#define GPIO_9XX_INT_EN10 0x54 |
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#define GPIO_9XX_INT_EN20 0x64 |
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#define GPIO_9XX_INT_EN30 0x74 |
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#define GPIO_9XX_INT_POL 0x104 |
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#define GPIO_9XX_INT_TYPE 0x114 |
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#define GPIO_9XX_INT_STAT 0x124 |
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#define GPIO_3XX_INT_EN00 0x18 |
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#define GPIO_3XX_INT_EN10 0x20 |
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#define GPIO_3XX_INT_EN20 0x28 |
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#define GPIO_3XX_INT_EN30 0x30 |
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#define GPIO_3XX_INT_POL 0x78 |
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#define GPIO_3XX_INT_TYPE 0x80 |
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#define GPIO_3XX_INT_STAT 0x88 |
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/* Interrupt type register mask */ |
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#define XLP_GPIO_IRQ_TYPE_LVL 0x0 |
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#define XLP_GPIO_IRQ_TYPE_EDGE 0x1 |
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/* Interrupt polarity register mask */ |
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#define XLP_GPIO_IRQ_POL_HIGH 0x0 |
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#define XLP_GPIO_IRQ_POL_LOW 0x1 |
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#define XLP_GPIO_REGSZ 32 |
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#define XLP_GPIO_IRQ_BASE 768 |
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#define XLP_MAX_NR_GPIO 96 |
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/* XLP variants supported by this driver */ |
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enum { |
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XLP_GPIO_VARIANT_XLP832 = 1, |
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XLP_GPIO_VARIANT_XLP316, |
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XLP_GPIO_VARIANT_XLP208, |
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XLP_GPIO_VARIANT_XLP980, |
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XLP_GPIO_VARIANT_XLP532, |
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GPIO_VARIANT_VULCAN |
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}; |
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struct xlp_gpio_priv { |
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struct gpio_chip chip; |
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DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO); |
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void __iomem *gpio_intr_en; /* pointer to first intr enable reg */ |
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void __iomem *gpio_intr_stat; /* pointer to first intr status reg */ |
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void __iomem *gpio_intr_type; /* pointer to first intr type reg */ |
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void __iomem *gpio_intr_pol; /* pointer to first intr polarity reg */ |
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void __iomem *gpio_out_en; /* pointer to first output enable reg */ |
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void __iomem *gpio_paddrv; /* pointer to first pad drive reg */ |
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spinlock_t lock; |
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}; |
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static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio) |
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{ |
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u32 pos, regset; |
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pos = gpio % XLP_GPIO_REGSZ; |
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regset = (gpio / XLP_GPIO_REGSZ) * 4; |
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return !!(readl(addr + regset) & BIT(pos)); |
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} |
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static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state) |
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{ |
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u32 value, pos, regset; |
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pos = gpio % XLP_GPIO_REGSZ; |
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regset = (gpio / XLP_GPIO_REGSZ) * 4; |
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value = readl(addr + regset); |
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if (state) |
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value |= BIT(pos); |
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else |
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value &= ~BIT(pos); |
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writel(value, addr + regset); |
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} |
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static void xlp_gpio_irq_disable(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
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unsigned long flags; |
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spin_lock_irqsave(&priv->lock, flags); |
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xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); |
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__clear_bit(d->hwirq, priv->gpio_enabled_mask); |
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spin_unlock_irqrestore(&priv->lock, flags); |
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} |
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static void xlp_gpio_irq_mask_ack(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
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unsigned long flags; |
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spin_lock_irqsave(&priv->lock, flags); |
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xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0); |
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xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1); |
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__clear_bit(d->hwirq, priv->gpio_enabled_mask); |
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spin_unlock_irqrestore(&priv->lock, flags); |
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} |
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static void xlp_gpio_irq_unmask(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
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unsigned long flags; |
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spin_lock_irqsave(&priv->lock, flags); |
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xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1); |
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__set_bit(d->hwirq, priv->gpio_enabled_mask); |
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spin_unlock_irqrestore(&priv->lock, flags); |
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} |
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static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
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int pol, irq_type; |
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switch (type) { |
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case IRQ_TYPE_EDGE_RISING: |
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irq_type = XLP_GPIO_IRQ_TYPE_EDGE; |
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pol = XLP_GPIO_IRQ_POL_HIGH; |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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irq_type = XLP_GPIO_IRQ_TYPE_EDGE; |
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pol = XLP_GPIO_IRQ_POL_LOW; |
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break; |
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case IRQ_TYPE_LEVEL_HIGH: |
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irq_type = XLP_GPIO_IRQ_TYPE_LVL; |
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pol = XLP_GPIO_IRQ_POL_HIGH; |
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break; |
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case IRQ_TYPE_LEVEL_LOW: |
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irq_type = XLP_GPIO_IRQ_TYPE_LVL; |
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pol = XLP_GPIO_IRQ_POL_LOW; |
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break; |
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default: |
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return -EINVAL; |
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} |
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xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type); |
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xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol); |
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return 0; |
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} |
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static struct irq_chip xlp_gpio_irq_chip = { |
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.name = "XLP-GPIO", |
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.irq_mask_ack = xlp_gpio_irq_mask_ack, |
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.irq_disable = xlp_gpio_irq_disable, |
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.irq_set_type = xlp_gpio_set_irq_type, |
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.irq_unmask = xlp_gpio_irq_unmask, |
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.flags = IRQCHIP_ONESHOT_SAFE, |
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}; |
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static void xlp_gpio_generic_handler(struct irq_desc *desc) |
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{ |
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struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc); |
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struct irq_chip *irqchip = irq_desc_get_chip(desc); |
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int gpio, regoff; |
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u32 gpio_stat; |
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regoff = -1; |
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gpio_stat = 0; |
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chained_irq_enter(irqchip, desc); |
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for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) { |
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if (regoff != gpio / XLP_GPIO_REGSZ) { |
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regoff = gpio / XLP_GPIO_REGSZ; |
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gpio_stat = readl(priv->gpio_intr_stat + regoff * 4); |
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} |
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if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ)) |
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generic_handle_domain_irq(priv->chip.irq.domain, gpio); |
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} |
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chained_irq_exit(irqchip, desc); |
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} |
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static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state) |
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{ |
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struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
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BUG_ON(gpio >= gc->ngpio); |
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xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1); |
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return 0; |
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} |
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static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio) |
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{ |
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struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
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BUG_ON(gpio >= gc->ngpio); |
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xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0); |
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return 0; |
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} |
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static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio) |
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{ |
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struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
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BUG_ON(gpio >= gc->ngpio); |
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return xlp_gpio_get_reg(priv->gpio_paddrv, gpio); |
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} |
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static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state) |
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{ |
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struct xlp_gpio_priv *priv = gpiochip_get_data(gc); |
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BUG_ON(gpio >= gc->ngpio); |
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xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state); |
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} |
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static const struct of_device_id xlp_gpio_of_ids[] = { |
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{ |
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.compatible = "netlogic,xlp832-gpio", |
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.data = (void *)XLP_GPIO_VARIANT_XLP832, |
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}, |
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{ |
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.compatible = "netlogic,xlp316-gpio", |
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.data = (void *)XLP_GPIO_VARIANT_XLP316, |
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}, |
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{ |
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.compatible = "netlogic,xlp208-gpio", |
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.data = (void *)XLP_GPIO_VARIANT_XLP208, |
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}, |
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{ |
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.compatible = "netlogic,xlp980-gpio", |
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.data = (void *)XLP_GPIO_VARIANT_XLP980, |
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}, |
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{ |
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.compatible = "netlogic,xlp532-gpio", |
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.data = (void *)XLP_GPIO_VARIANT_XLP532, |
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}, |
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{ |
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.compatible = "brcm,vulcan-gpio", |
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.data = (void *)GPIO_VARIANT_VULCAN, |
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}, |
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{ /* sentinel */ }, |
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}; |
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MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids); |
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static int xlp_gpio_probe(struct platform_device *pdev) |
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{ |
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struct gpio_chip *gc; |
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struct gpio_irq_chip *girq; |
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struct xlp_gpio_priv *priv; |
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void __iomem *gpio_base; |
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int irq_base, irq, err; |
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int ngpio; |
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u32 soc_type; |
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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gpio_base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(gpio_base)) |
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return PTR_ERR(gpio_base); |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) |
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return irq; |
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if (pdev->dev.of_node) { |
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soc_type = (uintptr_t)of_device_get_match_data(&pdev->dev); |
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} else { |
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const struct acpi_device_id *acpi_id; |
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acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, |
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&pdev->dev); |
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if (!acpi_id || !acpi_id->driver_data) { |
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dev_err(&pdev->dev, "Unable to match ACPI ID\n"); |
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return -ENODEV; |
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} |
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soc_type = (uintptr_t) acpi_id->driver_data; |
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} |
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switch (soc_type) { |
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case XLP_GPIO_VARIANT_XLP832: |
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priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN; |
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priv->gpio_paddrv = gpio_base + GPIO_PADDRV; |
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priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT; |
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priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE; |
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priv->gpio_intr_pol = gpio_base + GPIO_INT_POL; |
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priv->gpio_intr_en = gpio_base + GPIO_INT_EN00; |
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ngpio = 41; |
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break; |
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case XLP_GPIO_VARIANT_XLP208: |
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case XLP_GPIO_VARIANT_XLP316: |
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priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN; |
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priv->gpio_paddrv = gpio_base + GPIO_PADDRV; |
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priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT; |
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priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE; |
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priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL; |
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priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00; |
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ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57; |
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break; |
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case XLP_GPIO_VARIANT_XLP980: |
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case XLP_GPIO_VARIANT_XLP532: |
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case GPIO_VARIANT_VULCAN: |
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priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN; |
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priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV; |
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priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT; |
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priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE; |
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priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL; |
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priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00; |
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if (soc_type == XLP_GPIO_VARIANT_XLP980) |
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ngpio = 66; |
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else if (soc_type == XLP_GPIO_VARIANT_XLP532) |
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ngpio = 67; |
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else |
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ngpio = 70; |
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break; |
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default: |
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dev_err(&pdev->dev, "Unknown Processor type!\n"); |
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return -ENODEV; |
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} |
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bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO); |
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gc = &priv->chip; |
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gc->owner = THIS_MODULE; |
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gc->label = dev_name(&pdev->dev); |
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gc->base = 0; |
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gc->parent = &pdev->dev; |
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gc->ngpio = ngpio; |
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gc->of_node = pdev->dev.of_node; |
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gc->direction_output = xlp_gpio_dir_output; |
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gc->direction_input = xlp_gpio_dir_input; |
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gc->set = xlp_gpio_set; |
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gc->get = xlp_gpio_get; |
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spin_lock_init(&priv->lock); |
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/* XLP(MIPS) has fixed range for GPIO IRQs, Vulcan(ARM64) does not */ |
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if (soc_type != GPIO_VARIANT_VULCAN) { |
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irq_base = devm_irq_alloc_descs(&pdev->dev, -1, |
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XLP_GPIO_IRQ_BASE, |
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gc->ngpio, 0); |
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if (irq_base < 0) { |
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dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n"); |
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return irq_base; |
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} |
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} else { |
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irq_base = 0; |
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} |
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girq = &gc->irq; |
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girq->chip = &xlp_gpio_irq_chip; |
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girq->parent_handler = xlp_gpio_generic_handler; |
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girq->num_parents = 1; |
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girq->parents = devm_kcalloc(&pdev->dev, 1, |
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sizeof(*girq->parents), |
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GFP_KERNEL); |
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if (!girq->parents) |
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return -ENOMEM; |
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girq->parents[0] = irq; |
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girq->first = irq_base; |
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girq->default_type = IRQ_TYPE_NONE; |
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girq->handler = handle_level_irq; |
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err = gpiochip_add_data(gc, priv); |
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if (err < 0) |
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return err; |
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dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio); |
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return 0; |
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} |
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#ifdef CONFIG_ACPI |
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static const struct acpi_device_id xlp_gpio_acpi_match[] = { |
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{ "BRCM9006", GPIO_VARIANT_VULCAN }, |
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{ "CAV9006", GPIO_VARIANT_VULCAN }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(acpi, xlp_gpio_acpi_match); |
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#endif |
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static struct platform_driver xlp_gpio_driver = { |
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.driver = { |
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.name = "xlp-gpio", |
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.of_match_table = xlp_gpio_of_ids, |
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.acpi_match_table = ACPI_PTR(xlp_gpio_acpi_match), |
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}, |
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.probe = xlp_gpio_probe, |
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}; |
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module_platform_driver(xlp_gpio_driver); |
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MODULE_AUTHOR("Kamlakant Patel <[email protected]>"); |
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MODULE_AUTHOR("Ganesan Ramalingam <[email protected]>"); |
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MODULE_DESCRIPTION("Netlogic XLP GPIO Driver"); |
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MODULE_LICENSE("GPL v2");
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