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319 lines
8.5 KiB
319 lines
8.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2017 Broadcom |
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*/ |
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#include <linux/gpio/driver.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/spinlock.h> |
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#define IPROC_CCA_INT_F_GPIOINT BIT(0) |
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#define IPROC_CCA_INT_STS 0x20 |
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#define IPROC_CCA_INT_MASK 0x24 |
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#define IPROC_GPIO_CCA_DIN 0x0 |
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#define IPROC_GPIO_CCA_DOUT 0x4 |
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#define IPROC_GPIO_CCA_OUT_EN 0x8 |
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#define IPROC_GPIO_CCA_INT_LEVEL 0x10 |
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#define IPROC_GPIO_CCA_INT_LEVEL_MASK 0x14 |
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#define IPROC_GPIO_CCA_INT_EVENT 0x18 |
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#define IPROC_GPIO_CCA_INT_EVENT_MASK 0x1C |
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#define IPROC_GPIO_CCA_INT_EDGE 0x24 |
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struct iproc_gpio_chip { |
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struct irq_chip irqchip; |
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struct gpio_chip gc; |
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spinlock_t lock; |
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struct device *dev; |
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void __iomem *base; |
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void __iomem *intr; |
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}; |
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static inline struct iproc_gpio_chip * |
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to_iproc_gpio(struct gpio_chip *gc) |
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{ |
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return container_of(gc, struct iproc_gpio_chip, gc); |
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} |
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static void iproc_gpio_irq_ack(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct iproc_gpio_chip *chip = to_iproc_gpio(gc); |
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int pin = d->hwirq; |
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unsigned long flags; |
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u32 irq = d->irq; |
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u32 irq_type, event_status = 0; |
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spin_lock_irqsave(&chip->lock, flags); |
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irq_type = irq_get_trigger_type(irq); |
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if (irq_type & IRQ_TYPE_EDGE_BOTH) { |
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event_status |= BIT(pin); |
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writel_relaxed(event_status, |
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chip->base + IPROC_GPIO_CCA_INT_EVENT); |
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} |
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spin_unlock_irqrestore(&chip->lock, flags); |
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} |
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static void iproc_gpio_irq_unmask(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct iproc_gpio_chip *chip = to_iproc_gpio(gc); |
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int pin = d->hwirq; |
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unsigned long flags; |
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u32 irq = d->irq; |
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u32 int_mask, irq_type, event_mask; |
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spin_lock_irqsave(&chip->lock, flags); |
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irq_type = irq_get_trigger_type(irq); |
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event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); |
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int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); |
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if (irq_type & IRQ_TYPE_EDGE_BOTH) { |
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event_mask |= 1 << pin; |
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writel_relaxed(event_mask, |
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chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); |
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} else { |
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int_mask |= 1 << pin; |
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writel_relaxed(int_mask, |
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chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); |
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} |
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spin_unlock_irqrestore(&chip->lock, flags); |
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} |
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static void iproc_gpio_irq_mask(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct iproc_gpio_chip *chip = to_iproc_gpio(gc); |
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int pin = d->hwirq; |
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unsigned long flags; |
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u32 irq = d->irq; |
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u32 irq_type, int_mask, event_mask; |
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spin_lock_irqsave(&chip->lock, flags); |
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irq_type = irq_get_trigger_type(irq); |
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event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); |
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int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); |
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if (irq_type & IRQ_TYPE_EDGE_BOTH) { |
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event_mask &= ~BIT(pin); |
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writel_relaxed(event_mask, |
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chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); |
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} else { |
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int_mask &= ~BIT(pin); |
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writel_relaxed(int_mask, |
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chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); |
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} |
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spin_unlock_irqrestore(&chip->lock, flags); |
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} |
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static int iproc_gpio_irq_set_type(struct irq_data *d, u32 type) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct iproc_gpio_chip *chip = to_iproc_gpio(gc); |
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int pin = d->hwirq; |
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unsigned long flags; |
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u32 irq = d->irq; |
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u32 event_pol, int_pol; |
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int ret = 0; |
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spin_lock_irqsave(&chip->lock, flags); |
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switch (type & IRQ_TYPE_SENSE_MASK) { |
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case IRQ_TYPE_EDGE_RISING: |
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event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE); |
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event_pol &= ~BIT(pin); |
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writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE); |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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event_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EDGE); |
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event_pol |= BIT(pin); |
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writel_relaxed(event_pol, chip->base + IPROC_GPIO_CCA_INT_EDGE); |
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break; |
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case IRQ_TYPE_LEVEL_HIGH: |
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int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL); |
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int_pol &= ~BIT(pin); |
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writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL); |
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break; |
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case IRQ_TYPE_LEVEL_LOW: |
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int_pol = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL); |
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int_pol |= BIT(pin); |
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writel_relaxed(int_pol, chip->base + IPROC_GPIO_CCA_INT_LEVEL); |
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break; |
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default: |
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/* should not come here */ |
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ret = -EINVAL; |
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goto out_unlock; |
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} |
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if (type & IRQ_TYPE_LEVEL_MASK) |
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irq_set_handler_locked(irq_get_irq_data(irq), handle_level_irq); |
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else if (type & IRQ_TYPE_EDGE_BOTH) |
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irq_set_handler_locked(irq_get_irq_data(irq), handle_edge_irq); |
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out_unlock: |
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spin_unlock_irqrestore(&chip->lock, flags); |
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return ret; |
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} |
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static irqreturn_t iproc_gpio_irq_handler(int irq, void *data) |
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{ |
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struct gpio_chip *gc = (struct gpio_chip *)data; |
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struct iproc_gpio_chip *chip = to_iproc_gpio(gc); |
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int bit; |
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unsigned long int_bits = 0; |
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u32 int_status; |
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/* go through the entire GPIOs and handle all interrupts */ |
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int_status = readl_relaxed(chip->intr + IPROC_CCA_INT_STS); |
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if (int_status & IPROC_CCA_INT_F_GPIOINT) { |
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u32 event, level; |
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/* Get level and edge interrupts */ |
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event = |
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readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); |
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event &= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT); |
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level = readl_relaxed(chip->base + IPROC_GPIO_CCA_DIN); |
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level ^= readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL); |
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level &= |
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readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); |
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int_bits = level | event; |
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for_each_set_bit(bit, &int_bits, gc->ngpio) |
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generic_handle_domain_irq(gc->irq.domain, bit); |
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} |
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return int_bits ? IRQ_HANDLED : IRQ_NONE; |
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} |
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static int iproc_gpio_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *dn = pdev->dev.of_node; |
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struct iproc_gpio_chip *chip; |
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u32 num_gpios; |
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int irq, ret; |
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chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); |
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if (!chip) |
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return -ENOMEM; |
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chip->dev = dev; |
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platform_set_drvdata(pdev, chip); |
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spin_lock_init(&chip->lock); |
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chip->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(chip->base)) |
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return PTR_ERR(chip->base); |
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ret = bgpio_init(&chip->gc, dev, 4, |
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chip->base + IPROC_GPIO_CCA_DIN, |
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chip->base + IPROC_GPIO_CCA_DOUT, |
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NULL, |
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chip->base + IPROC_GPIO_CCA_OUT_EN, |
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NULL, |
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0); |
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if (ret) { |
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dev_err(dev, "unable to init GPIO chip\n"); |
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return ret; |
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} |
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chip->gc.label = dev_name(dev); |
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if (of_property_read_u32(dn, "ngpios", &num_gpios)) |
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chip->gc.ngpio = num_gpios; |
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irq = platform_get_irq(pdev, 0); |
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if (irq > 0) { |
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struct gpio_irq_chip *girq; |
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struct irq_chip *irqc; |
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u32 val; |
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irqc = &chip->irqchip; |
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irqc->name = dev_name(dev); |
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irqc->irq_ack = iproc_gpio_irq_ack; |
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irqc->irq_mask = iproc_gpio_irq_mask; |
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irqc->irq_unmask = iproc_gpio_irq_unmask; |
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irqc->irq_set_type = iproc_gpio_irq_set_type; |
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chip->intr = devm_platform_ioremap_resource(pdev, 1); |
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if (IS_ERR(chip->intr)) |
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return PTR_ERR(chip->intr); |
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/* Enable GPIO interrupts for CCA GPIO */ |
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val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK); |
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val |= IPROC_CCA_INT_F_GPIOINT; |
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writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK); |
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/* |
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* Directly request the irq here instead of passing |
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* a flow-handler because the irq is shared. |
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*/ |
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ret = devm_request_irq(dev, irq, iproc_gpio_irq_handler, |
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IRQF_SHARED, chip->gc.label, &chip->gc); |
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if (ret) { |
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dev_err(dev, "Fail to request IRQ%d: %d\n", irq, ret); |
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return ret; |
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} |
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girq = &chip->gc.irq; |
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girq->chip = irqc; |
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/* This will let us handle the parent IRQ in the driver */ |
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girq->parent_handler = NULL; |
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girq->num_parents = 0; |
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girq->parents = NULL; |
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girq->default_type = IRQ_TYPE_NONE; |
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girq->handler = handle_simple_irq; |
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} |
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ret = devm_gpiochip_add_data(dev, &chip->gc, chip); |
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if (ret) { |
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dev_err(dev, "unable to add GPIO chip\n"); |
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return ret; |
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} |
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return 0; |
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} |
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static int iproc_gpio_remove(struct platform_device *pdev) |
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{ |
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struct iproc_gpio_chip *chip; |
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chip = platform_get_drvdata(pdev); |
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if (!chip) |
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return -ENODEV; |
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if (chip->intr) { |
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u32 val; |
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val = readl_relaxed(chip->intr + IPROC_CCA_INT_MASK); |
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val &= ~IPROC_CCA_INT_F_GPIOINT; |
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writel_relaxed(val, chip->intr + IPROC_CCA_INT_MASK); |
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} |
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return 0; |
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} |
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static const struct of_device_id bcm_iproc_gpio_of_match[] = { |
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{ .compatible = "brcm,iproc-gpio-cca" }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, bcm_iproc_gpio_of_match); |
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static struct platform_driver bcm_iproc_gpio_driver = { |
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.driver = { |
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.name = "iproc-xgs-gpio", |
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.of_match_table = bcm_iproc_gpio_of_match, |
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}, |
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.probe = iproc_gpio_probe, |
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.remove = iproc_gpio_remove, |
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}; |
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module_platform_driver(bcm_iproc_gpio_driver); |
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MODULE_DESCRIPTION("XGS IPROC GPIO driver"); |
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MODULE_LICENSE("GPL v2");
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