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279 lines
7.3 KiB
279 lines
7.3 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* SYSCON GPIO driver |
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* |
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* Copyright (C) 2014 Alexander Shiyan <[email protected]> |
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*/ |
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#include <linux/err.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/mfd/syscon.h> |
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#define GPIO_SYSCON_FEAT_IN BIT(0) |
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#define GPIO_SYSCON_FEAT_OUT BIT(1) |
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#define GPIO_SYSCON_FEAT_DIR BIT(2) |
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/* SYSCON driver is designed to use 32-bit wide registers */ |
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#define SYSCON_REG_SIZE (4) |
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#define SYSCON_REG_BITS (SYSCON_REG_SIZE * 8) |
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/** |
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* struct syscon_gpio_data - Configuration for the device. |
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* @compatible: SYSCON driver compatible string. |
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* @flags: Set of GPIO_SYSCON_FEAT_ flags: |
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* GPIO_SYSCON_FEAT_IN: GPIOs supports input, |
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* GPIO_SYSCON_FEAT_OUT: GPIOs supports output, |
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* GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction. |
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* @bit_count: Number of bits used as GPIOs. |
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* @dat_bit_offset: Offset (in bits) to the first GPIO bit. |
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* @dir_bit_offset: Optional offset (in bits) to the first bit to switch |
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* GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag). |
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* @set: HW specific callback to assigns output value |
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* for signal "offset" |
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*/ |
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struct syscon_gpio_data { |
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const char *compatible; |
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unsigned int flags; |
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unsigned int bit_count; |
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unsigned int dat_bit_offset; |
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unsigned int dir_bit_offset; |
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void (*set)(struct gpio_chip *chip, |
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unsigned offset, int value); |
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}; |
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struct syscon_gpio_priv { |
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struct gpio_chip chip; |
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struct regmap *syscon; |
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const struct syscon_gpio_data *data; |
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u32 dreg_offset; |
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u32 dir_reg_offset; |
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}; |
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static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct syscon_gpio_priv *priv = gpiochip_get_data(chip); |
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unsigned int val, offs; |
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int ret; |
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offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; |
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ret = regmap_read(priv->syscon, |
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(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val); |
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if (ret) |
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return ret; |
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return !!(val & BIT(offs % SYSCON_REG_BITS)); |
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} |
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static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val) |
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{ |
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struct syscon_gpio_priv *priv = gpiochip_get_data(chip); |
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unsigned int offs; |
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offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; |
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regmap_update_bits(priv->syscon, |
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(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, |
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BIT(offs % SYSCON_REG_BITS), |
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val ? BIT(offs % SYSCON_REG_BITS) : 0); |
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} |
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static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct syscon_gpio_priv *priv = gpiochip_get_data(chip); |
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if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) { |
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unsigned int offs; |
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offs = priv->dir_reg_offset + |
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priv->data->dir_bit_offset + offset; |
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regmap_update_bits(priv->syscon, |
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(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, |
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BIT(offs % SYSCON_REG_BITS), 0); |
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} |
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return 0; |
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} |
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static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val) |
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{ |
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struct syscon_gpio_priv *priv = gpiochip_get_data(chip); |
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if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) { |
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unsigned int offs; |
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offs = priv->dir_reg_offset + |
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priv->data->dir_bit_offset + offset; |
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regmap_update_bits(priv->syscon, |
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(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, |
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BIT(offs % SYSCON_REG_BITS), |
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BIT(offs % SYSCON_REG_BITS)); |
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} |
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chip->set(chip, offset, val); |
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return 0; |
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} |
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static const struct syscon_gpio_data clps711x_mctrl_gpio = { |
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/* ARM CLPS711X SYSFLG1 Bits 8-10 */ |
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.compatible = "cirrus,ep7209-syscon1", |
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.flags = GPIO_SYSCON_FEAT_IN, |
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.bit_count = 3, |
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.dat_bit_offset = 0x40 * 8 + 8, |
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}; |
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static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset, |
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int val) |
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{ |
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struct syscon_gpio_priv *priv = gpiochip_get_data(chip); |
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unsigned int offs; |
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u8 bit; |
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u32 data; |
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int ret; |
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offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; |
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bit = offs % SYSCON_REG_BITS; |
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data = (val ? BIT(bit) : 0) | BIT(bit + 16); |
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ret = regmap_write(priv->syscon, |
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(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, |
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data); |
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if (ret < 0) |
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dev_err(chip->parent, "gpio write failed ret(%d)\n", ret); |
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} |
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static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = { |
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/* RK3328 GPIO_MUTE is an output only pin at GRF_SOC_CON10[1] */ |
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.flags = GPIO_SYSCON_FEAT_OUT, |
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.bit_count = 1, |
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.dat_bit_offset = 0x0428 * 8 + 1, |
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.set = rockchip_gpio_set, |
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}; |
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#define KEYSTONE_LOCK_BIT BIT(0) |
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static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val) |
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{ |
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struct syscon_gpio_priv *priv = gpiochip_get_data(chip); |
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unsigned int offs; |
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int ret; |
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offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; |
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if (!val) |
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return; |
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ret = regmap_update_bits( |
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priv->syscon, |
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(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, |
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BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT, |
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BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT); |
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if (ret < 0) |
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dev_err(chip->parent, "gpio write failed ret(%d)\n", ret); |
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} |
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static const struct syscon_gpio_data keystone_dsp_gpio = { |
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/* ARM Keystone 2 */ |
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.compatible = NULL, |
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.flags = GPIO_SYSCON_FEAT_OUT, |
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.bit_count = 28, |
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.dat_bit_offset = 4, |
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.set = keystone_gpio_set, |
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}; |
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static const struct of_device_id syscon_gpio_ids[] = { |
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{ |
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.compatible = "cirrus,ep7209-mctrl-gpio", |
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.data = &clps711x_mctrl_gpio, |
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}, |
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{ |
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.compatible = "ti,keystone-dsp-gpio", |
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.data = &keystone_dsp_gpio, |
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}, |
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{ |
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.compatible = "rockchip,rk3328-grf-gpio", |
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.data = &rockchip_rk3328_gpio_mute, |
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}, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, syscon_gpio_ids); |
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static int syscon_gpio_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct syscon_gpio_priv *priv; |
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struct device_node *np = dev->of_node; |
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int ret; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->data = of_device_get_match_data(dev); |
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if (priv->data->compatible) { |
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priv->syscon = syscon_regmap_lookup_by_compatible( |
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priv->data->compatible); |
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if (IS_ERR(priv->syscon)) |
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return PTR_ERR(priv->syscon); |
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} else { |
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priv->syscon = |
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syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev"); |
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if (IS_ERR(priv->syscon) && np->parent) |
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priv->syscon = syscon_node_to_regmap(np->parent); |
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if (IS_ERR(priv->syscon)) |
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return PTR_ERR(priv->syscon); |
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ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1, |
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&priv->dreg_offset); |
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if (ret) |
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dev_err(dev, "can't read the data register offset!\n"); |
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priv->dreg_offset <<= 3; |
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ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2, |
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&priv->dir_reg_offset); |
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if (ret) |
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dev_dbg(dev, "can't read the dir register offset!\n"); |
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priv->dir_reg_offset <<= 3; |
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} |
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priv->chip.parent = dev; |
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priv->chip.owner = THIS_MODULE; |
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priv->chip.label = dev_name(dev); |
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priv->chip.base = -1; |
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priv->chip.ngpio = priv->data->bit_count; |
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priv->chip.get = syscon_gpio_get; |
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if (priv->data->flags & GPIO_SYSCON_FEAT_IN) |
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priv->chip.direction_input = syscon_gpio_dir_in; |
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if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) { |
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priv->chip.set = priv->data->set ? : syscon_gpio_set; |
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priv->chip.direction_output = syscon_gpio_dir_out; |
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} |
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platform_set_drvdata(pdev, priv); |
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return devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); |
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} |
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static struct platform_driver syscon_gpio_driver = { |
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.driver = { |
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.name = "gpio-syscon", |
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.of_match_table = syscon_gpio_ids, |
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}, |
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.probe = syscon_gpio_probe, |
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}; |
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module_platform_driver(syscon_gpio_driver); |
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MODULE_AUTHOR("Alexander Shiyan <[email protected]>"); |
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MODULE_DESCRIPTION("SYSCON GPIO driver"); |
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MODULE_LICENSE("GPL");
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