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541 lines
14 KiB
541 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) ST-Ericsson SA 2010 |
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* |
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* Author: Rabin Vincent <[email protected]> for ST-Ericsson |
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*/ |
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|
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#include <linux/init.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/interrupt.h> |
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#include <linux/of.h> |
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#include <linux/mfd/stmpe.h> |
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#include <linux/seq_file.h> |
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#include <linux/bitops.h> |
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|
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/* |
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* These registers are modified under the irq bus lock and cached to avoid |
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* unnecessary writes in bus_sync_unlock. |
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*/ |
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enum { REG_RE, REG_FE, REG_IE }; |
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enum { LSB, CSB, MSB }; |
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#define CACHE_NR_REGS 3 |
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/* No variant has more than 24 GPIOs */ |
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#define CACHE_NR_BANKS (24 / 8) |
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struct stmpe_gpio { |
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struct gpio_chip chip; |
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struct stmpe *stmpe; |
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struct device *dev; |
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struct mutex irq_lock; |
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u32 norequest_mask; |
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/* Caches of interrupt control registers for bus_lock */ |
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u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; |
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u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; |
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}; |
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static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
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struct stmpe *stmpe = stmpe_gpio->stmpe; |
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u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)]; |
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u8 mask = BIT(offset % 8); |
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int ret; |
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ret = stmpe_reg_read(stmpe, reg); |
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if (ret < 0) |
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return ret; |
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return !!(ret & mask); |
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} |
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static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val) |
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{ |
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
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struct stmpe *stmpe = stmpe_gpio->stmpe; |
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int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB; |
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u8 reg = stmpe->regs[which + (offset / 8)]; |
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u8 mask = BIT(offset % 8); |
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/* |
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* Some variants have single register for gpio set/clear functionality. |
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* For them we need to write 0 to clear and 1 to set. |
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*/ |
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if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB]) |
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stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); |
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else |
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stmpe_reg_write(stmpe, reg, mask); |
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} |
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static int stmpe_gpio_get_direction(struct gpio_chip *chip, |
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unsigned offset) |
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{ |
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
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struct stmpe *stmpe = stmpe_gpio->stmpe; |
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u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8); |
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u8 mask = BIT(offset % 8); |
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int ret; |
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ret = stmpe_reg_read(stmpe, reg); |
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if (ret < 0) |
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return ret; |
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if (ret & mask) |
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return GPIO_LINE_DIRECTION_OUT; |
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return GPIO_LINE_DIRECTION_IN; |
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} |
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static int stmpe_gpio_direction_output(struct gpio_chip *chip, |
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unsigned offset, int val) |
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{ |
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
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struct stmpe *stmpe = stmpe_gpio->stmpe; |
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u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; |
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u8 mask = BIT(offset % 8); |
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stmpe_gpio_set(chip, offset, val); |
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return stmpe_set_bits(stmpe, reg, mask, mask); |
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} |
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static int stmpe_gpio_direction_input(struct gpio_chip *chip, |
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unsigned offset) |
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{ |
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
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struct stmpe *stmpe = stmpe_gpio->stmpe; |
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u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)]; |
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u8 mask = BIT(offset % 8); |
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return stmpe_set_bits(stmpe, reg, mask, 0); |
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} |
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static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip); |
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struct stmpe *stmpe = stmpe_gpio->stmpe; |
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if (stmpe_gpio->norequest_mask & BIT(offset)) |
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return -EINVAL; |
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return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO); |
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} |
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static const struct gpio_chip template_chip = { |
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.label = "stmpe", |
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.owner = THIS_MODULE, |
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.get_direction = stmpe_gpio_get_direction, |
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.direction_input = stmpe_gpio_direction_input, |
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.get = stmpe_gpio_get, |
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.direction_output = stmpe_gpio_direction_output, |
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.set = stmpe_gpio_set, |
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.request = stmpe_gpio_request, |
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.can_sleep = true, |
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}; |
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static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
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int offset = d->hwirq; |
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int regoffset = offset / 8; |
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int mask = BIT(offset % 8); |
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if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH) |
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return -EINVAL; |
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/* STMPE801 and STMPE 1600 don't have RE and FE registers */ |
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if (stmpe_gpio->stmpe->partnum == STMPE801 || |
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stmpe_gpio->stmpe->partnum == STMPE1600) |
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return 0; |
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if (type & IRQ_TYPE_EDGE_RISING) |
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stmpe_gpio->regs[REG_RE][regoffset] |= mask; |
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else |
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stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; |
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if (type & IRQ_TYPE_EDGE_FALLING) |
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stmpe_gpio->regs[REG_FE][regoffset] |= mask; |
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else |
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stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; |
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return 0; |
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} |
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static void stmpe_gpio_irq_lock(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
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mutex_lock(&stmpe_gpio->irq_lock); |
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} |
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static void stmpe_gpio_irq_sync_unlock(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
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struct stmpe *stmpe = stmpe_gpio->stmpe; |
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int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); |
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static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = { |
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[REG_RE][LSB] = STMPE_IDX_GPRER_LSB, |
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[REG_RE][CSB] = STMPE_IDX_GPRER_CSB, |
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[REG_RE][MSB] = STMPE_IDX_GPRER_MSB, |
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[REG_FE][LSB] = STMPE_IDX_GPFER_LSB, |
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[REG_FE][CSB] = STMPE_IDX_GPFER_CSB, |
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[REG_FE][MSB] = STMPE_IDX_GPFER_MSB, |
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[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB, |
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[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB, |
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[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB, |
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}; |
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int i, j; |
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/* |
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* STMPE1600: to be able to get IRQ from pins, |
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* a read must be done on GPMR register, or a write in |
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* GPSR or GPCR registers |
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*/ |
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if (stmpe->partnum == STMPE1600) { |
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stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]); |
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stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]); |
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} |
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for (i = 0; i < CACHE_NR_REGS; i++) { |
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/* STMPE801 and STMPE1600 don't have RE and FE registers */ |
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if ((stmpe->partnum == STMPE801 || |
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stmpe->partnum == STMPE1600) && |
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(i != REG_IE)) |
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continue; |
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for (j = 0; j < num_banks; j++) { |
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u8 old = stmpe_gpio->oldregs[i][j]; |
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u8 new = stmpe_gpio->regs[i][j]; |
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if (new == old) |
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continue; |
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stmpe_gpio->oldregs[i][j] = new; |
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stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new); |
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} |
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} |
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mutex_unlock(&stmpe_gpio->irq_lock); |
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} |
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static void stmpe_gpio_irq_mask(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
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int offset = d->hwirq; |
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int regoffset = offset / 8; |
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int mask = BIT(offset % 8); |
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stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; |
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} |
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static void stmpe_gpio_irq_unmask(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
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int offset = d->hwirq; |
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int regoffset = offset / 8; |
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int mask = BIT(offset % 8); |
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stmpe_gpio->regs[REG_IE][regoffset] |= mask; |
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} |
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static void stmpe_dbg_show_one(struct seq_file *s, |
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struct gpio_chip *gc, |
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unsigned offset, unsigned gpio) |
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{ |
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
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struct stmpe *stmpe = stmpe_gpio->stmpe; |
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const char *label = gpiochip_is_requested(gc, offset); |
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bool val = !!stmpe_gpio_get(gc, offset); |
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u8 bank = offset / 8; |
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u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank]; |
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u8 mask = BIT(offset % 8); |
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int ret; |
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u8 dir; |
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ret = stmpe_reg_read(stmpe, dir_reg); |
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if (ret < 0) |
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return; |
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dir = !!(ret & mask); |
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if (dir) { |
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seq_printf(s, " gpio-%-3d (%-20.20s) out %s", |
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gpio, label ?: "(none)", |
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val ? "hi" : "lo"); |
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} else { |
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u8 edge_det_reg; |
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u8 rise_reg; |
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u8 fall_reg; |
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u8 irqen_reg; |
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static const char * const edge_det_values[] = { |
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"edge-inactive", |
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"edge-asserted", |
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"not-supported" |
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}; |
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static const char * const rise_values[] = { |
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"no-rising-edge-detection", |
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"rising-edge-detection", |
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"not-supported" |
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}; |
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static const char * const fall_values[] = { |
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"no-falling-edge-detection", |
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"falling-edge-detection", |
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"not-supported" |
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}; |
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#define NOT_SUPPORTED_IDX 2 |
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u8 edge_det = NOT_SUPPORTED_IDX; |
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u8 rise = NOT_SUPPORTED_IDX; |
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u8 fall = NOT_SUPPORTED_IDX; |
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bool irqen; |
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switch (stmpe->partnum) { |
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case STMPE610: |
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case STMPE811: |
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case STMPE1601: |
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case STMPE2401: |
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case STMPE2403: |
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edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank]; |
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ret = stmpe_reg_read(stmpe, edge_det_reg); |
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if (ret < 0) |
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return; |
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edge_det = !!(ret & mask); |
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fallthrough; |
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case STMPE1801: |
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rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank]; |
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fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank]; |
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ret = stmpe_reg_read(stmpe, rise_reg); |
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if (ret < 0) |
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return; |
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rise = !!(ret & mask); |
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ret = stmpe_reg_read(stmpe, fall_reg); |
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if (ret < 0) |
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return; |
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fall = !!(ret & mask); |
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fallthrough; |
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case STMPE801: |
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case STMPE1600: |
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irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank]; |
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break; |
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default: |
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return; |
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} |
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ret = stmpe_reg_read(stmpe, irqen_reg); |
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if (ret < 0) |
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return; |
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irqen = !!(ret & mask); |
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seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s", |
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gpio, label ?: "(none)", |
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val ? "hi" : "lo", |
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edge_det_values[edge_det], |
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irqen ? "IRQ-enabled" : "IRQ-disabled", |
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rise_values[rise], |
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fall_values[fall]); |
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} |
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} |
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static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc) |
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{ |
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unsigned i; |
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unsigned gpio = gc->base; |
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for (i = 0; i < gc->ngpio; i++, gpio++) { |
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stmpe_dbg_show_one(s, gc, i, gpio); |
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seq_putc(s, '\n'); |
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} |
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} |
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static struct irq_chip stmpe_gpio_irq_chip = { |
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.name = "stmpe-gpio", |
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.irq_bus_lock = stmpe_gpio_irq_lock, |
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.irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock, |
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.irq_mask = stmpe_gpio_irq_mask, |
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.irq_unmask = stmpe_gpio_irq_unmask, |
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.irq_set_type = stmpe_gpio_irq_set_type, |
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}; |
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#define MAX_GPIOS 24 |
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static irqreturn_t stmpe_gpio_irq(int irq, void *dev) |
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{ |
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struct stmpe_gpio *stmpe_gpio = dev; |
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struct stmpe *stmpe = stmpe_gpio->stmpe; |
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u8 statmsbreg; |
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int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8); |
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u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)]; |
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int ret; |
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int i; |
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/* |
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* the stmpe_block_read() call below, imposes to set statmsbreg |
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* with the register located at the lowest address. As STMPE1600 |
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* variant is the only one which respect registers address's order |
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* (LSB regs located at lowest address than MSB ones) whereas all |
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* the others have a registers layout with MSB located before the |
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* LSB regs. |
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*/ |
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if (stmpe->partnum == STMPE1600) |
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statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB]; |
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else |
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statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB]; |
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ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status); |
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if (ret < 0) |
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return IRQ_NONE; |
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for (i = 0; i < num_banks; i++) { |
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int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i : |
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num_banks - i - 1; |
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unsigned int enabled = stmpe_gpio->regs[REG_IE][bank]; |
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unsigned int stat = status[i]; |
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stat &= enabled; |
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if (!stat) |
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continue; |
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while (stat) { |
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int bit = __ffs(stat); |
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int line = bank * 8 + bit; |
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int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain, |
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line); |
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handle_nested_irq(child_irq); |
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stat &= ~BIT(bit); |
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} |
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/* |
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* interrupt status register write has no effect on |
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* 801/1801/1600, bits are cleared when read. |
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* Edge detect register is not present on 801/1600/1801 |
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*/ |
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if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 && |
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stmpe->partnum != STMPE1801) { |
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stmpe_reg_write(stmpe, statmsbreg + i, status[i]); |
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stmpe_reg_write(stmpe, |
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stmpe->regs[STMPE_IDX_GPEDR_MSB] + i, |
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status[i]); |
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} |
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} |
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return IRQ_HANDLED; |
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} |
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|
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static void stmpe_init_irq_valid_mask(struct gpio_chip *gc, |
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unsigned long *valid_mask, |
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unsigned int ngpios) |
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{ |
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struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); |
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int i; |
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|
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if (!stmpe_gpio->norequest_mask) |
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return; |
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|
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/* Forbid unused lines to be mapped as IRQs */ |
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for (i = 0; i < sizeof(u32); i++) { |
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if (stmpe_gpio->norequest_mask & BIT(i)) |
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clear_bit(i, valid_mask); |
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} |
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} |
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|
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static void stmpe_gpio_disable(void *stmpe) |
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{ |
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stmpe_disable(stmpe, STMPE_BLOCK_GPIO); |
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} |
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|
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static int stmpe_gpio_probe(struct platform_device *pdev) |
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{ |
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struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); |
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struct device_node *np = pdev->dev.of_node; |
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struct stmpe_gpio *stmpe_gpio; |
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int ret, irq; |
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|
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if (stmpe->num_gpios > MAX_GPIOS) { |
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dev_err(&pdev->dev, "Need to increase maximum GPIO number\n"); |
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return -EINVAL; |
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} |
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|
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stmpe_gpio = devm_kzalloc(&pdev->dev, sizeof(*stmpe_gpio), GFP_KERNEL); |
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if (!stmpe_gpio) |
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return -ENOMEM; |
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|
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mutex_init(&stmpe_gpio->irq_lock); |
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|
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stmpe_gpio->dev = &pdev->dev; |
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stmpe_gpio->stmpe = stmpe; |
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stmpe_gpio->chip = template_chip; |
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stmpe_gpio->chip.ngpio = stmpe->num_gpios; |
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stmpe_gpio->chip.parent = &pdev->dev; |
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stmpe_gpio->chip.of_node = np; |
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stmpe_gpio->chip.base = -1; |
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|
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if (IS_ENABLED(CONFIG_DEBUG_FS)) |
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stmpe_gpio->chip.dbg_show = stmpe_dbg_show; |
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|
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of_property_read_u32(np, "st,norequest-mask", |
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&stmpe_gpio->norequest_mask); |
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|
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) |
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dev_info(&pdev->dev, |
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"device configured in no-irq mode: " |
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"irqs are not available\n"); |
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|
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ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO); |
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if (ret) |
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return ret; |
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|
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ret = devm_add_action_or_reset(&pdev->dev, stmpe_gpio_disable, stmpe); |
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if (ret) |
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return ret; |
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|
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if (irq > 0) { |
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struct gpio_irq_chip *girq; |
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|
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ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, |
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stmpe_gpio_irq, IRQF_ONESHOT, |
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"stmpe-gpio", stmpe_gpio); |
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if (ret) { |
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dev_err(&pdev->dev, "unable to get irq: %d\n", ret); |
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return ret; |
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} |
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|
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girq = &stmpe_gpio->chip.irq; |
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girq->chip = &stmpe_gpio_irq_chip; |
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/* This will let us handle the parent IRQ in the driver */ |
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girq->parent_handler = NULL; |
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girq->num_parents = 0; |
|
girq->parents = NULL; |
|
girq->default_type = IRQ_TYPE_NONE; |
|
girq->handler = handle_simple_irq; |
|
girq->threaded = true; |
|
girq->init_valid_mask = stmpe_init_irq_valid_mask; |
|
} |
|
|
|
return devm_gpiochip_add_data(&pdev->dev, &stmpe_gpio->chip, stmpe_gpio); |
|
} |
|
|
|
static struct platform_driver stmpe_gpio_driver = { |
|
.driver = { |
|
.suppress_bind_attrs = true, |
|
.name = "stmpe-gpio", |
|
}, |
|
.probe = stmpe_gpio_probe, |
|
}; |
|
|
|
static int __init stmpe_gpio_init(void) |
|
{ |
|
return platform_driver_register(&stmpe_gpio_driver); |
|
} |
|
subsys_initcall(stmpe_gpio_init);
|
|
|