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416 lines
9.9 KiB
416 lines
9.9 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* GPIO driver for NXP LPC18xx/43xx. |
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* |
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* Copyright (C) 2018 Vladimir Zapolskiy <[email protected]> |
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* Copyright (C) 2015 Joachim Eastwood <[email protected]> |
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* |
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*/ |
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#include <linux/clk.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/io.h> |
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#include <linux/irqdomain.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_gpio.h> |
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#include <linux/of_irq.h> |
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#include <linux/pinctrl/consumer.h> |
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#include <linux/platform_device.h> |
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/* LPC18xx GPIO register offsets */ |
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#define LPC18XX_REG_DIR(n) (0x2000 + n * sizeof(u32)) |
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#define LPC18XX_MAX_PORTS 8 |
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#define LPC18XX_PINS_PER_PORT 32 |
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/* LPC18xx GPIO pin interrupt controller register offsets */ |
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#define LPC18XX_GPIO_PIN_IC_ISEL 0x00 |
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#define LPC18XX_GPIO_PIN_IC_IENR 0x04 |
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#define LPC18XX_GPIO_PIN_IC_SIENR 0x08 |
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#define LPC18XX_GPIO_PIN_IC_CIENR 0x0c |
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#define LPC18XX_GPIO_PIN_IC_IENF 0x10 |
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#define LPC18XX_GPIO_PIN_IC_SIENF 0x14 |
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#define LPC18XX_GPIO_PIN_IC_CIENF 0x18 |
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#define LPC18XX_GPIO_PIN_IC_RISE 0x1c |
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#define LPC18XX_GPIO_PIN_IC_FALL 0x20 |
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#define LPC18XX_GPIO_PIN_IC_IST 0x24 |
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#define NR_LPC18XX_GPIO_PIN_IC_IRQS 8 |
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struct lpc18xx_gpio_pin_ic { |
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void __iomem *base; |
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struct irq_domain *domain; |
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struct raw_spinlock lock; |
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}; |
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struct lpc18xx_gpio_chip { |
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struct gpio_chip gpio; |
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void __iomem *base; |
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struct clk *clk; |
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struct lpc18xx_gpio_pin_ic *pin_ic; |
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spinlock_t lock; |
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}; |
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static inline void lpc18xx_gpio_pin_ic_isel(struct lpc18xx_gpio_pin_ic *ic, |
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u32 pin, bool set) |
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{ |
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u32 val = readl_relaxed(ic->base + LPC18XX_GPIO_PIN_IC_ISEL); |
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if (set) |
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val &= ~BIT(pin); |
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else |
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val |= BIT(pin); |
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writel_relaxed(val, ic->base + LPC18XX_GPIO_PIN_IC_ISEL); |
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} |
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static inline void lpc18xx_gpio_pin_ic_set(struct lpc18xx_gpio_pin_ic *ic, |
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u32 pin, u32 reg) |
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{ |
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writel_relaxed(BIT(pin), ic->base + reg); |
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} |
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static void lpc18xx_gpio_pin_ic_mask(struct irq_data *d) |
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{ |
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struct lpc18xx_gpio_pin_ic *ic = d->chip_data; |
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u32 type = irqd_get_trigger_type(d); |
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raw_spin_lock(&ic->lock); |
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if (type & IRQ_TYPE_LEVEL_MASK || type & IRQ_TYPE_EDGE_RISING) |
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq, |
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LPC18XX_GPIO_PIN_IC_CIENR); |
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if (type & IRQ_TYPE_EDGE_FALLING) |
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq, |
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LPC18XX_GPIO_PIN_IC_CIENF); |
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raw_spin_unlock(&ic->lock); |
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irq_chip_mask_parent(d); |
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} |
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static void lpc18xx_gpio_pin_ic_unmask(struct irq_data *d) |
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{ |
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struct lpc18xx_gpio_pin_ic *ic = d->chip_data; |
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u32 type = irqd_get_trigger_type(d); |
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raw_spin_lock(&ic->lock); |
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if (type & IRQ_TYPE_LEVEL_MASK || type & IRQ_TYPE_EDGE_RISING) |
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq, |
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LPC18XX_GPIO_PIN_IC_SIENR); |
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if (type & IRQ_TYPE_EDGE_FALLING) |
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq, |
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LPC18XX_GPIO_PIN_IC_SIENF); |
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raw_spin_unlock(&ic->lock); |
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irq_chip_unmask_parent(d); |
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} |
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static void lpc18xx_gpio_pin_ic_eoi(struct irq_data *d) |
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{ |
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struct lpc18xx_gpio_pin_ic *ic = d->chip_data; |
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u32 type = irqd_get_trigger_type(d); |
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raw_spin_lock(&ic->lock); |
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if (type & IRQ_TYPE_EDGE_BOTH) |
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq, |
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LPC18XX_GPIO_PIN_IC_IST); |
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raw_spin_unlock(&ic->lock); |
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irq_chip_eoi_parent(d); |
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} |
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static int lpc18xx_gpio_pin_ic_set_type(struct irq_data *d, unsigned int type) |
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{ |
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struct lpc18xx_gpio_pin_ic *ic = d->chip_data; |
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raw_spin_lock(&ic->lock); |
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if (type & IRQ_TYPE_LEVEL_HIGH) { |
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lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true); |
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq, |
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LPC18XX_GPIO_PIN_IC_SIENF); |
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} else if (type & IRQ_TYPE_LEVEL_LOW) { |
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lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, true); |
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lpc18xx_gpio_pin_ic_set(ic, d->hwirq, |
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LPC18XX_GPIO_PIN_IC_CIENF); |
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} else { |
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lpc18xx_gpio_pin_ic_isel(ic, d->hwirq, false); |
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} |
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raw_spin_unlock(&ic->lock); |
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return 0; |
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} |
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static struct irq_chip lpc18xx_gpio_pin_ic = { |
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.name = "LPC18xx GPIO pin", |
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.irq_mask = lpc18xx_gpio_pin_ic_mask, |
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.irq_unmask = lpc18xx_gpio_pin_ic_unmask, |
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.irq_eoi = lpc18xx_gpio_pin_ic_eoi, |
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.irq_set_type = lpc18xx_gpio_pin_ic_set_type, |
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.flags = IRQCHIP_SET_TYPE_MASKED, |
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}; |
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static int lpc18xx_gpio_pin_ic_domain_alloc(struct irq_domain *domain, |
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unsigned int virq, |
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unsigned int nr_irqs, void *data) |
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{ |
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struct irq_fwspec parent_fwspec, *fwspec = data; |
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struct lpc18xx_gpio_pin_ic *ic = domain->host_data; |
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irq_hw_number_t hwirq; |
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int ret; |
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if (nr_irqs != 1) |
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return -EINVAL; |
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hwirq = fwspec->param[0]; |
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if (hwirq >= NR_LPC18XX_GPIO_PIN_IC_IRQS) |
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return -EINVAL; |
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/* |
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* All LPC18xx/LPC43xx GPIO pin hardware interrupts are translated |
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* into edge interrupts 32...39 on parent Cortex-M3/M4 NVIC |
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*/ |
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parent_fwspec.fwnode = domain->parent->fwnode; |
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parent_fwspec.param_count = 1; |
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parent_fwspec.param[0] = hwirq + 32; |
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ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec); |
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if (ret < 0) { |
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pr_err("failed to allocate parent irq %u: %d\n", |
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parent_fwspec.param[0], ret); |
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return ret; |
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} |
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return irq_domain_set_hwirq_and_chip(domain, virq, hwirq, |
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&lpc18xx_gpio_pin_ic, ic); |
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} |
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static const struct irq_domain_ops lpc18xx_gpio_pin_ic_domain_ops = { |
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.alloc = lpc18xx_gpio_pin_ic_domain_alloc, |
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.xlate = irq_domain_xlate_twocell, |
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.free = irq_domain_free_irqs_common, |
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}; |
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static int lpc18xx_gpio_pin_ic_probe(struct lpc18xx_gpio_chip *gc) |
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{ |
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struct device *dev = gc->gpio.parent; |
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struct irq_domain *parent_domain; |
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struct device_node *parent_node; |
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struct lpc18xx_gpio_pin_ic *ic; |
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struct resource res; |
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int ret, index; |
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parent_node = of_irq_find_parent(dev->of_node); |
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if (!parent_node) |
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return -ENXIO; |
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parent_domain = irq_find_host(parent_node); |
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of_node_put(parent_node); |
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if (!parent_domain) |
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return -ENXIO; |
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ic = devm_kzalloc(dev, sizeof(*ic), GFP_KERNEL); |
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if (!ic) |
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return -ENOMEM; |
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index = of_property_match_string(dev->of_node, "reg-names", |
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"gpio-pin-ic"); |
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if (index < 0) { |
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ret = -ENODEV; |
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goto free_ic; |
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} |
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ret = of_address_to_resource(dev->of_node, index, &res); |
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if (ret < 0) |
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goto free_ic; |
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ic->base = devm_ioremap_resource(dev, &res); |
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if (IS_ERR(ic->base)) { |
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ret = PTR_ERR(ic->base); |
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goto free_ic; |
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} |
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raw_spin_lock_init(&ic->lock); |
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ic->domain = irq_domain_add_hierarchy(parent_domain, 0, |
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NR_LPC18XX_GPIO_PIN_IC_IRQS, |
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dev->of_node, |
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&lpc18xx_gpio_pin_ic_domain_ops, |
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ic); |
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if (!ic->domain) { |
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pr_err("unable to add irq domain\n"); |
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ret = -ENODEV; |
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goto free_iomap; |
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} |
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gc->pin_ic = ic; |
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return 0; |
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free_iomap: |
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devm_iounmap(dev, ic->base); |
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free_ic: |
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devm_kfree(dev, ic); |
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return ret; |
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} |
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static void lpc18xx_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
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{ |
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struct lpc18xx_gpio_chip *gc = gpiochip_get_data(chip); |
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writeb(value ? 1 : 0, gc->base + offset); |
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} |
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static int lpc18xx_gpio_get(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct lpc18xx_gpio_chip *gc = gpiochip_get_data(chip); |
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return !!readb(gc->base + offset); |
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} |
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static int lpc18xx_gpio_direction(struct gpio_chip *chip, unsigned offset, |
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bool out) |
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{ |
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struct lpc18xx_gpio_chip *gc = gpiochip_get_data(chip); |
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unsigned long flags; |
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u32 port, pin, dir; |
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port = offset / LPC18XX_PINS_PER_PORT; |
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pin = offset % LPC18XX_PINS_PER_PORT; |
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spin_lock_irqsave(&gc->lock, flags); |
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dir = readl(gc->base + LPC18XX_REG_DIR(port)); |
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if (out) |
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dir |= BIT(pin); |
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else |
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dir &= ~BIT(pin); |
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writel(dir, gc->base + LPC18XX_REG_DIR(port)); |
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spin_unlock_irqrestore(&gc->lock, flags); |
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return 0; |
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} |
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static int lpc18xx_gpio_direction_input(struct gpio_chip *chip, |
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unsigned offset) |
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{ |
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return lpc18xx_gpio_direction(chip, offset, false); |
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} |
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static int lpc18xx_gpio_direction_output(struct gpio_chip *chip, |
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unsigned offset, int value) |
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{ |
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lpc18xx_gpio_set(chip, offset, value); |
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return lpc18xx_gpio_direction(chip, offset, true); |
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} |
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static const struct gpio_chip lpc18xx_chip = { |
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.label = "lpc18xx/43xx-gpio", |
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.request = gpiochip_generic_request, |
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.free = gpiochip_generic_free, |
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.direction_input = lpc18xx_gpio_direction_input, |
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.direction_output = lpc18xx_gpio_direction_output, |
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.set = lpc18xx_gpio_set, |
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.get = lpc18xx_gpio_get, |
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.ngpio = LPC18XX_MAX_PORTS * LPC18XX_PINS_PER_PORT, |
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.owner = THIS_MODULE, |
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}; |
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static int lpc18xx_gpio_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct lpc18xx_gpio_chip *gc; |
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int index, ret; |
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gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); |
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if (!gc) |
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return -ENOMEM; |
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gc->gpio = lpc18xx_chip; |
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platform_set_drvdata(pdev, gc); |
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index = of_property_match_string(dev->of_node, "reg-names", "gpio"); |
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if (index < 0) { |
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/* To support backward compatibility take the first resource */ |
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gc->base = devm_platform_ioremap_resource(pdev, 0); |
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} else { |
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struct resource res; |
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ret = of_address_to_resource(dev->of_node, index, &res); |
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if (ret < 0) |
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return ret; |
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gc->base = devm_ioremap_resource(dev, &res); |
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} |
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if (IS_ERR(gc->base)) |
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return PTR_ERR(gc->base); |
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gc->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(gc->clk)) { |
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dev_err(dev, "input clock not found\n"); |
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return PTR_ERR(gc->clk); |
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} |
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ret = clk_prepare_enable(gc->clk); |
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if (ret) { |
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dev_err(dev, "unable to enable clock\n"); |
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return ret; |
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} |
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spin_lock_init(&gc->lock); |
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gc->gpio.parent = dev; |
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ret = devm_gpiochip_add_data(dev, &gc->gpio, gc); |
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if (ret) { |
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dev_err(dev, "failed to add gpio chip\n"); |
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clk_disable_unprepare(gc->clk); |
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return ret; |
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} |
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/* On error GPIO pin interrupt controller just won't be registered */ |
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lpc18xx_gpio_pin_ic_probe(gc); |
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return 0; |
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} |
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static int lpc18xx_gpio_remove(struct platform_device *pdev) |
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{ |
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struct lpc18xx_gpio_chip *gc = platform_get_drvdata(pdev); |
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if (gc->pin_ic) |
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irq_domain_remove(gc->pin_ic->domain); |
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clk_disable_unprepare(gc->clk); |
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return 0; |
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} |
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static const struct of_device_id lpc18xx_gpio_match[] = { |
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{ .compatible = "nxp,lpc1850-gpio" }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, lpc18xx_gpio_match); |
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static struct platform_driver lpc18xx_gpio_driver = { |
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.probe = lpc18xx_gpio_probe, |
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.remove = lpc18xx_gpio_remove, |
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.driver = { |
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.name = "lpc18xx-gpio", |
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.of_match_table = lpc18xx_gpio_match, |
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}, |
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}; |
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module_platform_driver(lpc18xx_gpio_driver); |
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MODULE_AUTHOR("Joachim Eastwood <[email protected]>"); |
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MODULE_AUTHOR("Vladimir Zapolskiy <[email protected]>"); |
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MODULE_DESCRIPTION("GPIO driver for LPC18xx/43xx"); |
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MODULE_LICENSE("GPL v2");
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