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603 lines
17 KiB
603 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* FPGA Manager Driver for Altera SOCFPGA |
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* |
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* Copyright (C) 2013-2015 Altera Corporation |
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*/ |
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#include <linux/completion.h> |
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#include <linux/delay.h> |
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#include <linux/fpga/fpga-mgr.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/pm.h> |
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/* Register offsets */ |
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#define SOCFPGA_FPGMGR_STAT_OFST 0x0 |
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#define SOCFPGA_FPGMGR_CTL_OFST 0x4 |
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#define SOCFPGA_FPGMGR_DCLKCNT_OFST 0x8 |
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#define SOCFPGA_FPGMGR_DCLKSTAT_OFST 0xc |
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#define SOCFPGA_FPGMGR_GPIO_INTEN_OFST 0x830 |
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#define SOCFPGA_FPGMGR_GPIO_INTMSK_OFST 0x834 |
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#define SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST 0x838 |
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#define SOCFPGA_FPGMGR_GPIO_INT_POL_OFST 0x83c |
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#define SOCFPGA_FPGMGR_GPIO_INTSTAT_OFST 0x840 |
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#define SOCFPGA_FPGMGR_GPIO_RAW_INTSTAT_OFST 0x844 |
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#define SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST 0x84c |
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#define SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST 0x850 |
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/* Register bit defines */ |
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/* SOCFPGA_FPGMGR_STAT register mode field values */ |
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#define SOCFPGA_FPGMGR_STAT_POWER_UP 0x0 /*ramping*/ |
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#define SOCFPGA_FPGMGR_STAT_RESET 0x1 |
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#define SOCFPGA_FPGMGR_STAT_CFG 0x2 |
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#define SOCFPGA_FPGMGR_STAT_INIT 0x3 |
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#define SOCFPGA_FPGMGR_STAT_USER_MODE 0x4 |
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#define SOCFPGA_FPGMGR_STAT_UNKNOWN 0x5 |
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#define SOCFPGA_FPGMGR_STAT_STATE_MASK 0x7 |
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/* This is a flag value that doesn't really happen in this register field */ |
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#define SOCFPGA_FPGMGR_STAT_POWER_OFF 0x0 |
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#define MSEL_PP16_FAST_NOAES_NODC 0x0 |
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#define MSEL_PP16_FAST_AES_NODC 0x1 |
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#define MSEL_PP16_FAST_AESOPT_DC 0x2 |
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#define MSEL_PP16_SLOW_NOAES_NODC 0x4 |
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#define MSEL_PP16_SLOW_AES_NODC 0x5 |
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#define MSEL_PP16_SLOW_AESOPT_DC 0x6 |
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#define MSEL_PP32_FAST_NOAES_NODC 0x8 |
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#define MSEL_PP32_FAST_AES_NODC 0x9 |
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#define MSEL_PP32_FAST_AESOPT_DC 0xa |
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#define MSEL_PP32_SLOW_NOAES_NODC 0xc |
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#define MSEL_PP32_SLOW_AES_NODC 0xd |
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#define MSEL_PP32_SLOW_AESOPT_DC 0xe |
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#define SOCFPGA_FPGMGR_STAT_MSEL_MASK 0x000000f8 |
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#define SOCFPGA_FPGMGR_STAT_MSEL_SHIFT 3 |
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/* SOCFPGA_FPGMGR_CTL register */ |
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#define SOCFPGA_FPGMGR_CTL_EN 0x00000001 |
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#define SOCFPGA_FPGMGR_CTL_NCE 0x00000002 |
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#define SOCFPGA_FPGMGR_CTL_NCFGPULL 0x00000004 |
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#define CDRATIO_X1 0x00000000 |
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#define CDRATIO_X2 0x00000040 |
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#define CDRATIO_X4 0x00000080 |
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#define CDRATIO_X8 0x000000c0 |
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#define SOCFPGA_FPGMGR_CTL_CDRATIO_MASK 0x000000c0 |
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#define SOCFPGA_FPGMGR_CTL_AXICFGEN 0x00000100 |
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#define CFGWDTH_16 0x00000000 |
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#define CFGWDTH_32 0x00000200 |
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#define SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK 0x00000200 |
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/* SOCFPGA_FPGMGR_DCLKSTAT register */ |
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#define SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE 0x1 |
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/* SOCFPGA_FPGMGR_GPIO_* registers share the same bit positions */ |
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#define SOCFPGA_FPGMGR_MON_NSTATUS 0x0001 |
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#define SOCFPGA_FPGMGR_MON_CONF_DONE 0x0002 |
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#define SOCFPGA_FPGMGR_MON_INIT_DONE 0x0004 |
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#define SOCFPGA_FPGMGR_MON_CRC_ERROR 0x0008 |
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#define SOCFPGA_FPGMGR_MON_CVP_CONF_DONE 0x0010 |
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#define SOCFPGA_FPGMGR_MON_PR_READY 0x0020 |
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#define SOCFPGA_FPGMGR_MON_PR_ERROR 0x0040 |
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#define SOCFPGA_FPGMGR_MON_PR_DONE 0x0080 |
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#define SOCFPGA_FPGMGR_MON_NCONFIG_PIN 0x0100 |
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#define SOCFPGA_FPGMGR_MON_NSTATUS_PIN 0x0200 |
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#define SOCFPGA_FPGMGR_MON_CONF_DONE_PIN 0x0400 |
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#define SOCFPGA_FPGMGR_MON_FPGA_POWER_ON 0x0800 |
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#define SOCFPGA_FPGMGR_MON_STATUS_MASK 0x0fff |
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#define SOCFPGA_FPGMGR_NUM_SUPPLIES 3 |
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#define SOCFPGA_RESUME_TIMEOUT 3 |
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/* In power-up order. Reverse for power-down. */ |
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static const char *supply_names[SOCFPGA_FPGMGR_NUM_SUPPLIES] __maybe_unused = { |
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"FPGA-1.5V", |
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"FPGA-1.1V", |
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"FPGA-2.5V", |
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}; |
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struct socfpga_fpga_priv { |
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void __iomem *fpga_base_addr; |
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void __iomem *fpga_data_addr; |
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struct completion status_complete; |
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int irq; |
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}; |
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struct cfgmgr_mode { |
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/* Values to set in the CTRL register */ |
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u32 ctrl; |
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/* flag that this table entry is a valid mode */ |
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bool valid; |
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}; |
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/* For SOCFPGA_FPGMGR_STAT_MSEL field */ |
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static struct cfgmgr_mode cfgmgr_modes[] = { |
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[MSEL_PP16_FAST_NOAES_NODC] = { CFGWDTH_16 | CDRATIO_X1, 1 }, |
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[MSEL_PP16_FAST_AES_NODC] = { CFGWDTH_16 | CDRATIO_X2, 1 }, |
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[MSEL_PP16_FAST_AESOPT_DC] = { CFGWDTH_16 | CDRATIO_X4, 1 }, |
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[MSEL_PP16_SLOW_NOAES_NODC] = { CFGWDTH_16 | CDRATIO_X1, 1 }, |
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[MSEL_PP16_SLOW_AES_NODC] = { CFGWDTH_16 | CDRATIO_X2, 1 }, |
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[MSEL_PP16_SLOW_AESOPT_DC] = { CFGWDTH_16 | CDRATIO_X4, 1 }, |
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[MSEL_PP32_FAST_NOAES_NODC] = { CFGWDTH_32 | CDRATIO_X1, 1 }, |
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[MSEL_PP32_FAST_AES_NODC] = { CFGWDTH_32 | CDRATIO_X4, 1 }, |
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[MSEL_PP32_FAST_AESOPT_DC] = { CFGWDTH_32 | CDRATIO_X8, 1 }, |
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[MSEL_PP32_SLOW_NOAES_NODC] = { CFGWDTH_32 | CDRATIO_X1, 1 }, |
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[MSEL_PP32_SLOW_AES_NODC] = { CFGWDTH_32 | CDRATIO_X4, 1 }, |
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[MSEL_PP32_SLOW_AESOPT_DC] = { CFGWDTH_32 | CDRATIO_X8, 1 }, |
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}; |
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static u32 socfpga_fpga_readl(struct socfpga_fpga_priv *priv, u32 reg_offset) |
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{ |
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return readl(priv->fpga_base_addr + reg_offset); |
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} |
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static void socfpga_fpga_writel(struct socfpga_fpga_priv *priv, u32 reg_offset, |
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u32 value) |
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{ |
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writel(value, priv->fpga_base_addr + reg_offset); |
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} |
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static u32 socfpga_fpga_raw_readl(struct socfpga_fpga_priv *priv, |
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u32 reg_offset) |
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{ |
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return __raw_readl(priv->fpga_base_addr + reg_offset); |
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} |
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static void socfpga_fpga_raw_writel(struct socfpga_fpga_priv *priv, |
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u32 reg_offset, u32 value) |
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{ |
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__raw_writel(value, priv->fpga_base_addr + reg_offset); |
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} |
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static void socfpga_fpga_data_writel(struct socfpga_fpga_priv *priv, u32 value) |
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{ |
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writel(value, priv->fpga_data_addr); |
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} |
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static inline void socfpga_fpga_set_bitsl(struct socfpga_fpga_priv *priv, |
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u32 offset, u32 bits) |
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{ |
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u32 val; |
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val = socfpga_fpga_readl(priv, offset); |
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val |= bits; |
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socfpga_fpga_writel(priv, offset, val); |
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} |
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static inline void socfpga_fpga_clr_bitsl(struct socfpga_fpga_priv *priv, |
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u32 offset, u32 bits) |
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{ |
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u32 val; |
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val = socfpga_fpga_readl(priv, offset); |
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val &= ~bits; |
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socfpga_fpga_writel(priv, offset, val); |
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} |
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static u32 socfpga_fpga_mon_status_get(struct socfpga_fpga_priv *priv) |
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{ |
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return socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST) & |
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SOCFPGA_FPGMGR_MON_STATUS_MASK; |
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} |
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static u32 socfpga_fpga_state_get(struct socfpga_fpga_priv *priv) |
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{ |
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u32 status = socfpga_fpga_mon_status_get(priv); |
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if ((status & SOCFPGA_FPGMGR_MON_FPGA_POWER_ON) == 0) |
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return SOCFPGA_FPGMGR_STAT_POWER_OFF; |
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return socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_STAT_OFST) & |
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SOCFPGA_FPGMGR_STAT_STATE_MASK; |
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} |
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static void socfpga_fpga_clear_done_status(struct socfpga_fpga_priv *priv) |
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{ |
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socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST, |
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SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE); |
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} |
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/* |
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* Set the DCLKCNT, wait for DCLKSTAT to report the count completed, and clear |
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* the complete status. |
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*/ |
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static int socfpga_fpga_dclk_set_and_wait_clear(struct socfpga_fpga_priv *priv, |
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u32 count) |
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{ |
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int timeout = 2; |
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u32 done; |
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/* Clear any existing DONE status. */ |
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if (socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST)) |
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socfpga_fpga_clear_done_status(priv); |
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/* Issue the DCLK count. */ |
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socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_DCLKCNT_OFST, count); |
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/* Poll DCLKSTAT to see if it completed in the timeout period. */ |
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do { |
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done = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST); |
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if (done == SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE) { |
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socfpga_fpga_clear_done_status(priv); |
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return 0; |
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} |
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udelay(1); |
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} while (timeout--); |
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return -ETIMEDOUT; |
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} |
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static int socfpga_fpga_wait_for_state(struct socfpga_fpga_priv *priv, |
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u32 state) |
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{ |
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int timeout = 2; |
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/* |
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* HW doesn't support an interrupt for changes in state, so poll to see |
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* if it matches the requested state within the timeout period. |
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*/ |
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do { |
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if ((socfpga_fpga_state_get(priv) & state) != 0) |
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return 0; |
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msleep(20); |
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} while (timeout--); |
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return -ETIMEDOUT; |
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} |
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static void socfpga_fpga_enable_irqs(struct socfpga_fpga_priv *priv, u32 irqs) |
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{ |
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/* set irqs to level sensitive */ |
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socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST, 0); |
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/* set interrupt polarity */ |
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socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INT_POL_OFST, irqs); |
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/* clear irqs */ |
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socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST, irqs); |
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/* unmask interrupts */ |
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socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTMSK_OFST, 0); |
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/* enable interrupts */ |
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socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTEN_OFST, irqs); |
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} |
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static void socfpga_fpga_disable_irqs(struct socfpga_fpga_priv *priv) |
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{ |
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socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTEN_OFST, 0); |
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} |
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static irqreturn_t socfpga_fpga_isr(int irq, void *dev_id) |
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{ |
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struct socfpga_fpga_priv *priv = dev_id; |
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u32 irqs, st; |
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bool conf_done, nstatus; |
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/* clear irqs */ |
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irqs = socfpga_fpga_raw_readl(priv, SOCFPGA_FPGMGR_GPIO_INTSTAT_OFST); |
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socfpga_fpga_raw_writel(priv, SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST, irqs); |
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st = socfpga_fpga_raw_readl(priv, SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST); |
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conf_done = (st & SOCFPGA_FPGMGR_MON_CONF_DONE) != 0; |
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nstatus = (st & SOCFPGA_FPGMGR_MON_NSTATUS) != 0; |
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/* success */ |
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if (conf_done && nstatus) { |
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/* disable irqs */ |
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socfpga_fpga_raw_writel(priv, |
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SOCFPGA_FPGMGR_GPIO_INTEN_OFST, 0); |
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complete(&priv->status_complete); |
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} |
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return IRQ_HANDLED; |
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} |
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static int socfpga_fpga_wait_for_config_done(struct socfpga_fpga_priv *priv) |
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{ |
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int timeout, ret = 0; |
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socfpga_fpga_disable_irqs(priv); |
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init_completion(&priv->status_complete); |
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socfpga_fpga_enable_irqs(priv, SOCFPGA_FPGMGR_MON_CONF_DONE); |
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timeout = wait_for_completion_interruptible_timeout( |
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&priv->status_complete, |
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msecs_to_jiffies(10)); |
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if (timeout == 0) |
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ret = -ETIMEDOUT; |
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socfpga_fpga_disable_irqs(priv); |
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return ret; |
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} |
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static int socfpga_fpga_cfg_mode_get(struct socfpga_fpga_priv *priv) |
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{ |
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u32 msel; |
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msel = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_STAT_OFST); |
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msel &= SOCFPGA_FPGMGR_STAT_MSEL_MASK; |
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msel >>= SOCFPGA_FPGMGR_STAT_MSEL_SHIFT; |
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/* Check that this MSEL setting is supported */ |
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if ((msel >= ARRAY_SIZE(cfgmgr_modes)) || !cfgmgr_modes[msel].valid) |
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return -EINVAL; |
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return msel; |
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} |
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static int socfpga_fpga_cfg_mode_set(struct socfpga_fpga_priv *priv) |
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{ |
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u32 ctrl_reg; |
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int mode; |
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/* get value from MSEL pins */ |
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mode = socfpga_fpga_cfg_mode_get(priv); |
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if (mode < 0) |
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return mode; |
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/* Adjust CTRL for the CDRATIO */ |
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ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); |
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ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CDRATIO_MASK; |
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ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK; |
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ctrl_reg |= cfgmgr_modes[mode].ctrl; |
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/* Set NCE to 0. */ |
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ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCE; |
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socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg); |
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return 0; |
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} |
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static int socfpga_fpga_reset(struct fpga_manager *mgr) |
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{ |
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struct socfpga_fpga_priv *priv = mgr->priv; |
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u32 ctrl_reg, status; |
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int ret; |
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/* |
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* Step 1: |
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* - Set CTRL.CFGWDTH, CTRL.CDRATIO to match cfg mode |
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* - Set CTRL.NCE to 0 |
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*/ |
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ret = socfpga_fpga_cfg_mode_set(priv); |
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if (ret) |
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return ret; |
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/* Step 2: Set CTRL.EN to 1 */ |
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socfpga_fpga_set_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST, |
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SOCFPGA_FPGMGR_CTL_EN); |
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/* Step 3: Set CTRL.NCONFIGPULL to 1 to put FPGA in reset */ |
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ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); |
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ctrl_reg |= SOCFPGA_FPGMGR_CTL_NCFGPULL; |
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socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg); |
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/* Step 4: Wait for STATUS.MODE to report FPGA is in reset phase */ |
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status = socfpga_fpga_wait_for_state(priv, SOCFPGA_FPGMGR_STAT_RESET); |
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/* Step 5: Set CONTROL.NCONFIGPULL to 0 to release FPGA from reset */ |
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ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCFGPULL; |
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socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg); |
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/* Timeout waiting for reset */ |
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if (status) |
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return -ETIMEDOUT; |
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return 0; |
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} |
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/* |
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* Prepare the FPGA to receive the configuration data. |
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*/ |
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static int socfpga_fpga_ops_configure_init(struct fpga_manager *mgr, |
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struct fpga_image_info *info, |
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const char *buf, size_t count) |
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{ |
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struct socfpga_fpga_priv *priv = mgr->priv; |
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int ret; |
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if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { |
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dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); |
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return -EINVAL; |
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} |
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/* Steps 1 - 5: Reset the FPGA */ |
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ret = socfpga_fpga_reset(mgr); |
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if (ret) |
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return ret; |
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/* Step 6: Wait for FPGA to enter configuration phase */ |
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if (socfpga_fpga_wait_for_state(priv, SOCFPGA_FPGMGR_STAT_CFG)) |
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return -ETIMEDOUT; |
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/* Step 7: Clear nSTATUS interrupt */ |
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socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST, |
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SOCFPGA_FPGMGR_MON_NSTATUS); |
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/* Step 8: Set CTRL.AXICFGEN to 1 to enable transfer of config data */ |
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socfpga_fpga_set_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST, |
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SOCFPGA_FPGMGR_CTL_AXICFGEN); |
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return 0; |
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} |
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/* |
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* Step 9: write data to the FPGA data register |
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*/ |
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static int socfpga_fpga_ops_configure_write(struct fpga_manager *mgr, |
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const char *buf, size_t count) |
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{ |
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struct socfpga_fpga_priv *priv = mgr->priv; |
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u32 *buffer_32 = (u32 *)buf; |
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size_t i = 0; |
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if (count <= 0) |
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return -EINVAL; |
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/* Write out the complete 32-bit chunks. */ |
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while (count >= sizeof(u32)) { |
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socfpga_fpga_data_writel(priv, buffer_32[i++]); |
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count -= sizeof(u32); |
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} |
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|
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/* Write out remaining non 32-bit chunks. */ |
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switch (count) { |
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case 3: |
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socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x00ffffff); |
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break; |
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case 2: |
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socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x0000ffff); |
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break; |
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case 1: |
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socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x000000ff); |
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break; |
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case 0: |
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break; |
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default: |
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/* This will never happen. */ |
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return -EFAULT; |
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} |
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return 0; |
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} |
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|
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static int socfpga_fpga_ops_configure_complete(struct fpga_manager *mgr, |
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struct fpga_image_info *info) |
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{ |
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struct socfpga_fpga_priv *priv = mgr->priv; |
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u32 status; |
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|
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/* |
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* Step 10: |
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* - Observe CONF_DONE and nSTATUS (active low) |
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* - if CONF_DONE = 1 and nSTATUS = 1, configuration was successful |
|
* - if CONF_DONE = 0 and nSTATUS = 0, configuration failed |
|
*/ |
|
status = socfpga_fpga_wait_for_config_done(priv); |
|
if (status) |
|
return status; |
|
|
|
/* Step 11: Clear CTRL.AXICFGEN to disable transfer of config data */ |
|
socfpga_fpga_clr_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST, |
|
SOCFPGA_FPGMGR_CTL_AXICFGEN); |
|
|
|
/* |
|
* Step 12: |
|
* - Write 4 to DCLKCNT |
|
* - Wait for STATUS.DCNTDONE = 1 |
|
* - Clear W1C bit in STATUS.DCNTDONE |
|
*/ |
|
if (socfpga_fpga_dclk_set_and_wait_clear(priv, 4)) |
|
return -ETIMEDOUT; |
|
|
|
/* Step 13: Wait for STATUS.MODE to report USER MODE */ |
|
if (socfpga_fpga_wait_for_state(priv, SOCFPGA_FPGMGR_STAT_USER_MODE)) |
|
return -ETIMEDOUT; |
|
|
|
/* Step 14: Set CTRL.EN to 0 */ |
|
socfpga_fpga_clr_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST, |
|
SOCFPGA_FPGMGR_CTL_EN); |
|
|
|
return 0; |
|
} |
|
|
|
/* Translate state register values to FPGA framework state */ |
|
static const enum fpga_mgr_states socfpga_state_to_framework_state[] = { |
|
[SOCFPGA_FPGMGR_STAT_POWER_OFF] = FPGA_MGR_STATE_POWER_OFF, |
|
[SOCFPGA_FPGMGR_STAT_RESET] = FPGA_MGR_STATE_RESET, |
|
[SOCFPGA_FPGMGR_STAT_CFG] = FPGA_MGR_STATE_WRITE_INIT, |
|
[SOCFPGA_FPGMGR_STAT_INIT] = FPGA_MGR_STATE_WRITE_INIT, |
|
[SOCFPGA_FPGMGR_STAT_USER_MODE] = FPGA_MGR_STATE_OPERATING, |
|
[SOCFPGA_FPGMGR_STAT_UNKNOWN] = FPGA_MGR_STATE_UNKNOWN, |
|
}; |
|
|
|
static enum fpga_mgr_states socfpga_fpga_ops_state(struct fpga_manager *mgr) |
|
{ |
|
struct socfpga_fpga_priv *priv = mgr->priv; |
|
enum fpga_mgr_states ret; |
|
u32 state; |
|
|
|
state = socfpga_fpga_state_get(priv); |
|
|
|
if (state < ARRAY_SIZE(socfpga_state_to_framework_state)) |
|
ret = socfpga_state_to_framework_state[state]; |
|
else |
|
ret = FPGA_MGR_STATE_UNKNOWN; |
|
|
|
return ret; |
|
} |
|
|
|
static const struct fpga_manager_ops socfpga_fpga_ops = { |
|
.state = socfpga_fpga_ops_state, |
|
.write_init = socfpga_fpga_ops_configure_init, |
|
.write = socfpga_fpga_ops_configure_write, |
|
.write_complete = socfpga_fpga_ops_configure_complete, |
|
}; |
|
|
|
static int socfpga_fpga_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct socfpga_fpga_priv *priv; |
|
struct fpga_manager *mgr; |
|
struct resource *res; |
|
int ret; |
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
priv->fpga_base_addr = devm_ioremap_resource(dev, res); |
|
if (IS_ERR(priv->fpga_base_addr)) |
|
return PTR_ERR(priv->fpga_base_addr); |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
|
priv->fpga_data_addr = devm_ioremap_resource(dev, res); |
|
if (IS_ERR(priv->fpga_data_addr)) |
|
return PTR_ERR(priv->fpga_data_addr); |
|
|
|
priv->irq = platform_get_irq(pdev, 0); |
|
if (priv->irq < 0) |
|
return priv->irq; |
|
|
|
ret = devm_request_irq(dev, priv->irq, socfpga_fpga_isr, 0, |
|
dev_name(dev), priv); |
|
if (ret) |
|
return ret; |
|
|
|
mgr = devm_fpga_mgr_create(dev, "Altera SOCFPGA FPGA Manager", |
|
&socfpga_fpga_ops, priv); |
|
if (!mgr) |
|
return -ENOMEM; |
|
|
|
return devm_fpga_mgr_register(dev, mgr); |
|
} |
|
|
|
#ifdef CONFIG_OF |
|
static const struct of_device_id socfpga_fpga_of_match[] = { |
|
{ .compatible = "altr,socfpga-fpga-mgr", }, |
|
{}, |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(of, socfpga_fpga_of_match); |
|
#endif |
|
|
|
static struct platform_driver socfpga_fpga_driver = { |
|
.probe = socfpga_fpga_probe, |
|
.driver = { |
|
.name = "socfpga_fpga_manager", |
|
.of_match_table = of_match_ptr(socfpga_fpga_of_match), |
|
}, |
|
}; |
|
|
|
module_platform_driver(socfpga_fpga_driver); |
|
|
|
MODULE_AUTHOR("Alan Tull <[email protected]>"); |
|
MODULE_DESCRIPTION("Altera SOCFPGA FPGA Manager"); |
|
MODULE_LICENSE("GPL v2");
|
|
|