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558 lines
15 KiB
558 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* FPGA Manager Driver for Altera Arria10 SoCFPGA |
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* |
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* Copyright (C) 2015-2016 Altera Corporation |
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*/ |
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#include <linux/clk.h> |
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#include <linux/device.h> |
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#include <linux/delay.h> |
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#include <linux/fpga/fpga-mgr.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/regmap.h> |
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#define A10_FPGAMGR_DCLKCNT_OFST 0x08 |
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#define A10_FPGAMGR_DCLKSTAT_OFST 0x0c |
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#define A10_FPGAMGR_IMGCFG_CTL_00_OFST 0x70 |
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#define A10_FPGAMGR_IMGCFG_CTL_01_OFST 0x74 |
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#define A10_FPGAMGR_IMGCFG_CTL_02_OFST 0x78 |
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#define A10_FPGAMGR_IMGCFG_STAT_OFST 0x80 |
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#define A10_FPGAMGR_DCLKSTAT_DCLKDONE BIT(0) |
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#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG BIT(0) |
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#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS BIT(1) |
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#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE BIT(2) |
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#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG BIT(8) |
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#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE BIT(16) |
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#define A10_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE BIT(24) |
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#define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG BIT(0) |
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#define A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST BIT(16) |
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#define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCE BIT(24) |
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#define A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL BIT(0) |
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#define A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MASK (BIT(16) | BIT(17)) |
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#define A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SHIFT 16 |
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#define A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH BIT(24) |
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#define A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SHIFT 24 |
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#define A10_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR BIT(0) |
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#define A10_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE BIT(1) |
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#define A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE BIT(2) |
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#define A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN BIT(4) |
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#define A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN BIT(6) |
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#define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY BIT(9) |
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#define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE BIT(10) |
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#define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR BIT(11) |
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#define A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN BIT(12) |
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#define A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK (BIT(16) | BIT(17) | BIT(18)) |
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#define A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT 16 |
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/* FPGA CD Ratio Value */ |
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#define CDRATIO_x1 0x0 |
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#define CDRATIO_x2 0x1 |
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#define CDRATIO_x4 0x2 |
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#define CDRATIO_x8 0x3 |
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/* Configuration width 16/32 bit */ |
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#define CFGWDTH_32 1 |
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#define CFGWDTH_16 0 |
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/* |
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* struct a10_fpga_priv - private data for fpga manager |
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* @regmap: regmap for register access |
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* @fpga_data_addr: iomap for single address data register to FPGA |
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* @clk: clock |
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*/ |
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struct a10_fpga_priv { |
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struct regmap *regmap; |
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void __iomem *fpga_data_addr; |
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struct clk *clk; |
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}; |
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static bool socfpga_a10_fpga_writeable_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case A10_FPGAMGR_DCLKCNT_OFST: |
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case A10_FPGAMGR_DCLKSTAT_OFST: |
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case A10_FPGAMGR_IMGCFG_CTL_00_OFST: |
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case A10_FPGAMGR_IMGCFG_CTL_01_OFST: |
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case A10_FPGAMGR_IMGCFG_CTL_02_OFST: |
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return true; |
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} |
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return false; |
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} |
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static bool socfpga_a10_fpga_readable_reg(struct device *dev, unsigned int reg) |
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{ |
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switch (reg) { |
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case A10_FPGAMGR_DCLKCNT_OFST: |
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case A10_FPGAMGR_DCLKSTAT_OFST: |
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case A10_FPGAMGR_IMGCFG_CTL_00_OFST: |
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case A10_FPGAMGR_IMGCFG_CTL_01_OFST: |
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case A10_FPGAMGR_IMGCFG_CTL_02_OFST: |
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case A10_FPGAMGR_IMGCFG_STAT_OFST: |
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return true; |
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} |
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return false; |
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} |
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static const struct regmap_config socfpga_a10_fpga_regmap_config = { |
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.reg_bits = 32, |
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.reg_stride = 4, |
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.val_bits = 32, |
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.writeable_reg = socfpga_a10_fpga_writeable_reg, |
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.readable_reg = socfpga_a10_fpga_readable_reg, |
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.max_register = A10_FPGAMGR_IMGCFG_STAT_OFST, |
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.cache_type = REGCACHE_NONE, |
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}; |
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/* |
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* from the register map description of cdratio in imgcfg_ctrl_02: |
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* Normal Configuration : 32bit Passive Parallel |
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* Partial Reconfiguration : 16bit Passive Parallel |
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*/ |
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static void socfpga_a10_fpga_set_cfg_width(struct a10_fpga_priv *priv, |
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int width) |
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{ |
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width <<= A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SHIFT; |
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regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, |
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A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH, width); |
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} |
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static void socfpga_a10_fpga_generate_dclks(struct a10_fpga_priv *priv, |
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u32 count) |
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{ |
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u32 val; |
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/* Clear any existing DONE status. */ |
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regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, |
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A10_FPGAMGR_DCLKSTAT_DCLKDONE); |
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/* Issue the DCLK regmap. */ |
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regmap_write(priv->regmap, A10_FPGAMGR_DCLKCNT_OFST, count); |
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/* wait till the dclkcnt done */ |
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regmap_read_poll_timeout(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, val, |
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val, 1, 100); |
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/* Clear DONE status. */ |
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regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, |
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A10_FPGAMGR_DCLKSTAT_DCLKDONE); |
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} |
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#define RBF_ENCRYPTION_MODE_OFFSET 69 |
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#define RBF_DECOMPRESS_OFFSET 229 |
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static int socfpga_a10_fpga_encrypted(u32 *buf32, size_t buf32_size) |
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{ |
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if (buf32_size < RBF_ENCRYPTION_MODE_OFFSET + 1) |
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return -EINVAL; |
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/* Is the bitstream encrypted? */ |
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return ((buf32[RBF_ENCRYPTION_MODE_OFFSET] >> 2) & 3) != 0; |
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} |
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static int socfpga_a10_fpga_compressed(u32 *buf32, size_t buf32_size) |
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{ |
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if (buf32_size < RBF_DECOMPRESS_OFFSET + 1) |
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return -EINVAL; |
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/* Is the bitstream compressed? */ |
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return !((buf32[RBF_DECOMPRESS_OFFSET] >> 1) & 1); |
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} |
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static unsigned int socfpga_a10_fpga_get_cd_ratio(unsigned int cfg_width, |
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bool encrypt, bool compress) |
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{ |
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unsigned int cd_ratio; |
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/* |
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* cd ratio is dependent on cfg width and whether the bitstream |
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* is encrypted and/or compressed. |
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* |
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* | width | encr. | compr. | cd ratio | |
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* | 16 | 0 | 0 | 1 | |
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* | 16 | 0 | 1 | 4 | |
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* | 16 | 1 | 0 | 2 | |
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* | 16 | 1 | 1 | 4 | |
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* | 32 | 0 | 0 | 1 | |
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* | 32 | 0 | 1 | 8 | |
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* | 32 | 1 | 0 | 4 | |
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* | 32 | 1 | 1 | 8 | |
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*/ |
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if (!compress && !encrypt) |
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return CDRATIO_x1; |
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if (compress) |
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cd_ratio = CDRATIO_x4; |
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else |
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cd_ratio = CDRATIO_x2; |
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/* If 32 bit, double the cd ratio by incrementing the field */ |
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if (cfg_width == CFGWDTH_32) |
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cd_ratio += 1; |
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return cd_ratio; |
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} |
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static int socfpga_a10_fpga_set_cdratio(struct fpga_manager *mgr, |
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unsigned int cfg_width, |
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const char *buf, size_t count) |
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{ |
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struct a10_fpga_priv *priv = mgr->priv; |
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unsigned int cd_ratio; |
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int encrypt, compress; |
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encrypt = socfpga_a10_fpga_encrypted((u32 *)buf, count / 4); |
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if (encrypt < 0) |
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return -EINVAL; |
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compress = socfpga_a10_fpga_compressed((u32 *)buf, count / 4); |
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if (compress < 0) |
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return -EINVAL; |
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cd_ratio = socfpga_a10_fpga_get_cd_ratio(cfg_width, encrypt, compress); |
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regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, |
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A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MASK, |
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cd_ratio << A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SHIFT); |
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return 0; |
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} |
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static u32 socfpga_a10_fpga_read_stat(struct a10_fpga_priv *priv) |
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{ |
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u32 val; |
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regmap_read(priv->regmap, A10_FPGAMGR_IMGCFG_STAT_OFST, &val); |
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return val; |
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} |
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static int socfpga_a10_fpga_wait_for_pr_ready(struct a10_fpga_priv *priv) |
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{ |
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u32 reg, i; |
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for (i = 0; i < 10 ; i++) { |
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reg = socfpga_a10_fpga_read_stat(priv); |
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if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR) |
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return -EINVAL; |
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if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY) |
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return 0; |
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} |
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return -ETIMEDOUT; |
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} |
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static int socfpga_a10_fpga_wait_for_pr_done(struct a10_fpga_priv *priv) |
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{ |
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u32 reg, i; |
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for (i = 0; i < 10 ; i++) { |
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reg = socfpga_a10_fpga_read_stat(priv); |
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if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR) |
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return -EINVAL; |
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if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE) |
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return 0; |
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} |
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return -ETIMEDOUT; |
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} |
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/* Start the FPGA programming by initialize the FPGA Manager */ |
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static int socfpga_a10_fpga_write_init(struct fpga_manager *mgr, |
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struct fpga_image_info *info, |
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const char *buf, size_t count) |
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{ |
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struct a10_fpga_priv *priv = mgr->priv; |
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unsigned int cfg_width; |
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u32 msel, stat, mask; |
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int ret; |
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if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) |
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cfg_width = CFGWDTH_16; |
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else |
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return -EINVAL; |
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/* Check for passive parallel (msel == 000 or 001) */ |
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msel = socfpga_a10_fpga_read_stat(priv); |
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msel &= A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK; |
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msel >>= A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT; |
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if ((msel != 0) && (msel != 1)) { |
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dev_dbg(&mgr->dev, "Fail: invalid msel=%d\n", msel); |
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return -EINVAL; |
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} |
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/* Make sure no external devices are interfering */ |
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stat = socfpga_a10_fpga_read_stat(priv); |
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mask = A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN | |
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A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN; |
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if ((stat & mask) != mask) |
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return -EINVAL; |
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/* Set cfg width */ |
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socfpga_a10_fpga_set_cfg_width(priv, cfg_width); |
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/* Determine cd ratio from bitstream header and set cd ratio */ |
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ret = socfpga_a10_fpga_set_cdratio(mgr, cfg_width, buf, count); |
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if (ret) |
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return ret; |
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/* |
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* Clear s2f_nce to enable chip select. Leave pr_request |
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* unasserted and override disabled. |
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*/ |
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regmap_write(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST, |
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A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG); |
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/* Set cfg_ctrl to enable s2f dclk and data */ |
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regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, |
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A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL, |
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A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL); |
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/* |
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* Disable overrides not needed for pr. |
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* s2f_config==1 leaves reset deasseted. |
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*/ |
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regmap_write(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_00_OFST, |
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A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG | |
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A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS | |
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A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE | |
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A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG); |
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/* Enable override for data, dclk, nce, and pr_request to CSS */ |
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regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST, |
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A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG, 0); |
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/* Send some clocks to clear out any errors */ |
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socfpga_a10_fpga_generate_dclks(priv, 256); |
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/* Assert pr_request */ |
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regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST, |
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A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST, |
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A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST); |
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/* Provide 2048 DCLKs before starting the config data streaming. */ |
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socfpga_a10_fpga_generate_dclks(priv, 0x7ff); |
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/* Wait for pr_ready */ |
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return socfpga_a10_fpga_wait_for_pr_ready(priv); |
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} |
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/* |
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* write data to the FPGA data register |
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*/ |
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static int socfpga_a10_fpga_write(struct fpga_manager *mgr, const char *buf, |
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size_t count) |
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{ |
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struct a10_fpga_priv *priv = mgr->priv; |
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u32 *buffer_32 = (u32 *)buf; |
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size_t i = 0; |
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if (count <= 0) |
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return -EINVAL; |
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/* Write out the complete 32-bit chunks */ |
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while (count >= sizeof(u32)) { |
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writel(buffer_32[i++], priv->fpga_data_addr); |
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count -= sizeof(u32); |
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} |
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/* Write out remaining non 32-bit chunks */ |
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switch (count) { |
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case 3: |
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writel(buffer_32[i++] & 0x00ffffff, priv->fpga_data_addr); |
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break; |
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case 2: |
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writel(buffer_32[i++] & 0x0000ffff, priv->fpga_data_addr); |
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break; |
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case 1: |
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writel(buffer_32[i++] & 0x000000ff, priv->fpga_data_addr); |
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break; |
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case 0: |
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break; |
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default: |
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/* This will never happen */ |
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return -EFAULT; |
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} |
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return 0; |
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} |
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static int socfpga_a10_fpga_write_complete(struct fpga_manager *mgr, |
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struct fpga_image_info *info) |
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{ |
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struct a10_fpga_priv *priv = mgr->priv; |
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u32 reg; |
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int ret; |
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/* Wait for pr_done */ |
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ret = socfpga_a10_fpga_wait_for_pr_done(priv); |
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/* Clear pr_request */ |
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regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST, |
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A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST, 0); |
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/* Send some clocks to clear out any errors */ |
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socfpga_a10_fpga_generate_dclks(priv, 256); |
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/* Disable s2f dclk and data */ |
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regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, |
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A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL, 0); |
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/* Deassert chip select */ |
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regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST, |
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A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCE, |
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A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCE); |
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/* Disable data, dclk, nce, and pr_request override to CSS */ |
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regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST, |
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A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG, |
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A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG); |
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/* Return any errors regarding pr_done or pr_error */ |
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if (ret) |
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return ret; |
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/* Final check */ |
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reg = socfpga_a10_fpga_read_stat(priv); |
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if (((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE) == 0) || |
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((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN) == 0) || |
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((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN) == 0)) { |
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dev_dbg(&mgr->dev, |
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"Timeout in final check. Status=%08xf\n", reg); |
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return -ETIMEDOUT; |
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} |
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return 0; |
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} |
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static enum fpga_mgr_states socfpga_a10_fpga_state(struct fpga_manager *mgr) |
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{ |
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struct a10_fpga_priv *priv = mgr->priv; |
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u32 reg = socfpga_a10_fpga_read_stat(priv); |
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if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE) |
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return FPGA_MGR_STATE_OPERATING; |
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if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY) |
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return FPGA_MGR_STATE_WRITE; |
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if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR) |
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return FPGA_MGR_STATE_WRITE_COMPLETE_ERR; |
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if ((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN) == 0) |
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return FPGA_MGR_STATE_RESET; |
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return FPGA_MGR_STATE_UNKNOWN; |
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} |
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static const struct fpga_manager_ops socfpga_a10_fpga_mgr_ops = { |
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.initial_header_size = (RBF_DECOMPRESS_OFFSET + 1) * 4, |
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.state = socfpga_a10_fpga_state, |
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.write_init = socfpga_a10_fpga_write_init, |
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.write = socfpga_a10_fpga_write, |
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.write_complete = socfpga_a10_fpga_write_complete, |
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}; |
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static int socfpga_a10_fpga_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct a10_fpga_priv *priv; |
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void __iomem *reg_base; |
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struct fpga_manager *mgr; |
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struct resource *res; |
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int ret; |
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|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
/* First mmio base is for register access */ |
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
reg_base = devm_ioremap_resource(dev, res); |
|
if (IS_ERR(reg_base)) |
|
return PTR_ERR(reg_base); |
|
|
|
/* Second mmio base is for writing FPGA image data */ |
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
|
priv->fpga_data_addr = devm_ioremap_resource(dev, res); |
|
if (IS_ERR(priv->fpga_data_addr)) |
|
return PTR_ERR(priv->fpga_data_addr); |
|
|
|
/* regmap for register access */ |
|
priv->regmap = devm_regmap_init_mmio(dev, reg_base, |
|
&socfpga_a10_fpga_regmap_config); |
|
if (IS_ERR(priv->regmap)) |
|
return -ENODEV; |
|
|
|
priv->clk = devm_clk_get(dev, NULL); |
|
if (IS_ERR(priv->clk)) { |
|
dev_err(dev, "no clock specified\n"); |
|
return PTR_ERR(priv->clk); |
|
} |
|
|
|
ret = clk_prepare_enable(priv->clk); |
|
if (ret) { |
|
dev_err(dev, "could not enable clock\n"); |
|
return -EBUSY; |
|
} |
|
|
|
mgr = devm_fpga_mgr_create(dev, "SoCFPGA Arria10 FPGA Manager", |
|
&socfpga_a10_fpga_mgr_ops, priv); |
|
if (!mgr) |
|
return -ENOMEM; |
|
|
|
platform_set_drvdata(pdev, mgr); |
|
|
|
ret = fpga_mgr_register(mgr); |
|
if (ret) { |
|
clk_disable_unprepare(priv->clk); |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int socfpga_a10_fpga_remove(struct platform_device *pdev) |
|
{ |
|
struct fpga_manager *mgr = platform_get_drvdata(pdev); |
|
struct a10_fpga_priv *priv = mgr->priv; |
|
|
|
fpga_mgr_unregister(mgr); |
|
clk_disable_unprepare(priv->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id socfpga_a10_fpga_of_match[] = { |
|
{ .compatible = "altr,socfpga-a10-fpga-mgr", }, |
|
{}, |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(of, socfpga_a10_fpga_of_match); |
|
|
|
static struct platform_driver socfpga_a10_fpga_driver = { |
|
.probe = socfpga_a10_fpga_probe, |
|
.remove = socfpga_a10_fpga_remove, |
|
.driver = { |
|
.name = "socfpga_a10_fpga_manager", |
|
.of_match_table = socfpga_a10_fpga_of_match, |
|
}, |
|
}; |
|
|
|
module_platform_driver(socfpga_a10_fpga_driver); |
|
|
|
MODULE_AUTHOR("Alan Tull <[email protected]>"); |
|
MODULE_DESCRIPTION("SoCFPGA Arria10 FPGA Manager"); |
|
MODULE_LICENSE("GPL v2");
|
|
|