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973 lines
25 KiB
973 lines
25 KiB
/* |
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* Qualcomm Technologies HIDMA DMA engine interface |
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* |
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* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 and |
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* only version 2 as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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|
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/* |
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* Copyright (C) Freescale Semicondutor, Inc. 2007, 2008. |
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* Copyright (C) Semihalf 2009 |
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* Copyright (C) Ilya Yanok, Emcraft Systems 2010 |
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* Copyright (C) Alexander Popov, Promcontroller 2014 |
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* |
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* Written by Piotr Ziecik <[email protected]>. Hardware description |
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* (defines, structures and comments) was taken from MPC5121 DMA driver |
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* written by Hongjun Chen <[email protected]>. |
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* |
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* Approved as OSADL project by a majority of OSADL members and funded |
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* by OSADL membership fees in 2009; for details see www.osadl.org. |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the Free |
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* Software Foundation; either version 2 of the License, or (at your option) |
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* any later version. |
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* |
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* This program is distributed in the hope that it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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* more details. |
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* |
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* The full GNU General Public License is included in this distribution in the |
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* file called COPYING. |
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*/ |
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|
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/* Linux Foundation elects GPLv2 license only. */ |
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|
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#include <linux/dmaengine.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/list.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/of_dma.h> |
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#include <linux/of_device.h> |
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#include <linux/property.h> |
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#include <linux/delay.h> |
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#include <linux/acpi.h> |
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#include <linux/irq.h> |
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#include <linux/atomic.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/msi.h> |
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|
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#include "../dmaengine.h" |
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#include "hidma.h" |
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|
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/* |
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* Default idle time is 2 seconds. This parameter can |
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* be overridden by changing the following |
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* /sys/bus/platform/devices/QCOM8061:<xy>/power/autosuspend_delay_ms |
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* during kernel boot. |
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*/ |
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#define HIDMA_AUTOSUSPEND_TIMEOUT 2000 |
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#define HIDMA_ERR_INFO_SW 0xFF |
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#define HIDMA_ERR_CODE_UNEXPECTED_TERMINATE 0x0 |
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#define HIDMA_NR_DEFAULT_DESC 10 |
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#define HIDMA_MSI_INTS 11 |
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static inline struct hidma_dev *to_hidma_dev(struct dma_device *dmadev) |
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{ |
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return container_of(dmadev, struct hidma_dev, ddev); |
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} |
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|
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static inline |
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struct hidma_dev *to_hidma_dev_from_lldev(struct hidma_lldev **_lldevp) |
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{ |
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return container_of(_lldevp, struct hidma_dev, lldev); |
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} |
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static inline struct hidma_chan *to_hidma_chan(struct dma_chan *dmach) |
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{ |
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return container_of(dmach, struct hidma_chan, chan); |
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} |
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static void hidma_free(struct hidma_dev *dmadev) |
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{ |
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INIT_LIST_HEAD(&dmadev->ddev.channels); |
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} |
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|
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static unsigned int nr_desc_prm; |
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module_param(nr_desc_prm, uint, 0644); |
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MODULE_PARM_DESC(nr_desc_prm, "number of descriptors (default: 0)"); |
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enum hidma_cap { |
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HIDMA_MSI_CAP = 1, |
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HIDMA_IDENTITY_CAP, |
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}; |
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/* process completed descriptors */ |
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static void hidma_process_completed(struct hidma_chan *mchan) |
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{ |
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struct dma_device *ddev = mchan->chan.device; |
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struct hidma_dev *mdma = to_hidma_dev(ddev); |
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struct dma_async_tx_descriptor *desc; |
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dma_cookie_t last_cookie; |
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struct hidma_desc *mdesc; |
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struct hidma_desc *next; |
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unsigned long irqflags; |
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struct list_head list; |
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INIT_LIST_HEAD(&list); |
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|
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/* Get all completed descriptors */ |
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spin_lock_irqsave(&mchan->lock, irqflags); |
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list_splice_tail_init(&mchan->completed, &list); |
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spin_unlock_irqrestore(&mchan->lock, irqflags); |
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|
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/* Execute callbacks and run dependencies */ |
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list_for_each_entry_safe(mdesc, next, &list, node) { |
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enum dma_status llstat; |
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struct dmaengine_desc_callback cb; |
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struct dmaengine_result result; |
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desc = &mdesc->desc; |
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last_cookie = desc->cookie; |
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llstat = hidma_ll_status(mdma->lldev, mdesc->tre_ch); |
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spin_lock_irqsave(&mchan->lock, irqflags); |
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if (llstat == DMA_COMPLETE) { |
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mchan->last_success = last_cookie; |
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result.result = DMA_TRANS_NOERROR; |
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} else { |
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result.result = DMA_TRANS_ABORTED; |
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} |
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dma_cookie_complete(desc); |
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spin_unlock_irqrestore(&mchan->lock, irqflags); |
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dmaengine_desc_get_callback(desc, &cb); |
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dma_run_dependencies(desc); |
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spin_lock_irqsave(&mchan->lock, irqflags); |
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list_move(&mdesc->node, &mchan->free); |
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spin_unlock_irqrestore(&mchan->lock, irqflags); |
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|
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dmaengine_desc_callback_invoke(&cb, &result); |
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} |
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} |
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/* |
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* Called once for each submitted descriptor. |
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* PM is locked once for each descriptor that is currently |
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* in execution. |
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*/ |
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static void hidma_callback(void *data) |
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{ |
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struct hidma_desc *mdesc = data; |
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struct hidma_chan *mchan = to_hidma_chan(mdesc->desc.chan); |
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struct dma_device *ddev = mchan->chan.device; |
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struct hidma_dev *dmadev = to_hidma_dev(ddev); |
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unsigned long irqflags; |
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bool queued = false; |
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spin_lock_irqsave(&mchan->lock, irqflags); |
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if (mdesc->node.next) { |
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/* Delete from the active list, add to completed list */ |
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list_move_tail(&mdesc->node, &mchan->completed); |
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queued = true; |
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|
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/* calculate the next running descriptor */ |
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mchan->running = list_first_entry(&mchan->active, |
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struct hidma_desc, node); |
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} |
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spin_unlock_irqrestore(&mchan->lock, irqflags); |
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hidma_process_completed(mchan); |
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if (queued) { |
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pm_runtime_mark_last_busy(dmadev->ddev.dev); |
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pm_runtime_put_autosuspend(dmadev->ddev.dev); |
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} |
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} |
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static int hidma_chan_init(struct hidma_dev *dmadev, u32 dma_sig) |
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{ |
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struct hidma_chan *mchan; |
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struct dma_device *ddev; |
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mchan = devm_kzalloc(dmadev->ddev.dev, sizeof(*mchan), GFP_KERNEL); |
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if (!mchan) |
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return -ENOMEM; |
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ddev = &dmadev->ddev; |
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mchan->dma_sig = dma_sig; |
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mchan->dmadev = dmadev; |
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mchan->chan.device = ddev; |
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dma_cookie_init(&mchan->chan); |
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INIT_LIST_HEAD(&mchan->free); |
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INIT_LIST_HEAD(&mchan->prepared); |
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INIT_LIST_HEAD(&mchan->active); |
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INIT_LIST_HEAD(&mchan->completed); |
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INIT_LIST_HEAD(&mchan->queued); |
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spin_lock_init(&mchan->lock); |
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list_add_tail(&mchan->chan.device_node, &ddev->channels); |
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dmadev->ddev.chancnt++; |
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return 0; |
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} |
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static void hidma_issue_task(struct tasklet_struct *t) |
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{ |
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struct hidma_dev *dmadev = from_tasklet(dmadev, t, task); |
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pm_runtime_get_sync(dmadev->ddev.dev); |
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hidma_ll_start(dmadev->lldev); |
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} |
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static void hidma_issue_pending(struct dma_chan *dmach) |
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{ |
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struct hidma_chan *mchan = to_hidma_chan(dmach); |
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struct hidma_dev *dmadev = mchan->dmadev; |
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unsigned long flags; |
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struct hidma_desc *qdesc, *next; |
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int status; |
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spin_lock_irqsave(&mchan->lock, flags); |
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list_for_each_entry_safe(qdesc, next, &mchan->queued, node) { |
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hidma_ll_queue_request(dmadev->lldev, qdesc->tre_ch); |
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list_move_tail(&qdesc->node, &mchan->active); |
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} |
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if (!mchan->running) { |
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struct hidma_desc *desc = list_first_entry(&mchan->active, |
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struct hidma_desc, |
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node); |
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mchan->running = desc; |
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} |
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spin_unlock_irqrestore(&mchan->lock, flags); |
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/* PM will be released in hidma_callback function. */ |
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status = pm_runtime_get(dmadev->ddev.dev); |
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if (status < 0) |
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tasklet_schedule(&dmadev->task); |
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else |
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hidma_ll_start(dmadev->lldev); |
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} |
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static inline bool hidma_txn_is_success(dma_cookie_t cookie, |
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dma_cookie_t last_success, dma_cookie_t last_used) |
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{ |
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if (last_success <= last_used) { |
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if ((cookie <= last_success) || (cookie > last_used)) |
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return true; |
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} else { |
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if ((cookie <= last_success) && (cookie > last_used)) |
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return true; |
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} |
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return false; |
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} |
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static enum dma_status hidma_tx_status(struct dma_chan *dmach, |
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dma_cookie_t cookie, |
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struct dma_tx_state *txstate) |
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{ |
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struct hidma_chan *mchan = to_hidma_chan(dmach); |
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enum dma_status ret; |
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ret = dma_cookie_status(dmach, cookie, txstate); |
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if (ret == DMA_COMPLETE) { |
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bool is_success; |
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is_success = hidma_txn_is_success(cookie, mchan->last_success, |
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dmach->cookie); |
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return is_success ? ret : DMA_ERROR; |
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} |
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if (mchan->paused && (ret == DMA_IN_PROGRESS)) { |
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unsigned long flags; |
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dma_cookie_t runcookie; |
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spin_lock_irqsave(&mchan->lock, flags); |
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if (mchan->running) |
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runcookie = mchan->running->desc.cookie; |
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else |
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runcookie = -EINVAL; |
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|
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if (runcookie == cookie) |
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ret = DMA_PAUSED; |
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spin_unlock_irqrestore(&mchan->lock, flags); |
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} |
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return ret; |
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} |
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/* |
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* Submit descriptor to hardware. |
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* Lock the PM for each descriptor we are sending. |
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*/ |
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static dma_cookie_t hidma_tx_submit(struct dma_async_tx_descriptor *txd) |
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{ |
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struct hidma_chan *mchan = to_hidma_chan(txd->chan); |
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struct hidma_dev *dmadev = mchan->dmadev; |
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struct hidma_desc *mdesc; |
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unsigned long irqflags; |
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dma_cookie_t cookie; |
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|
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pm_runtime_get_sync(dmadev->ddev.dev); |
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if (!hidma_ll_isenabled(dmadev->lldev)) { |
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pm_runtime_mark_last_busy(dmadev->ddev.dev); |
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pm_runtime_put_autosuspend(dmadev->ddev.dev); |
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return -ENODEV; |
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} |
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pm_runtime_mark_last_busy(dmadev->ddev.dev); |
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pm_runtime_put_autosuspend(dmadev->ddev.dev); |
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mdesc = container_of(txd, struct hidma_desc, desc); |
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spin_lock_irqsave(&mchan->lock, irqflags); |
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|
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/* Move descriptor to queued */ |
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list_move_tail(&mdesc->node, &mchan->queued); |
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|
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/* Update cookie */ |
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cookie = dma_cookie_assign(txd); |
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|
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spin_unlock_irqrestore(&mchan->lock, irqflags); |
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return cookie; |
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} |
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static int hidma_alloc_chan_resources(struct dma_chan *dmach) |
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{ |
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struct hidma_chan *mchan = to_hidma_chan(dmach); |
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struct hidma_dev *dmadev = mchan->dmadev; |
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struct hidma_desc *mdesc, *tmp; |
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unsigned long irqflags; |
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LIST_HEAD(descs); |
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unsigned int i; |
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int rc = 0; |
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|
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if (mchan->allocated) |
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return 0; |
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|
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/* Alloc descriptors for this channel */ |
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for (i = 0; i < dmadev->nr_descriptors; i++) { |
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mdesc = kzalloc(sizeof(struct hidma_desc), GFP_NOWAIT); |
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if (!mdesc) { |
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rc = -ENOMEM; |
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break; |
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} |
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dma_async_tx_descriptor_init(&mdesc->desc, dmach); |
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mdesc->desc.tx_submit = hidma_tx_submit; |
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|
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rc = hidma_ll_request(dmadev->lldev, mchan->dma_sig, |
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"DMA engine", hidma_callback, mdesc, |
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&mdesc->tre_ch); |
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if (rc) { |
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dev_err(dmach->device->dev, |
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"channel alloc failed at %u\n", i); |
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kfree(mdesc); |
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break; |
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} |
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list_add_tail(&mdesc->node, &descs); |
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} |
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|
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if (rc) { |
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/* return the allocated descriptors */ |
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list_for_each_entry_safe(mdesc, tmp, &descs, node) { |
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hidma_ll_free(dmadev->lldev, mdesc->tre_ch); |
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kfree(mdesc); |
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} |
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return rc; |
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} |
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|
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spin_lock_irqsave(&mchan->lock, irqflags); |
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list_splice_tail_init(&descs, &mchan->free); |
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mchan->allocated = true; |
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spin_unlock_irqrestore(&mchan->lock, irqflags); |
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return 1; |
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} |
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|
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static struct dma_async_tx_descriptor * |
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hidma_prep_dma_memcpy(struct dma_chan *dmach, dma_addr_t dest, dma_addr_t src, |
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size_t len, unsigned long flags) |
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{ |
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struct hidma_chan *mchan = to_hidma_chan(dmach); |
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struct hidma_desc *mdesc = NULL; |
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struct hidma_dev *mdma = mchan->dmadev; |
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unsigned long irqflags; |
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|
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/* Get free descriptor */ |
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spin_lock_irqsave(&mchan->lock, irqflags); |
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if (!list_empty(&mchan->free)) { |
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mdesc = list_first_entry(&mchan->free, struct hidma_desc, node); |
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list_del(&mdesc->node); |
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} |
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spin_unlock_irqrestore(&mchan->lock, irqflags); |
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|
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if (!mdesc) |
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return NULL; |
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|
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mdesc->desc.flags = flags; |
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hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch, |
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src, dest, len, flags, |
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HIDMA_TRE_MEMCPY); |
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|
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/* Place descriptor in prepared list */ |
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spin_lock_irqsave(&mchan->lock, irqflags); |
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list_add_tail(&mdesc->node, &mchan->prepared); |
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spin_unlock_irqrestore(&mchan->lock, irqflags); |
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|
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return &mdesc->desc; |
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} |
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|
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static struct dma_async_tx_descriptor * |
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hidma_prep_dma_memset(struct dma_chan *dmach, dma_addr_t dest, int value, |
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size_t len, unsigned long flags) |
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{ |
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struct hidma_chan *mchan = to_hidma_chan(dmach); |
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struct hidma_desc *mdesc = NULL; |
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struct hidma_dev *mdma = mchan->dmadev; |
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unsigned long irqflags; |
|
|
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/* Get free descriptor */ |
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spin_lock_irqsave(&mchan->lock, irqflags); |
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if (!list_empty(&mchan->free)) { |
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mdesc = list_first_entry(&mchan->free, struct hidma_desc, node); |
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list_del(&mdesc->node); |
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} |
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spin_unlock_irqrestore(&mchan->lock, irqflags); |
|
|
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if (!mdesc) |
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return NULL; |
|
|
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mdesc->desc.flags = flags; |
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hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch, |
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value, dest, len, flags, |
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HIDMA_TRE_MEMSET); |
|
|
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/* Place descriptor in prepared list */ |
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spin_lock_irqsave(&mchan->lock, irqflags); |
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list_add_tail(&mdesc->node, &mchan->prepared); |
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spin_unlock_irqrestore(&mchan->lock, irqflags); |
|
|
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return &mdesc->desc; |
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} |
|
|
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static int hidma_terminate_channel(struct dma_chan *chan) |
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{ |
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struct hidma_chan *mchan = to_hidma_chan(chan); |
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struct hidma_dev *dmadev = to_hidma_dev(mchan->chan.device); |
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struct hidma_desc *tmp, *mdesc; |
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unsigned long irqflags; |
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LIST_HEAD(list); |
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int rc; |
|
|
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pm_runtime_get_sync(dmadev->ddev.dev); |
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/* give completed requests a chance to finish */ |
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hidma_process_completed(mchan); |
|
|
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spin_lock_irqsave(&mchan->lock, irqflags); |
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mchan->last_success = 0; |
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list_splice_init(&mchan->active, &list); |
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list_splice_init(&mchan->prepared, &list); |
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list_splice_init(&mchan->completed, &list); |
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list_splice_init(&mchan->queued, &list); |
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spin_unlock_irqrestore(&mchan->lock, irqflags); |
|
|
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/* this suspends the existing transfer */ |
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rc = hidma_ll_disable(dmadev->lldev); |
|
if (rc) { |
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dev_err(dmadev->ddev.dev, "channel did not pause\n"); |
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goto out; |
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} |
|
|
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/* return all user requests */ |
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list_for_each_entry_safe(mdesc, tmp, &list, node) { |
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struct dma_async_tx_descriptor *txd = &mdesc->desc; |
|
|
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dma_descriptor_unmap(txd); |
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dmaengine_desc_get_callback_invoke(txd, NULL); |
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dma_run_dependencies(txd); |
|
|
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/* move myself to free_list */ |
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list_move(&mdesc->node, &mchan->free); |
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} |
|
|
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rc = hidma_ll_enable(dmadev->lldev); |
|
out: |
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pm_runtime_mark_last_busy(dmadev->ddev.dev); |
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pm_runtime_put_autosuspend(dmadev->ddev.dev); |
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return rc; |
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} |
|
|
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static int hidma_terminate_all(struct dma_chan *chan) |
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{ |
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struct hidma_chan *mchan = to_hidma_chan(chan); |
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struct hidma_dev *dmadev = to_hidma_dev(mchan->chan.device); |
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int rc; |
|
|
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rc = hidma_terminate_channel(chan); |
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if (rc) |
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return rc; |
|
|
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/* reinitialize the hardware */ |
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pm_runtime_get_sync(dmadev->ddev.dev); |
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rc = hidma_ll_setup(dmadev->lldev); |
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pm_runtime_mark_last_busy(dmadev->ddev.dev); |
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pm_runtime_put_autosuspend(dmadev->ddev.dev); |
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return rc; |
|
} |
|
|
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static void hidma_free_chan_resources(struct dma_chan *dmach) |
|
{ |
|
struct hidma_chan *mchan = to_hidma_chan(dmach); |
|
struct hidma_dev *mdma = mchan->dmadev; |
|
struct hidma_desc *mdesc, *tmp; |
|
unsigned long irqflags; |
|
LIST_HEAD(descs); |
|
|
|
/* terminate running transactions and free descriptors */ |
|
hidma_terminate_channel(dmach); |
|
|
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spin_lock_irqsave(&mchan->lock, irqflags); |
|
|
|
/* Move data */ |
|
list_splice_tail_init(&mchan->free, &descs); |
|
|
|
/* Free descriptors */ |
|
list_for_each_entry_safe(mdesc, tmp, &descs, node) { |
|
hidma_ll_free(mdma->lldev, mdesc->tre_ch); |
|
list_del(&mdesc->node); |
|
kfree(mdesc); |
|
} |
|
|
|
mchan->allocated = false; |
|
spin_unlock_irqrestore(&mchan->lock, irqflags); |
|
} |
|
|
|
static int hidma_pause(struct dma_chan *chan) |
|
{ |
|
struct hidma_chan *mchan; |
|
struct hidma_dev *dmadev; |
|
|
|
mchan = to_hidma_chan(chan); |
|
dmadev = to_hidma_dev(mchan->chan.device); |
|
if (!mchan->paused) { |
|
pm_runtime_get_sync(dmadev->ddev.dev); |
|
if (hidma_ll_disable(dmadev->lldev)) |
|
dev_warn(dmadev->ddev.dev, "channel did not stop\n"); |
|
mchan->paused = true; |
|
pm_runtime_mark_last_busy(dmadev->ddev.dev); |
|
pm_runtime_put_autosuspend(dmadev->ddev.dev); |
|
} |
|
return 0; |
|
} |
|
|
|
static int hidma_resume(struct dma_chan *chan) |
|
{ |
|
struct hidma_chan *mchan; |
|
struct hidma_dev *dmadev; |
|
int rc = 0; |
|
|
|
mchan = to_hidma_chan(chan); |
|
dmadev = to_hidma_dev(mchan->chan.device); |
|
if (mchan->paused) { |
|
pm_runtime_get_sync(dmadev->ddev.dev); |
|
rc = hidma_ll_enable(dmadev->lldev); |
|
if (!rc) |
|
mchan->paused = false; |
|
else |
|
dev_err(dmadev->ddev.dev, |
|
"failed to resume the channel"); |
|
pm_runtime_mark_last_busy(dmadev->ddev.dev); |
|
pm_runtime_put_autosuspend(dmadev->ddev.dev); |
|
} |
|
return rc; |
|
} |
|
|
|
static irqreturn_t hidma_chirq_handler(int chirq, void *arg) |
|
{ |
|
struct hidma_lldev *lldev = arg; |
|
|
|
/* |
|
* All interrupts are request driven. |
|
* HW doesn't send an interrupt by itself. |
|
*/ |
|
return hidma_ll_inthandler(chirq, lldev); |
|
} |
|
|
|
#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN |
|
static irqreturn_t hidma_chirq_handler_msi(int chirq, void *arg) |
|
{ |
|
struct hidma_lldev **lldevp = arg; |
|
struct hidma_dev *dmadev = to_hidma_dev_from_lldev(lldevp); |
|
|
|
return hidma_ll_inthandler_msi(chirq, *lldevp, |
|
1 << (chirq - dmadev->msi_virqbase)); |
|
} |
|
#endif |
|
|
|
static ssize_t hidma_show_values(struct device *dev, |
|
struct device_attribute *attr, char *buf) |
|
{ |
|
struct hidma_dev *mdev = dev_get_drvdata(dev); |
|
|
|
buf[0] = 0; |
|
|
|
if (strcmp(attr->attr.name, "chid") == 0) |
|
sprintf(buf, "%d\n", mdev->chidx); |
|
|
|
return strlen(buf); |
|
} |
|
|
|
static inline void hidma_sysfs_uninit(struct hidma_dev *dev) |
|
{ |
|
device_remove_file(dev->ddev.dev, dev->chid_attrs); |
|
} |
|
|
|
static struct device_attribute* |
|
hidma_create_sysfs_entry(struct hidma_dev *dev, char *name, int mode) |
|
{ |
|
struct device_attribute *attrs; |
|
char *name_copy; |
|
|
|
attrs = devm_kmalloc(dev->ddev.dev, sizeof(struct device_attribute), |
|
GFP_KERNEL); |
|
if (!attrs) |
|
return NULL; |
|
|
|
name_copy = devm_kstrdup(dev->ddev.dev, name, GFP_KERNEL); |
|
if (!name_copy) |
|
return NULL; |
|
|
|
attrs->attr.name = name_copy; |
|
attrs->attr.mode = mode; |
|
attrs->show = hidma_show_values; |
|
sysfs_attr_init(&attrs->attr); |
|
|
|
return attrs; |
|
} |
|
|
|
static int hidma_sysfs_init(struct hidma_dev *dev) |
|
{ |
|
dev->chid_attrs = hidma_create_sysfs_entry(dev, "chid", S_IRUGO); |
|
if (!dev->chid_attrs) |
|
return -ENOMEM; |
|
|
|
return device_create_file(dev->ddev.dev, dev->chid_attrs); |
|
} |
|
|
|
#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN |
|
static void hidma_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) |
|
{ |
|
struct device *dev = msi_desc_to_dev(desc); |
|
struct hidma_dev *dmadev = dev_get_drvdata(dev); |
|
|
|
if (!desc->platform.msi_index) { |
|
writel(msg->address_lo, dmadev->dev_evca + 0x118); |
|
writel(msg->address_hi, dmadev->dev_evca + 0x11C); |
|
writel(msg->data, dmadev->dev_evca + 0x120); |
|
} |
|
} |
|
#endif |
|
|
|
static void hidma_free_msis(struct hidma_dev *dmadev) |
|
{ |
|
#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN |
|
struct device *dev = dmadev->ddev.dev; |
|
struct msi_desc *desc; |
|
|
|
/* free allocated MSI interrupts above */ |
|
for_each_msi_entry(desc, dev) |
|
devm_free_irq(dev, desc->irq, &dmadev->lldev); |
|
|
|
platform_msi_domain_free_irqs(dev); |
|
#endif |
|
} |
|
|
|
static int hidma_request_msi(struct hidma_dev *dmadev, |
|
struct platform_device *pdev) |
|
{ |
|
#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN |
|
int rc; |
|
struct msi_desc *desc; |
|
struct msi_desc *failed_desc = NULL; |
|
|
|
rc = platform_msi_domain_alloc_irqs(&pdev->dev, HIDMA_MSI_INTS, |
|
hidma_write_msi_msg); |
|
if (rc) |
|
return rc; |
|
|
|
for_each_msi_entry(desc, &pdev->dev) { |
|
if (!desc->platform.msi_index) |
|
dmadev->msi_virqbase = desc->irq; |
|
|
|
rc = devm_request_irq(&pdev->dev, desc->irq, |
|
hidma_chirq_handler_msi, |
|
0, "qcom-hidma-msi", |
|
&dmadev->lldev); |
|
if (rc) { |
|
failed_desc = desc; |
|
break; |
|
} |
|
} |
|
|
|
if (rc) { |
|
/* free allocated MSI interrupts above */ |
|
for_each_msi_entry(desc, &pdev->dev) { |
|
if (desc == failed_desc) |
|
break; |
|
devm_free_irq(&pdev->dev, desc->irq, |
|
&dmadev->lldev); |
|
} |
|
} else { |
|
/* Add callback to free MSIs on teardown */ |
|
hidma_ll_setup_irq(dmadev->lldev, true); |
|
|
|
} |
|
if (rc) |
|
dev_warn(&pdev->dev, |
|
"failed to request MSI irq, falling back to wired IRQ\n"); |
|
return rc; |
|
#else |
|
return -EINVAL; |
|
#endif |
|
} |
|
|
|
static bool hidma_test_capability(struct device *dev, enum hidma_cap test_cap) |
|
{ |
|
enum hidma_cap cap; |
|
|
|
cap = (enum hidma_cap) device_get_match_data(dev); |
|
return cap ? ((cap & test_cap) > 0) : 0; |
|
} |
|
|
|
static int hidma_probe(struct platform_device *pdev) |
|
{ |
|
struct hidma_dev *dmadev; |
|
struct resource *trca_resource; |
|
struct resource *evca_resource; |
|
int chirq; |
|
void __iomem *evca; |
|
void __iomem *trca; |
|
int rc; |
|
bool msi; |
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT); |
|
pm_runtime_use_autosuspend(&pdev->dev); |
|
pm_runtime_set_active(&pdev->dev); |
|
pm_runtime_enable(&pdev->dev); |
|
|
|
trca_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
trca = devm_ioremap_resource(&pdev->dev, trca_resource); |
|
if (IS_ERR(trca)) { |
|
rc = -ENOMEM; |
|
goto bailout; |
|
} |
|
|
|
evca_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
|
evca = devm_ioremap_resource(&pdev->dev, evca_resource); |
|
if (IS_ERR(evca)) { |
|
rc = -ENOMEM; |
|
goto bailout; |
|
} |
|
|
|
/* |
|
* This driver only handles the channel IRQs. |
|
* Common IRQ is handled by the management driver. |
|
*/ |
|
chirq = platform_get_irq(pdev, 0); |
|
if (chirq < 0) { |
|
rc = -ENODEV; |
|
goto bailout; |
|
} |
|
|
|
dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL); |
|
if (!dmadev) { |
|
rc = -ENOMEM; |
|
goto bailout; |
|
} |
|
|
|
INIT_LIST_HEAD(&dmadev->ddev.channels); |
|
spin_lock_init(&dmadev->lock); |
|
dmadev->ddev.dev = &pdev->dev; |
|
pm_runtime_get_sync(dmadev->ddev.dev); |
|
|
|
dma_cap_set(DMA_MEMCPY, dmadev->ddev.cap_mask); |
|
dma_cap_set(DMA_MEMSET, dmadev->ddev.cap_mask); |
|
if (WARN_ON(!pdev->dev.dma_mask)) { |
|
rc = -ENXIO; |
|
goto dmafree; |
|
} |
|
|
|
dmadev->dev_evca = evca; |
|
dmadev->evca_resource = evca_resource; |
|
dmadev->dev_trca = trca; |
|
dmadev->trca_resource = trca_resource; |
|
dmadev->ddev.device_prep_dma_memcpy = hidma_prep_dma_memcpy; |
|
dmadev->ddev.device_prep_dma_memset = hidma_prep_dma_memset; |
|
dmadev->ddev.device_alloc_chan_resources = hidma_alloc_chan_resources; |
|
dmadev->ddev.device_free_chan_resources = hidma_free_chan_resources; |
|
dmadev->ddev.device_tx_status = hidma_tx_status; |
|
dmadev->ddev.device_issue_pending = hidma_issue_pending; |
|
dmadev->ddev.device_pause = hidma_pause; |
|
dmadev->ddev.device_resume = hidma_resume; |
|
dmadev->ddev.device_terminate_all = hidma_terminate_all; |
|
dmadev->ddev.copy_align = 8; |
|
|
|
/* |
|
* Determine the MSI capability of the platform. Old HW doesn't |
|
* support MSI. |
|
*/ |
|
msi = hidma_test_capability(&pdev->dev, HIDMA_MSI_CAP); |
|
device_property_read_u32(&pdev->dev, "desc-count", |
|
&dmadev->nr_descriptors); |
|
|
|
if (nr_desc_prm) { |
|
dev_info(&pdev->dev, "overriding number of descriptors as %d\n", |
|
nr_desc_prm); |
|
dmadev->nr_descriptors = nr_desc_prm; |
|
} |
|
|
|
if (!dmadev->nr_descriptors) |
|
dmadev->nr_descriptors = HIDMA_NR_DEFAULT_DESC; |
|
|
|
if (hidma_test_capability(&pdev->dev, HIDMA_IDENTITY_CAP)) |
|
dmadev->chidx = readl(dmadev->dev_trca + 0x40); |
|
else |
|
dmadev->chidx = readl(dmadev->dev_trca + 0x28); |
|
|
|
/* Set DMA mask to 64 bits. */ |
|
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
|
if (rc) { |
|
dev_warn(&pdev->dev, "unable to set coherent mask to 64"); |
|
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
|
if (rc) |
|
goto dmafree; |
|
} |
|
|
|
dmadev->lldev = hidma_ll_init(dmadev->ddev.dev, |
|
dmadev->nr_descriptors, dmadev->dev_trca, |
|
dmadev->dev_evca, dmadev->chidx); |
|
if (!dmadev->lldev) { |
|
rc = -EPROBE_DEFER; |
|
goto dmafree; |
|
} |
|
|
|
platform_set_drvdata(pdev, dmadev); |
|
if (msi) |
|
rc = hidma_request_msi(dmadev, pdev); |
|
|
|
if (!msi || rc) { |
|
hidma_ll_setup_irq(dmadev->lldev, false); |
|
rc = devm_request_irq(&pdev->dev, chirq, hidma_chirq_handler, |
|
0, "qcom-hidma", dmadev->lldev); |
|
if (rc) |
|
goto uninit; |
|
} |
|
|
|
INIT_LIST_HEAD(&dmadev->ddev.channels); |
|
rc = hidma_chan_init(dmadev, 0); |
|
if (rc) |
|
goto uninit; |
|
|
|
rc = dma_async_device_register(&dmadev->ddev); |
|
if (rc) |
|
goto uninit; |
|
|
|
dmadev->irq = chirq; |
|
tasklet_setup(&dmadev->task, hidma_issue_task); |
|
hidma_debug_init(dmadev); |
|
hidma_sysfs_init(dmadev); |
|
dev_info(&pdev->dev, "HI-DMA engine driver registration complete\n"); |
|
pm_runtime_mark_last_busy(dmadev->ddev.dev); |
|
pm_runtime_put_autosuspend(dmadev->ddev.dev); |
|
return 0; |
|
|
|
uninit: |
|
if (msi) |
|
hidma_free_msis(dmadev); |
|
|
|
hidma_ll_uninit(dmadev->lldev); |
|
dmafree: |
|
if (dmadev) |
|
hidma_free(dmadev); |
|
bailout: |
|
pm_runtime_put_sync(&pdev->dev); |
|
pm_runtime_disable(&pdev->dev); |
|
return rc; |
|
} |
|
|
|
static void hidma_shutdown(struct platform_device *pdev) |
|
{ |
|
struct hidma_dev *dmadev = platform_get_drvdata(pdev); |
|
|
|
dev_info(dmadev->ddev.dev, "HI-DMA engine shutdown\n"); |
|
|
|
pm_runtime_get_sync(dmadev->ddev.dev); |
|
if (hidma_ll_disable(dmadev->lldev)) |
|
dev_warn(dmadev->ddev.dev, "channel did not stop\n"); |
|
pm_runtime_mark_last_busy(dmadev->ddev.dev); |
|
pm_runtime_put_autosuspend(dmadev->ddev.dev); |
|
|
|
} |
|
|
|
static int hidma_remove(struct platform_device *pdev) |
|
{ |
|
struct hidma_dev *dmadev = platform_get_drvdata(pdev); |
|
|
|
pm_runtime_get_sync(dmadev->ddev.dev); |
|
dma_async_device_unregister(&dmadev->ddev); |
|
if (!dmadev->lldev->msi_support) |
|
devm_free_irq(dmadev->ddev.dev, dmadev->irq, dmadev->lldev); |
|
else |
|
hidma_free_msis(dmadev); |
|
|
|
tasklet_kill(&dmadev->task); |
|
hidma_sysfs_uninit(dmadev); |
|
hidma_debug_uninit(dmadev); |
|
hidma_ll_uninit(dmadev->lldev); |
|
hidma_free(dmadev); |
|
|
|
dev_info(&pdev->dev, "HI-DMA engine removed\n"); |
|
pm_runtime_put_sync_suspend(&pdev->dev); |
|
pm_runtime_disable(&pdev->dev); |
|
|
|
return 0; |
|
} |
|
|
|
#if IS_ENABLED(CONFIG_ACPI) |
|
static const struct acpi_device_id hidma_acpi_ids[] = { |
|
{"QCOM8061"}, |
|
{"QCOM8062", HIDMA_MSI_CAP}, |
|
{"QCOM8063", (HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP)}, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids); |
|
#endif |
|
|
|
static const struct of_device_id hidma_match[] = { |
|
{.compatible = "qcom,hidma-1.0",}, |
|
{.compatible = "qcom,hidma-1.1", .data = (void *)(HIDMA_MSI_CAP),}, |
|
{.compatible = "qcom,hidma-1.2", |
|
.data = (void *)(HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP),}, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, hidma_match); |
|
|
|
static struct platform_driver hidma_driver = { |
|
.probe = hidma_probe, |
|
.remove = hidma_remove, |
|
.shutdown = hidma_shutdown, |
|
.driver = { |
|
.name = "hidma", |
|
.of_match_table = hidma_match, |
|
.acpi_match_table = ACPI_PTR(hidma_acpi_ids), |
|
}, |
|
}; |
|
|
|
module_platform_driver(hidma_driver); |
|
MODULE_LICENSE("GPL v2");
|
|
|