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367 lines
8.7 KiB
367 lines
8.7 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2008 |
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* Guennadi Liakhovetski, DENX Software Engineering, <[email protected]> |
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*/ |
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#include <linux/init.h> |
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#include <linux/err.h> |
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#include <linux/spinlock.h> |
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#include <linux/delay.h> |
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#include <linux/clk.h> |
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#include <linux/irq.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/dma/ipu-dma.h> |
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#include "ipu_intern.h" |
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/* |
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* Register read / write - shall be inlined by the compiler |
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*/ |
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static u32 ipu_read_reg(struct ipu *ipu, unsigned long reg) |
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{ |
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return __raw_readl(ipu->reg_ipu + reg); |
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} |
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static void ipu_write_reg(struct ipu *ipu, u32 value, unsigned long reg) |
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{ |
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__raw_writel(value, ipu->reg_ipu + reg); |
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} |
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/* |
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* IPU IRQ chip driver |
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*/ |
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#define IPU_IRQ_NR_FN_BANKS 3 |
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#define IPU_IRQ_NR_ERR_BANKS 2 |
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#define IPU_IRQ_NR_BANKS (IPU_IRQ_NR_FN_BANKS + IPU_IRQ_NR_ERR_BANKS) |
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struct ipu_irq_bank { |
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unsigned int control; |
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unsigned int status; |
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struct ipu *ipu; |
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}; |
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static struct ipu_irq_bank irq_bank[IPU_IRQ_NR_BANKS] = { |
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/* 3 groups of functional interrupts */ |
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{ |
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.control = IPU_INT_CTRL_1, |
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.status = IPU_INT_STAT_1, |
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}, { |
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.control = IPU_INT_CTRL_2, |
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.status = IPU_INT_STAT_2, |
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}, { |
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.control = IPU_INT_CTRL_3, |
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.status = IPU_INT_STAT_3, |
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}, |
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/* 2 groups of error interrupts */ |
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{ |
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.control = IPU_INT_CTRL_4, |
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.status = IPU_INT_STAT_4, |
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}, { |
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.control = IPU_INT_CTRL_5, |
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.status = IPU_INT_STAT_5, |
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}, |
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}; |
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struct ipu_irq_map { |
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unsigned int irq; |
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int source; |
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struct ipu_irq_bank *bank; |
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struct ipu *ipu; |
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}; |
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static struct ipu_irq_map irq_map[CONFIG_MX3_IPU_IRQS]; |
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/* Protects allocations from the above array of maps */ |
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static DEFINE_MUTEX(map_lock); |
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/* Protects register accesses and individual mappings */ |
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static DEFINE_RAW_SPINLOCK(bank_lock); |
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static struct ipu_irq_map *src2map(unsigned int src) |
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{ |
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int i; |
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for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) |
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if (irq_map[i].source == src) |
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return irq_map + i; |
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return NULL; |
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} |
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static void ipu_irq_unmask(struct irq_data *d) |
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{ |
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struct ipu_irq_map *map = irq_data_get_irq_chip_data(d); |
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struct ipu_irq_bank *bank; |
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uint32_t reg; |
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unsigned long lock_flags; |
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raw_spin_lock_irqsave(&bank_lock, lock_flags); |
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bank = map->bank; |
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if (!bank) { |
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raw_spin_unlock_irqrestore(&bank_lock, lock_flags); |
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pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq); |
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return; |
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} |
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reg = ipu_read_reg(bank->ipu, bank->control); |
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reg |= (1UL << (map->source & 31)); |
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ipu_write_reg(bank->ipu, reg, bank->control); |
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raw_spin_unlock_irqrestore(&bank_lock, lock_flags); |
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} |
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static void ipu_irq_mask(struct irq_data *d) |
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{ |
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struct ipu_irq_map *map = irq_data_get_irq_chip_data(d); |
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struct ipu_irq_bank *bank; |
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uint32_t reg; |
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unsigned long lock_flags; |
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raw_spin_lock_irqsave(&bank_lock, lock_flags); |
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bank = map->bank; |
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if (!bank) { |
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raw_spin_unlock_irqrestore(&bank_lock, lock_flags); |
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pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq); |
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return; |
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} |
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reg = ipu_read_reg(bank->ipu, bank->control); |
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reg &= ~(1UL << (map->source & 31)); |
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ipu_write_reg(bank->ipu, reg, bank->control); |
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raw_spin_unlock_irqrestore(&bank_lock, lock_flags); |
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} |
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static void ipu_irq_ack(struct irq_data *d) |
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{ |
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struct ipu_irq_map *map = irq_data_get_irq_chip_data(d); |
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struct ipu_irq_bank *bank; |
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unsigned long lock_flags; |
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raw_spin_lock_irqsave(&bank_lock, lock_flags); |
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bank = map->bank; |
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if (!bank) { |
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raw_spin_unlock_irqrestore(&bank_lock, lock_flags); |
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pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq); |
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return; |
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} |
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ipu_write_reg(bank->ipu, 1UL << (map->source & 31), bank->status); |
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raw_spin_unlock_irqrestore(&bank_lock, lock_flags); |
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} |
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/** |
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* ipu_irq_status() - returns the current interrupt status of the specified IRQ. |
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* @irq: interrupt line to get status for. |
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* @return: true if the interrupt is pending/asserted or false if the |
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* interrupt is not pending. |
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*/ |
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bool ipu_irq_status(unsigned int irq) |
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{ |
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struct ipu_irq_map *map = irq_get_chip_data(irq); |
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struct ipu_irq_bank *bank; |
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unsigned long lock_flags; |
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bool ret; |
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raw_spin_lock_irqsave(&bank_lock, lock_flags); |
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bank = map->bank; |
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ret = bank && ipu_read_reg(bank->ipu, bank->status) & |
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(1UL << (map->source & 31)); |
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raw_spin_unlock_irqrestore(&bank_lock, lock_flags); |
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return ret; |
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} |
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/** |
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* ipu_irq_map() - map an IPU interrupt source to an IRQ number |
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* @source: interrupt source bit position (see below) |
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* @return: mapped IRQ number or negative error code |
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* |
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* The source parameter has to be explained further. On i.MX31 IPU has 137 IRQ |
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* sources, they are broken down in 5 32-bit registers, like 32, 32, 24, 32, 17. |
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* However, the source argument of this function is not the sequence number of |
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* the possible IRQ, but rather its bit position. So, first interrupt in fourth |
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* register has source number 96, and not 88. This makes calculations easier, |
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* and also provides forward compatibility with any future IPU implementations |
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* with any interrupt bit assignments. |
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*/ |
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int ipu_irq_map(unsigned int source) |
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{ |
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int i, ret = -ENOMEM; |
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struct ipu_irq_map *map; |
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might_sleep(); |
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mutex_lock(&map_lock); |
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map = src2map(source); |
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if (map) { |
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pr_err("IPU: Source %u already mapped to IRQ %u\n", source, map->irq); |
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ret = -EBUSY; |
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goto out; |
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} |
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for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) { |
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if (irq_map[i].source < 0) { |
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unsigned long lock_flags; |
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raw_spin_lock_irqsave(&bank_lock, lock_flags); |
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irq_map[i].source = source; |
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irq_map[i].bank = irq_bank + source / 32; |
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raw_spin_unlock_irqrestore(&bank_lock, lock_flags); |
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ret = irq_map[i].irq; |
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pr_debug("IPU: mapped source %u to IRQ %u\n", |
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source, ret); |
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break; |
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} |
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} |
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out: |
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mutex_unlock(&map_lock); |
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if (ret < 0) |
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pr_err("IPU: couldn't map source %u: %d\n", source, ret); |
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return ret; |
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} |
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/** |
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* ipu_irq_unmap() - unmap an IPU interrupt source |
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* @source: interrupt source bit position (see ipu_irq_map()) |
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* @return: 0 or negative error code |
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*/ |
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int ipu_irq_unmap(unsigned int source) |
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{ |
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int i, ret = -EINVAL; |
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might_sleep(); |
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mutex_lock(&map_lock); |
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for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) { |
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if (irq_map[i].source == source) { |
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unsigned long lock_flags; |
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pr_debug("IPU: unmapped source %u from IRQ %u\n", |
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source, irq_map[i].irq); |
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raw_spin_lock_irqsave(&bank_lock, lock_flags); |
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irq_map[i].source = -EINVAL; |
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irq_map[i].bank = NULL; |
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raw_spin_unlock_irqrestore(&bank_lock, lock_flags); |
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ret = 0; |
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break; |
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} |
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} |
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mutex_unlock(&map_lock); |
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return ret; |
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} |
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/* Chained IRQ handler for IPU function and error interrupt */ |
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static void ipu_irq_handler(struct irq_desc *desc) |
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{ |
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struct ipu *ipu = irq_desc_get_handler_data(desc); |
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u32 status; |
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int i, line; |
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for (i = 0; i < IPU_IRQ_NR_BANKS; i++) { |
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struct ipu_irq_bank *bank = irq_bank + i; |
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raw_spin_lock(&bank_lock); |
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status = ipu_read_reg(ipu, bank->status); |
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/* |
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* Don't think we have to clear all interrupts here, they will |
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* be acked by ->handle_irq() (handle_level_irq). However, we |
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* might want to clear unhandled interrupts after the loop... |
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*/ |
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status &= ipu_read_reg(ipu, bank->control); |
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raw_spin_unlock(&bank_lock); |
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while ((line = ffs(status))) { |
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struct ipu_irq_map *map; |
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unsigned int irq; |
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line--; |
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status &= ~(1UL << line); |
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raw_spin_lock(&bank_lock); |
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map = src2map(32 * i + line); |
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if (!map) { |
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raw_spin_unlock(&bank_lock); |
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pr_err("IPU: Interrupt on unmapped source %u bank %d\n", |
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line, i); |
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continue; |
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} |
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irq = map->irq; |
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raw_spin_unlock(&bank_lock); |
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generic_handle_irq(irq); |
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} |
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} |
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} |
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static struct irq_chip ipu_irq_chip = { |
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.name = "ipu_irq", |
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.irq_ack = ipu_irq_ack, |
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.irq_mask = ipu_irq_mask, |
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.irq_unmask = ipu_irq_unmask, |
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}; |
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/* Install the IRQ handler */ |
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int __init ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev) |
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{ |
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unsigned int irq, i; |
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int irq_base = irq_alloc_descs(-1, 0, CONFIG_MX3_IPU_IRQS, |
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numa_node_id()); |
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if (irq_base < 0) |
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return irq_base; |
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for (i = 0; i < IPU_IRQ_NR_BANKS; i++) |
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irq_bank[i].ipu = ipu; |
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for (i = 0; i < CONFIG_MX3_IPU_IRQS; i++) { |
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int ret; |
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irq = irq_base + i; |
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ret = irq_set_chip(irq, &ipu_irq_chip); |
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if (ret < 0) |
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return ret; |
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ret = irq_set_chip_data(irq, irq_map + i); |
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if (ret < 0) |
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return ret; |
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irq_map[i].ipu = ipu; |
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irq_map[i].irq = irq; |
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irq_map[i].source = -EINVAL; |
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irq_set_handler(irq, handle_level_irq); |
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irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); |
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} |
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irq_set_chained_handler_and_data(ipu->irq_fn, ipu_irq_handler, ipu); |
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irq_set_chained_handler_and_data(ipu->irq_err, ipu_irq_handler, ipu); |
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ipu->irq_base = irq_base; |
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return 0; |
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} |
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void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev) |
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{ |
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unsigned int irq, irq_base; |
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irq_base = ipu->irq_base; |
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irq_set_chained_handler_and_data(ipu->irq_fn, NULL, NULL); |
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irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL); |
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for (irq = irq_base; irq < irq_base + CONFIG_MX3_IPU_IRQS; irq++) { |
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irq_set_status_flags(irq, IRQ_NOREQUEST); |
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irq_set_chip(irq, NULL); |
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irq_set_chip_data(irq, NULL); |
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} |
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}
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