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229 lines
6.3 KiB
229 lines
6.3 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Driver for the Intel integrated DMA 64-bit |
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* |
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* Copyright (C) 2015 Intel Corporation |
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*/ |
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#ifndef __DMA_IDMA64_H__ |
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#define __DMA_IDMA64_H__ |
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#include <linux/device.h> |
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#include <linux/io.h> |
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#include <linux/spinlock.h> |
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#include <linux/types.h> |
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#include <linux/io-64-nonatomic-lo-hi.h> |
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#include "virt-dma.h" |
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/* Channel registers */ |
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#define IDMA64_CH_SAR 0x00 /* Source Address Register */ |
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#define IDMA64_CH_DAR 0x08 /* Destination Address Register */ |
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#define IDMA64_CH_LLP 0x10 /* Linked List Pointer */ |
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#define IDMA64_CH_CTL_LO 0x18 /* Control Register Low */ |
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#define IDMA64_CH_CTL_HI 0x1c /* Control Register High */ |
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#define IDMA64_CH_SSTAT 0x20 |
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#define IDMA64_CH_DSTAT 0x28 |
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#define IDMA64_CH_SSTATAR 0x30 |
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#define IDMA64_CH_DSTATAR 0x38 |
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#define IDMA64_CH_CFG_LO 0x40 /* Configuration Register Low */ |
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#define IDMA64_CH_CFG_HI 0x44 /* Configuration Register High */ |
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#define IDMA64_CH_SGR 0x48 |
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#define IDMA64_CH_DSR 0x50 |
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#define IDMA64_CH_LENGTH 0x58 |
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/* Bitfields in CTL_LO */ |
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#define IDMA64C_CTLL_INT_EN (1 << 0) /* irqs enabled? */ |
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#define IDMA64C_CTLL_DST_WIDTH(x) ((x) << 1) /* bytes per element */ |
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#define IDMA64C_CTLL_SRC_WIDTH(x) ((x) << 4) |
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#define IDMA64C_CTLL_DST_INC (0 << 8) /* DAR update/not */ |
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#define IDMA64C_CTLL_DST_FIX (1 << 8) |
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#define IDMA64C_CTLL_SRC_INC (0 << 10) /* SAR update/not */ |
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#define IDMA64C_CTLL_SRC_FIX (1 << 10) |
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#define IDMA64C_CTLL_DST_MSIZE(x) ((x) << 11) /* burst, #elements */ |
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#define IDMA64C_CTLL_SRC_MSIZE(x) ((x) << 14) |
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#define IDMA64C_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ |
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#define IDMA64C_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ |
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#define IDMA64C_CTLL_LLP_D_EN (1 << 27) /* dest block chain */ |
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#define IDMA64C_CTLL_LLP_S_EN (1 << 28) /* src block chain */ |
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/* Bitfields in CTL_HI */ |
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#define IDMA64C_CTLH_BLOCK_TS_MASK ((1 << 17) - 1) |
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#define IDMA64C_CTLH_BLOCK_TS(x) ((x) & IDMA64C_CTLH_BLOCK_TS_MASK) |
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#define IDMA64C_CTLH_DONE (1 << 17) |
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/* Bitfields in CFG_LO */ |
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#define IDMA64C_CFGL_DST_BURST_ALIGN (1 << 0) /* dst burst align */ |
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#define IDMA64C_CFGL_SRC_BURST_ALIGN (1 << 1) /* src burst align */ |
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#define IDMA64C_CFGL_CH_SUSP (1 << 8) |
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#define IDMA64C_CFGL_FIFO_EMPTY (1 << 9) |
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#define IDMA64C_CFGL_CH_DRAIN (1 << 10) /* drain FIFO */ |
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#define IDMA64C_CFGL_DST_OPT_BL (1 << 20) /* optimize dst burst length */ |
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#define IDMA64C_CFGL_SRC_OPT_BL (1 << 21) /* optimize src burst length */ |
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/* Bitfields in CFG_HI */ |
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#define IDMA64C_CFGH_SRC_PER(x) ((x) << 0) /* src peripheral */ |
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#define IDMA64C_CFGH_DST_PER(x) ((x) << 4) /* dst peripheral */ |
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#define IDMA64C_CFGH_RD_ISSUE_THD(x) ((x) << 8) |
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#define IDMA64C_CFGH_WR_ISSUE_THD(x) ((x) << 18) |
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/* Interrupt registers */ |
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#define IDMA64_INT_XFER 0x00 |
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#define IDMA64_INT_BLOCK 0x08 |
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#define IDMA64_INT_SRC_TRAN 0x10 |
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#define IDMA64_INT_DST_TRAN 0x18 |
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#define IDMA64_INT_ERROR 0x20 |
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#define IDMA64_RAW(x) (0x2c0 + IDMA64_INT_##x) /* r */ |
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#define IDMA64_STATUS(x) (0x2e8 + IDMA64_INT_##x) /* r (raw & mask) */ |
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#define IDMA64_MASK(x) (0x310 + IDMA64_INT_##x) /* rw (set = irq enabled) */ |
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#define IDMA64_CLEAR(x) (0x338 + IDMA64_INT_##x) /* w (ack, affects "raw") */ |
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/* Common registers */ |
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#define IDMA64_STATUS_INT 0x360 /* r */ |
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#define IDMA64_CFG 0x398 |
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#define IDMA64_CH_EN 0x3a0 |
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/* Bitfields in CFG */ |
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#define IDMA64_CFG_DMA_EN (1 << 0) |
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/* Hardware descriptor for Linked LIst transfers */ |
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struct idma64_lli { |
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u64 sar; |
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u64 dar; |
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u64 llp; |
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u32 ctllo; |
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u32 ctlhi; |
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u32 sstat; |
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u32 dstat; |
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}; |
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struct idma64_hw_desc { |
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struct idma64_lli *lli; |
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dma_addr_t llp; |
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dma_addr_t phys; |
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unsigned int len; |
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}; |
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struct idma64_desc { |
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struct virt_dma_desc vdesc; |
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enum dma_transfer_direction direction; |
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struct idma64_hw_desc *hw; |
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unsigned int ndesc; |
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size_t length; |
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enum dma_status status; |
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}; |
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static inline struct idma64_desc *to_idma64_desc(struct virt_dma_desc *vdesc) |
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{ |
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return container_of(vdesc, struct idma64_desc, vdesc); |
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} |
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struct idma64_chan { |
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struct virt_dma_chan vchan; |
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void __iomem *regs; |
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/* hardware configuration */ |
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enum dma_transfer_direction direction; |
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unsigned int mask; |
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struct dma_slave_config config; |
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void *pool; |
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struct idma64_desc *desc; |
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}; |
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static inline struct idma64_chan *to_idma64_chan(struct dma_chan *chan) |
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{ |
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return container_of(chan, struct idma64_chan, vchan.chan); |
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} |
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#define channel_set_bit(idma64, reg, mask) \ |
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dma_writel(idma64, reg, ((mask) << 8) | (mask)) |
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#define channel_clear_bit(idma64, reg, mask) \ |
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dma_writel(idma64, reg, ((mask) << 8) | 0) |
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static inline u32 idma64c_readl(struct idma64_chan *idma64c, int offset) |
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{ |
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return readl(idma64c->regs + offset); |
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} |
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static inline void idma64c_writel(struct idma64_chan *idma64c, int offset, |
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u32 value) |
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{ |
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writel(value, idma64c->regs + offset); |
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} |
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#define channel_readl(idma64c, reg) \ |
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idma64c_readl(idma64c, IDMA64_CH_##reg) |
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#define channel_writel(idma64c, reg, value) \ |
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idma64c_writel(idma64c, IDMA64_CH_##reg, (value)) |
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static inline u64 idma64c_readq(struct idma64_chan *idma64c, int offset) |
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{ |
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return lo_hi_readq(idma64c->regs + offset); |
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} |
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static inline void idma64c_writeq(struct idma64_chan *idma64c, int offset, |
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u64 value) |
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{ |
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lo_hi_writeq(value, idma64c->regs + offset); |
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} |
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#define channel_readq(idma64c, reg) \ |
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idma64c_readq(idma64c, IDMA64_CH_##reg) |
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#define channel_writeq(idma64c, reg, value) \ |
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idma64c_writeq(idma64c, IDMA64_CH_##reg, (value)) |
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struct idma64 { |
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struct dma_device dma; |
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void __iomem *regs; |
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/* channels */ |
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unsigned short all_chan_mask; |
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struct idma64_chan *chan; |
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}; |
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static inline struct idma64 *to_idma64(struct dma_device *ddev) |
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{ |
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return container_of(ddev, struct idma64, dma); |
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} |
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static inline u32 idma64_readl(struct idma64 *idma64, int offset) |
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{ |
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return readl(idma64->regs + offset); |
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} |
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static inline void idma64_writel(struct idma64 *idma64, int offset, u32 value) |
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{ |
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writel(value, idma64->regs + offset); |
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} |
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#define dma_readl(idma64, reg) \ |
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idma64_readl(idma64, IDMA64_##reg) |
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#define dma_writel(idma64, reg, value) \ |
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idma64_writel(idma64, IDMA64_##reg, (value)) |
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/** |
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* struct idma64_chip - representation of iDMA 64-bit controller hardware |
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* @dev: struct device of the DMA controller |
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* @sysdev: struct device of the physical device that does DMA |
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* @irq: irq line |
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* @regs: memory mapped I/O space |
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* @idma64: struct idma64 that is filed by idma64_probe() |
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*/ |
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struct idma64_chip { |
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struct device *dev; |
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struct device *sysdev; |
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int irq; |
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void __iomem *regs; |
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struct idma64 *idma64; |
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}; |
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#endif /* __DMA_IDMA64_H__ */
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