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1323 lines
34 KiB
1323 lines
34 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Core driver for the Synopsys DesignWare DMA Controller |
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* |
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* Copyright (C) 2007-2008 Atmel Corporation |
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* Copyright (C) 2010-2011 ST Microelectronics |
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* Copyright (C) 2013 Intel Corporation |
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*/ |
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|
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#include <linux/bitops.h> |
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#include <linux/delay.h> |
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#include <linux/dmaengine.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/dmapool.h> |
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#include <linux/err.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/mm.h> |
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#include <linux/module.h> |
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#include <linux/slab.h> |
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#include <linux/pm_runtime.h> |
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|
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#include "../dmaengine.h" |
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#include "internal.h" |
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/* |
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* This supports the Synopsys "DesignWare AHB Central DMA Controller", |
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* (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all |
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* of which use ARM any more). See the "Databook" from Synopsys for |
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* information beyond what licensees probably provide. |
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* |
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* The driver has been tested with the Atmel AT32AP7000, which does not |
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* support descriptor writeback. |
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*/ |
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|
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/* The set of bus widths supported by the DMA controller */ |
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#define DW_DMA_BUSWIDTHS \ |
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BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ |
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BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ |
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ |
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
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/*----------------------------------------------------------------------*/ |
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|
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static struct device *chan2dev(struct dma_chan *chan) |
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{ |
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return &chan->dev->device; |
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} |
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static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) |
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{ |
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return to_dw_desc(dwc->active_list.next); |
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} |
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static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) |
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{ |
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struct dw_desc *desc = txd_to_dw_desc(tx); |
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struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); |
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dma_cookie_t cookie; |
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unsigned long flags; |
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spin_lock_irqsave(&dwc->lock, flags); |
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cookie = dma_cookie_assign(tx); |
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|
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/* |
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* REVISIT: We should attempt to chain as many descriptors as |
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* possible, perhaps even appending to those already submitted |
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* for DMA. But this is hard to do in a race-free manner. |
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*/ |
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|
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list_add_tail(&desc->desc_node, &dwc->queue); |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", |
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__func__, desc->txd.cookie); |
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|
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return cookie; |
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} |
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static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) |
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{ |
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struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
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struct dw_desc *desc; |
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dma_addr_t phys; |
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desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys); |
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if (!desc) |
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return NULL; |
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dwc->descs_allocated++; |
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INIT_LIST_HEAD(&desc->tx_list); |
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dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); |
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desc->txd.tx_submit = dwc_tx_submit; |
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desc->txd.flags = DMA_CTRL_ACK; |
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desc->txd.phys = phys; |
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return desc; |
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} |
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static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) |
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{ |
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struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
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struct dw_desc *child, *_next; |
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|
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if (unlikely(!desc)) |
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return; |
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list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) { |
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list_del(&child->desc_node); |
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dma_pool_free(dw->desc_pool, child, child->txd.phys); |
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dwc->descs_allocated--; |
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} |
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dma_pool_free(dw->desc_pool, desc, desc->txd.phys); |
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dwc->descs_allocated--; |
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} |
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static void dwc_initialize(struct dw_dma_chan *dwc) |
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{ |
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struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
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dw->initialize_chan(dwc); |
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|
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/* Enable interrupts */ |
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channel_set_bit(dw, MASK.XFER, dwc->mask); |
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channel_set_bit(dw, MASK.ERROR, dwc->mask); |
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} |
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|
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/*----------------------------------------------------------------------*/ |
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static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) |
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{ |
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dev_err(chan2dev(&dwc->chan), |
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" SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", |
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channel_readl(dwc, SAR), |
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channel_readl(dwc, DAR), |
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channel_readl(dwc, LLP), |
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channel_readl(dwc, CTL_HI), |
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channel_readl(dwc, CTL_LO)); |
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} |
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static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) |
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{ |
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channel_clear_bit(dw, CH_EN, dwc->mask); |
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while (dma_readl(dw, CH_EN) & dwc->mask) |
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cpu_relax(); |
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} |
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/*----------------------------------------------------------------------*/ |
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|
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/* Perform single block transfer */ |
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static inline void dwc_do_single_block(struct dw_dma_chan *dwc, |
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struct dw_desc *desc) |
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{ |
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struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
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u32 ctllo; |
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/* |
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* Software emulation of LLP mode relies on interrupts to continue |
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* multi block transfer. |
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*/ |
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ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN; |
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|
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channel_writel(dwc, SAR, lli_read(desc, sar)); |
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channel_writel(dwc, DAR, lli_read(desc, dar)); |
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channel_writel(dwc, CTL_LO, ctllo); |
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channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi)); |
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channel_set_bit(dw, CH_EN, dwc->mask); |
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|
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/* Move pointer to next descriptor */ |
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dwc->tx_node_active = dwc->tx_node_active->next; |
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} |
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/* Called with dwc->lock held and bh disabled */ |
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static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) |
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{ |
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struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
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u8 lms = DWC_LLP_LMS(dwc->dws.m_master); |
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unsigned long was_soft_llp; |
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/* ASSERT: channel is idle */ |
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if (dma_readl(dw, CH_EN) & dwc->mask) { |
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dev_err(chan2dev(&dwc->chan), |
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"%s: BUG: Attempted to start non-idle channel\n", |
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__func__); |
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dwc_dump_chan_regs(dwc); |
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/* The tasklet will hopefully advance the queue... */ |
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return; |
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} |
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if (dwc->nollp) { |
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was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, |
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&dwc->flags); |
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if (was_soft_llp) { |
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dev_err(chan2dev(&dwc->chan), |
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"BUG: Attempted to start new LLP transfer inside ongoing one\n"); |
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return; |
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} |
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dwc_initialize(dwc); |
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first->residue = first->total_len; |
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dwc->tx_node_active = &first->tx_list; |
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/* Submit first block */ |
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dwc_do_single_block(dwc, first); |
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return; |
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} |
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dwc_initialize(dwc); |
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channel_writel(dwc, LLP, first->txd.phys | lms); |
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channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
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channel_writel(dwc, CTL_HI, 0); |
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channel_set_bit(dw, CH_EN, dwc->mask); |
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} |
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static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) |
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{ |
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struct dw_desc *desc; |
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if (list_empty(&dwc->queue)) |
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return; |
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list_move(dwc->queue.next, &dwc->active_list); |
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desc = dwc_first_active(dwc); |
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dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); |
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dwc_dostart(dwc, desc); |
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} |
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/*----------------------------------------------------------------------*/ |
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static void |
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dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, |
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bool callback_required) |
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{ |
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struct dma_async_tx_descriptor *txd = &desc->txd; |
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struct dw_desc *child; |
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unsigned long flags; |
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struct dmaengine_desc_callback cb; |
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dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); |
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spin_lock_irqsave(&dwc->lock, flags); |
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dma_cookie_complete(txd); |
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if (callback_required) |
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dmaengine_desc_get_callback(txd, &cb); |
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else |
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memset(&cb, 0, sizeof(cb)); |
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/* async_tx_ack */ |
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list_for_each_entry(child, &desc->tx_list, desc_node) |
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async_tx_ack(&child->txd); |
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async_tx_ack(&desc->txd); |
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dwc_desc_put(dwc, desc); |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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dmaengine_desc_callback_invoke(&cb, NULL); |
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} |
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static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) |
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{ |
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struct dw_desc *desc, *_desc; |
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LIST_HEAD(list); |
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unsigned long flags; |
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spin_lock_irqsave(&dwc->lock, flags); |
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if (dma_readl(dw, CH_EN) & dwc->mask) { |
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dev_err(chan2dev(&dwc->chan), |
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"BUG: XFER bit set, but channel not idle!\n"); |
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/* Try to continue after resetting the channel... */ |
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dwc_chan_disable(dw, dwc); |
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} |
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/* |
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* Submit queued descriptors ASAP, i.e. before we go through |
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* the completed ones. |
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*/ |
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list_splice_init(&dwc->active_list, &list); |
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dwc_dostart_first_queued(dwc); |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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list_for_each_entry_safe(desc, _desc, &list, desc_node) |
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dwc_descriptor_complete(dwc, desc, true); |
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} |
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/* Returns how many bytes were already received from source */ |
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static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) |
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{ |
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struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
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u32 ctlhi = channel_readl(dwc, CTL_HI); |
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u32 ctllo = channel_readl(dwc, CTL_LO); |
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return dw->block2bytes(dwc, ctlhi, ctllo >> 4 & 7); |
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} |
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static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) |
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{ |
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dma_addr_t llp; |
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struct dw_desc *desc, *_desc; |
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struct dw_desc *child; |
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u32 status_xfer; |
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unsigned long flags; |
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spin_lock_irqsave(&dwc->lock, flags); |
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llp = channel_readl(dwc, LLP); |
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status_xfer = dma_readl(dw, RAW.XFER); |
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if (status_xfer & dwc->mask) { |
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/* Everything we've submitted is done */ |
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dma_writel(dw, CLEAR.XFER, dwc->mask); |
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if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
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struct list_head *head, *active = dwc->tx_node_active; |
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/* |
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* We are inside first active descriptor. |
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* Otherwise something is really wrong. |
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*/ |
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desc = dwc_first_active(dwc); |
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head = &desc->tx_list; |
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if (active != head) { |
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/* Update residue to reflect last sent descriptor */ |
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if (active == head->next) |
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desc->residue -= desc->len; |
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else |
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desc->residue -= to_dw_desc(active->prev)->len; |
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child = to_dw_desc(active); |
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/* Submit next block */ |
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dwc_do_single_block(dwc, child); |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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return; |
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} |
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/* We are done here */ |
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clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
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} |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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dwc_complete_all(dw, dwc); |
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return; |
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} |
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if (list_empty(&dwc->active_list)) { |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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return; |
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} |
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if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { |
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dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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return; |
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} |
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dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); |
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list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { |
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/* Initial residue value */ |
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desc->residue = desc->total_len; |
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|
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/* Check first descriptors addr */ |
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if (desc->txd.phys == DWC_LLP_LOC(llp)) { |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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return; |
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} |
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/* Check first descriptors llp */ |
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if (lli_read(desc, llp) == llp) { |
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/* This one is currently in progress */ |
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desc->residue -= dwc_get_sent(dwc); |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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return; |
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} |
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desc->residue -= desc->len; |
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list_for_each_entry(child, &desc->tx_list, desc_node) { |
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if (lli_read(child, llp) == llp) { |
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/* Currently in progress */ |
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desc->residue -= dwc_get_sent(dwc); |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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return; |
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} |
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desc->residue -= child->len; |
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} |
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/* |
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* No descriptors so far seem to be in progress, i.e. |
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* this one must be done. |
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*/ |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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dwc_descriptor_complete(dwc, desc, true); |
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spin_lock_irqsave(&dwc->lock, flags); |
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} |
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dev_err(chan2dev(&dwc->chan), |
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"BUG: All descriptors done, but channel not idle!\n"); |
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|
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/* Try to continue after resetting the channel... */ |
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dwc_chan_disable(dw, dwc); |
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|
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dwc_dostart_first_queued(dwc); |
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spin_unlock_irqrestore(&dwc->lock, flags); |
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} |
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static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc) |
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{ |
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dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", |
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lli_read(desc, sar), |
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lli_read(desc, dar), |
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lli_read(desc, llp), |
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lli_read(desc, ctlhi), |
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lli_read(desc, ctllo)); |
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} |
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static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) |
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{ |
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struct dw_desc *bad_desc; |
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struct dw_desc *child; |
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unsigned long flags; |
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|
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dwc_scan_descriptors(dw, dwc); |
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spin_lock_irqsave(&dwc->lock, flags); |
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|
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/* |
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* The descriptor currently at the head of the active list is |
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* borked. Since we don't have any way to report errors, we'll |
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* just have to scream loudly and try to carry on. |
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*/ |
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bad_desc = dwc_first_active(dwc); |
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list_del_init(&bad_desc->desc_node); |
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list_move(dwc->queue.next, dwc->active_list.prev); |
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|
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/* Clear the error flag and try to restart the controller */ |
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dma_writel(dw, CLEAR.ERROR, dwc->mask); |
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if (!list_empty(&dwc->active_list)) |
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dwc_dostart(dwc, dwc_first_active(dwc)); |
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|
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/* |
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* WARN may seem harsh, but since this only happens |
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* when someone submits a bad physical address in a |
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* descriptor, we should consider ourselves lucky that the |
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* controller flagged an error instead of scribbling over |
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* random memory locations. |
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*/ |
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dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" |
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" cookie: %d\n", bad_desc->txd.cookie); |
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dwc_dump_lli(dwc, bad_desc); |
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list_for_each_entry(child, &bad_desc->tx_list, desc_node) |
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dwc_dump_lli(dwc, child); |
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|
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spin_unlock_irqrestore(&dwc->lock, flags); |
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|
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/* Pretend the descriptor completed successfully */ |
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dwc_descriptor_complete(dwc, bad_desc, true); |
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} |
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|
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static void dw_dma_tasklet(struct tasklet_struct *t) |
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{ |
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struct dw_dma *dw = from_tasklet(dw, t, tasklet); |
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struct dw_dma_chan *dwc; |
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u32 status_xfer; |
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u32 status_err; |
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unsigned int i; |
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|
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status_xfer = dma_readl(dw, RAW.XFER); |
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status_err = dma_readl(dw, RAW.ERROR); |
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|
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dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); |
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|
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for (i = 0; i < dw->dma.chancnt; i++) { |
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dwc = &dw->chan[i]; |
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if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) |
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dev_vdbg(dw->dma.dev, "Cyclic xfer is not implemented\n"); |
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else if (status_err & (1 << i)) |
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dwc_handle_error(dw, dwc); |
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else if (status_xfer & (1 << i)) |
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dwc_scan_descriptors(dw, dwc); |
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} |
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|
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/* Re-enable interrupts */ |
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channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); |
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channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); |
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} |
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|
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static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) |
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{ |
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struct dw_dma *dw = dev_id; |
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u32 status; |
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|
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/* Check if we have any interrupt from the DMAC which is not in use */ |
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if (!dw->in_use) |
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return IRQ_NONE; |
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|
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status = dma_readl(dw, STATUS_INT); |
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dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); |
|
|
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/* Check if we have any interrupt from the DMAC */ |
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if (!status) |
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return IRQ_NONE; |
|
|
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/* |
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* Just disable the interrupts. We'll turn them back on in the |
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* softirq handler. |
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*/ |
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channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); |
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channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
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channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
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|
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status = dma_readl(dw, STATUS_INT); |
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if (status) { |
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dev_err(dw->dma.dev, |
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"BUG: Unexpected interrupts pending: 0x%x\n", |
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status); |
|
|
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/* Try to recover */ |
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channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); |
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channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); |
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channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); |
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channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); |
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channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); |
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} |
|
|
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tasklet_schedule(&dw->tasklet); |
|
|
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return IRQ_HANDLED; |
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} |
|
|
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/*----------------------------------------------------------------------*/ |
|
|
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static struct dma_async_tx_descriptor * |
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dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, |
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size_t len, unsigned long flags) |
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{ |
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
|
struct dw_dma *dw = to_dw_dma(chan->device); |
|
struct dw_desc *desc; |
|
struct dw_desc *first; |
|
struct dw_desc *prev; |
|
size_t xfer_count; |
|
size_t offset; |
|
u8 m_master = dwc->dws.m_master; |
|
unsigned int src_width; |
|
unsigned int dst_width; |
|
unsigned int data_width = dw->pdata->data_width[m_master]; |
|
u32 ctllo, ctlhi; |
|
u8 lms = DWC_LLP_LMS(m_master); |
|
|
|
dev_vdbg(chan2dev(chan), |
|
"%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, |
|
&dest, &src, len, flags); |
|
|
|
if (unlikely(!len)) { |
|
dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); |
|
return NULL; |
|
} |
|
|
|
dwc->direction = DMA_MEM_TO_MEM; |
|
|
|
src_width = dst_width = __ffs(data_width | src | dest | len); |
|
|
|
ctllo = dw->prepare_ctllo(dwc) |
|
| DWC_CTLL_DST_WIDTH(dst_width) |
|
| DWC_CTLL_SRC_WIDTH(src_width) |
|
| DWC_CTLL_DST_INC |
|
| DWC_CTLL_SRC_INC |
|
| DWC_CTLL_FC_M2M; |
|
prev = first = NULL; |
|
|
|
for (offset = 0; offset < len; offset += xfer_count) { |
|
desc = dwc_desc_get(dwc); |
|
if (!desc) |
|
goto err_desc_get; |
|
|
|
ctlhi = dw->bytes2block(dwc, len - offset, src_width, &xfer_count); |
|
|
|
lli_write(desc, sar, src + offset); |
|
lli_write(desc, dar, dest + offset); |
|
lli_write(desc, ctllo, ctllo); |
|
lli_write(desc, ctlhi, ctlhi); |
|
desc->len = xfer_count; |
|
|
|
if (!first) { |
|
first = desc; |
|
} else { |
|
lli_write(prev, llp, desc->txd.phys | lms); |
|
list_add_tail(&desc->desc_node, &first->tx_list); |
|
} |
|
prev = desc; |
|
} |
|
|
|
if (flags & DMA_PREP_INTERRUPT) |
|
/* Trigger interrupt after last block */ |
|
lli_set(prev, ctllo, DWC_CTLL_INT_EN); |
|
|
|
prev->lli.llp = 0; |
|
lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
|
first->txd.flags = flags; |
|
first->total_len = len; |
|
|
|
return &first->txd; |
|
|
|
err_desc_get: |
|
dwc_desc_put(dwc, first); |
|
return NULL; |
|
} |
|
|
|
static struct dma_async_tx_descriptor * |
|
dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, |
|
unsigned int sg_len, enum dma_transfer_direction direction, |
|
unsigned long flags, void *context) |
|
{ |
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
|
struct dw_dma *dw = to_dw_dma(chan->device); |
|
struct dma_slave_config *sconfig = &dwc->dma_sconfig; |
|
struct dw_desc *prev; |
|
struct dw_desc *first; |
|
u32 ctllo, ctlhi; |
|
u8 m_master = dwc->dws.m_master; |
|
u8 lms = DWC_LLP_LMS(m_master); |
|
dma_addr_t reg; |
|
unsigned int reg_width; |
|
unsigned int mem_width; |
|
unsigned int data_width = dw->pdata->data_width[m_master]; |
|
unsigned int i; |
|
struct scatterlist *sg; |
|
size_t total_len = 0; |
|
|
|
dev_vdbg(chan2dev(chan), "%s\n", __func__); |
|
|
|
if (unlikely(!is_slave_direction(direction) || !sg_len)) |
|
return NULL; |
|
|
|
dwc->direction = direction; |
|
|
|
prev = first = NULL; |
|
|
|
switch (direction) { |
|
case DMA_MEM_TO_DEV: |
|
reg_width = __ffs(sconfig->dst_addr_width); |
|
reg = sconfig->dst_addr; |
|
ctllo = dw->prepare_ctllo(dwc) |
|
| DWC_CTLL_DST_WIDTH(reg_width) |
|
| DWC_CTLL_DST_FIX |
|
| DWC_CTLL_SRC_INC; |
|
|
|
ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : |
|
DWC_CTLL_FC(DW_DMA_FC_D_M2P); |
|
|
|
for_each_sg(sgl, sg, sg_len, i) { |
|
struct dw_desc *desc; |
|
u32 len, mem; |
|
size_t dlen; |
|
|
|
mem = sg_dma_address(sg); |
|
len = sg_dma_len(sg); |
|
|
|
mem_width = __ffs(data_width | mem | len); |
|
|
|
slave_sg_todev_fill_desc: |
|
desc = dwc_desc_get(dwc); |
|
if (!desc) |
|
goto err_desc_get; |
|
|
|
ctlhi = dw->bytes2block(dwc, len, mem_width, &dlen); |
|
|
|
lli_write(desc, sar, mem); |
|
lli_write(desc, dar, reg); |
|
lli_write(desc, ctlhi, ctlhi); |
|
lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width)); |
|
desc->len = dlen; |
|
|
|
if (!first) { |
|
first = desc; |
|
} else { |
|
lli_write(prev, llp, desc->txd.phys | lms); |
|
list_add_tail(&desc->desc_node, &first->tx_list); |
|
} |
|
prev = desc; |
|
|
|
mem += dlen; |
|
len -= dlen; |
|
total_len += dlen; |
|
|
|
if (len) |
|
goto slave_sg_todev_fill_desc; |
|
} |
|
break; |
|
case DMA_DEV_TO_MEM: |
|
reg_width = __ffs(sconfig->src_addr_width); |
|
reg = sconfig->src_addr; |
|
ctllo = dw->prepare_ctllo(dwc) |
|
| DWC_CTLL_SRC_WIDTH(reg_width) |
|
| DWC_CTLL_DST_INC |
|
| DWC_CTLL_SRC_FIX; |
|
|
|
ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : |
|
DWC_CTLL_FC(DW_DMA_FC_D_P2M); |
|
|
|
for_each_sg(sgl, sg, sg_len, i) { |
|
struct dw_desc *desc; |
|
u32 len, mem; |
|
size_t dlen; |
|
|
|
mem = sg_dma_address(sg); |
|
len = sg_dma_len(sg); |
|
|
|
slave_sg_fromdev_fill_desc: |
|
desc = dwc_desc_get(dwc); |
|
if (!desc) |
|
goto err_desc_get; |
|
|
|
ctlhi = dw->bytes2block(dwc, len, reg_width, &dlen); |
|
|
|
lli_write(desc, sar, reg); |
|
lli_write(desc, dar, mem); |
|
lli_write(desc, ctlhi, ctlhi); |
|
mem_width = __ffs(data_width | mem); |
|
lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width)); |
|
desc->len = dlen; |
|
|
|
if (!first) { |
|
first = desc; |
|
} else { |
|
lli_write(prev, llp, desc->txd.phys | lms); |
|
list_add_tail(&desc->desc_node, &first->tx_list); |
|
} |
|
prev = desc; |
|
|
|
mem += dlen; |
|
len -= dlen; |
|
total_len += dlen; |
|
|
|
if (len) |
|
goto slave_sg_fromdev_fill_desc; |
|
} |
|
break; |
|
default: |
|
return NULL; |
|
} |
|
|
|
if (flags & DMA_PREP_INTERRUPT) |
|
/* Trigger interrupt after last block */ |
|
lli_set(prev, ctllo, DWC_CTLL_INT_EN); |
|
|
|
prev->lli.llp = 0; |
|
lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); |
|
first->total_len = total_len; |
|
|
|
return &first->txd; |
|
|
|
err_desc_get: |
|
dev_err(chan2dev(chan), |
|
"not enough descriptors available. Direction %d\n", direction); |
|
dwc_desc_put(dwc, first); |
|
return NULL; |
|
} |
|
|
|
bool dw_dma_filter(struct dma_chan *chan, void *param) |
|
{ |
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
|
struct dw_dma_slave *dws = param; |
|
|
|
if (dws->dma_dev != chan->device->dev) |
|
return false; |
|
|
|
/* permit channels in accordance with the channels mask */ |
|
if (dws->channels && !(dws->channels & dwc->mask)) |
|
return false; |
|
|
|
/* We have to copy data since dws can be temporary storage */ |
|
memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave)); |
|
|
|
return true; |
|
} |
|
EXPORT_SYMBOL_GPL(dw_dma_filter); |
|
|
|
static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) |
|
{ |
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
|
struct dw_dma *dw = to_dw_dma(chan->device); |
|
|
|
memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); |
|
|
|
dwc->dma_sconfig.src_maxburst = |
|
clamp(dwc->dma_sconfig.src_maxburst, 0U, dwc->max_burst); |
|
dwc->dma_sconfig.dst_maxburst = |
|
clamp(dwc->dma_sconfig.dst_maxburst, 0U, dwc->max_burst); |
|
|
|
dw->encode_maxburst(dwc, &dwc->dma_sconfig.src_maxburst); |
|
dw->encode_maxburst(dwc, &dwc->dma_sconfig.dst_maxburst); |
|
|
|
return 0; |
|
} |
|
|
|
static void dwc_chan_pause(struct dw_dma_chan *dwc, bool drain) |
|
{ |
|
struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
|
unsigned int count = 20; /* timeout iterations */ |
|
|
|
dw->suspend_chan(dwc, drain); |
|
|
|
while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) |
|
udelay(2); |
|
|
|
set_bit(DW_DMA_IS_PAUSED, &dwc->flags); |
|
} |
|
|
|
static int dwc_pause(struct dma_chan *chan) |
|
{ |
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&dwc->lock, flags); |
|
dwc_chan_pause(dwc, false); |
|
spin_unlock_irqrestore(&dwc->lock, flags); |
|
|
|
return 0; |
|
} |
|
|
|
static inline void dwc_chan_resume(struct dw_dma_chan *dwc, bool drain) |
|
{ |
|
struct dw_dma *dw = to_dw_dma(dwc->chan.device); |
|
|
|
dw->resume_chan(dwc, drain); |
|
|
|
clear_bit(DW_DMA_IS_PAUSED, &dwc->flags); |
|
} |
|
|
|
static int dwc_resume(struct dma_chan *chan) |
|
{ |
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&dwc->lock, flags); |
|
|
|
if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags)) |
|
dwc_chan_resume(dwc, false); |
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags); |
|
|
|
return 0; |
|
} |
|
|
|
static int dwc_terminate_all(struct dma_chan *chan) |
|
{ |
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
|
struct dw_dma *dw = to_dw_dma(chan->device); |
|
struct dw_desc *desc, *_desc; |
|
unsigned long flags; |
|
LIST_HEAD(list); |
|
|
|
spin_lock_irqsave(&dwc->lock, flags); |
|
|
|
clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); |
|
|
|
dwc_chan_pause(dwc, true); |
|
|
|
dwc_chan_disable(dw, dwc); |
|
|
|
dwc_chan_resume(dwc, true); |
|
|
|
/* active_list entries will end up before queued entries */ |
|
list_splice_init(&dwc->queue, &list); |
|
list_splice_init(&dwc->active_list, &list); |
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags); |
|
|
|
/* Flush all pending and queued descriptors */ |
|
list_for_each_entry_safe(desc, _desc, &list, desc_node) |
|
dwc_descriptor_complete(dwc, desc, false); |
|
|
|
return 0; |
|
} |
|
|
|
static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c) |
|
{ |
|
struct dw_desc *desc; |
|
|
|
list_for_each_entry(desc, &dwc->active_list, desc_node) |
|
if (desc->txd.cookie == c) |
|
return desc; |
|
|
|
return NULL; |
|
} |
|
|
|
static u32 dwc_get_residue(struct dw_dma_chan *dwc, dma_cookie_t cookie) |
|
{ |
|
struct dw_desc *desc; |
|
unsigned long flags; |
|
u32 residue; |
|
|
|
spin_lock_irqsave(&dwc->lock, flags); |
|
|
|
desc = dwc_find_desc(dwc, cookie); |
|
if (desc) { |
|
if (desc == dwc_first_active(dwc)) { |
|
residue = desc->residue; |
|
if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) |
|
residue -= dwc_get_sent(dwc); |
|
} else { |
|
residue = desc->total_len; |
|
} |
|
} else { |
|
residue = 0; |
|
} |
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags); |
|
return residue; |
|
} |
|
|
|
static enum dma_status |
|
dwc_tx_status(struct dma_chan *chan, |
|
dma_cookie_t cookie, |
|
struct dma_tx_state *txstate) |
|
{ |
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
|
enum dma_status ret; |
|
|
|
ret = dma_cookie_status(chan, cookie, txstate); |
|
if (ret == DMA_COMPLETE) |
|
return ret; |
|
|
|
dwc_scan_descriptors(to_dw_dma(chan->device), dwc); |
|
|
|
ret = dma_cookie_status(chan, cookie, txstate); |
|
if (ret == DMA_COMPLETE) |
|
return ret; |
|
|
|
dma_set_residue(txstate, dwc_get_residue(dwc, cookie)); |
|
|
|
if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS) |
|
return DMA_PAUSED; |
|
|
|
return ret; |
|
} |
|
|
|
static void dwc_issue_pending(struct dma_chan *chan) |
|
{ |
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&dwc->lock, flags); |
|
if (list_empty(&dwc->active_list)) |
|
dwc_dostart_first_queued(dwc); |
|
spin_unlock_irqrestore(&dwc->lock, flags); |
|
} |
|
|
|
/*----------------------------------------------------------------------*/ |
|
|
|
void do_dw_dma_off(struct dw_dma *dw) |
|
{ |
|
dma_writel(dw, CFG, 0); |
|
|
|
channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); |
|
channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); |
|
channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); |
|
channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); |
|
channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); |
|
|
|
while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) |
|
cpu_relax(); |
|
} |
|
|
|
void do_dw_dma_on(struct dw_dma *dw) |
|
{ |
|
dma_writel(dw, CFG, DW_CFG_DMA_EN); |
|
} |
|
|
|
static int dwc_alloc_chan_resources(struct dma_chan *chan) |
|
{ |
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
|
struct dw_dma *dw = to_dw_dma(chan->device); |
|
|
|
dev_vdbg(chan2dev(chan), "%s\n", __func__); |
|
|
|
/* ASSERT: channel is idle */ |
|
if (dma_readl(dw, CH_EN) & dwc->mask) { |
|
dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); |
|
return -EIO; |
|
} |
|
|
|
dma_cookie_init(chan); |
|
|
|
/* |
|
* NOTE: some controllers may have additional features that we |
|
* need to initialize here, like "scatter-gather" (which |
|
* doesn't mean what you think it means), and status writeback. |
|
*/ |
|
|
|
/* |
|
* We need controller-specific data to set up slave transfers. |
|
*/ |
|
if (chan->private && !dw_dma_filter(chan, chan->private)) { |
|
dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); |
|
return -EINVAL; |
|
} |
|
|
|
/* Enable controller here if needed */ |
|
if (!dw->in_use) |
|
do_dw_dma_on(dw); |
|
dw->in_use |= dwc->mask; |
|
|
|
return 0; |
|
} |
|
|
|
static void dwc_free_chan_resources(struct dma_chan *chan) |
|
{ |
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
|
struct dw_dma *dw = to_dw_dma(chan->device); |
|
unsigned long flags; |
|
|
|
dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, |
|
dwc->descs_allocated); |
|
|
|
/* ASSERT: channel is idle */ |
|
BUG_ON(!list_empty(&dwc->active_list)); |
|
BUG_ON(!list_empty(&dwc->queue)); |
|
BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); |
|
|
|
spin_lock_irqsave(&dwc->lock, flags); |
|
|
|
/* Clear custom channel configuration */ |
|
memset(&dwc->dws, 0, sizeof(struct dw_dma_slave)); |
|
|
|
/* Disable interrupts */ |
|
channel_clear_bit(dw, MASK.XFER, dwc->mask); |
|
channel_clear_bit(dw, MASK.BLOCK, dwc->mask); |
|
channel_clear_bit(dw, MASK.ERROR, dwc->mask); |
|
|
|
spin_unlock_irqrestore(&dwc->lock, flags); |
|
|
|
/* Disable controller in case it was a last user */ |
|
dw->in_use &= ~dwc->mask; |
|
if (!dw->in_use) |
|
do_dw_dma_off(dw); |
|
|
|
dev_vdbg(chan2dev(chan), "%s: done\n", __func__); |
|
} |
|
|
|
static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps) |
|
{ |
|
struct dw_dma_chan *dwc = to_dw_dma_chan(chan); |
|
|
|
caps->max_burst = dwc->max_burst; |
|
|
|
/* |
|
* It might be crucial for some devices to have the hardware |
|
* accelerated multi-block transfers supported, aka LLPs in DW DMAC |
|
* notation. So if LLPs are supported then max_sg_burst is set to |
|
* zero which means unlimited number of SG entries can be handled in a |
|
* single DMA transaction, otherwise it's just one SG entry. |
|
*/ |
|
if (dwc->nollp) |
|
caps->max_sg_burst = 1; |
|
else |
|
caps->max_sg_burst = 0; |
|
} |
|
|
|
int do_dma_probe(struct dw_dma_chip *chip) |
|
{ |
|
struct dw_dma *dw = chip->dw; |
|
struct dw_dma_platform_data *pdata; |
|
bool autocfg = false; |
|
unsigned int dw_params; |
|
unsigned int i; |
|
int err; |
|
|
|
dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL); |
|
if (!dw->pdata) |
|
return -ENOMEM; |
|
|
|
dw->regs = chip->regs; |
|
|
|
pm_runtime_get_sync(chip->dev); |
|
|
|
if (!chip->pdata) { |
|
dw_params = dma_readl(dw, DW_PARAMS); |
|
dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); |
|
|
|
autocfg = dw_params >> DW_PARAMS_EN & 1; |
|
if (!autocfg) { |
|
err = -EINVAL; |
|
goto err_pdata; |
|
} |
|
|
|
/* Reassign the platform data pointer */ |
|
pdata = dw->pdata; |
|
|
|
/* Get hardware configuration parameters */ |
|
pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; |
|
pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; |
|
for (i = 0; i < pdata->nr_masters; i++) { |
|
pdata->data_width[i] = |
|
4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3); |
|
} |
|
pdata->block_size = dma_readl(dw, MAX_BLK_SIZE); |
|
|
|
/* Fill platform data with the default values */ |
|
pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; |
|
pdata->chan_priority = CHAN_PRIORITY_ASCENDING; |
|
} else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { |
|
err = -EINVAL; |
|
goto err_pdata; |
|
} else { |
|
memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata)); |
|
|
|
/* Reassign the platform data pointer */ |
|
pdata = dw->pdata; |
|
} |
|
|
|
dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), |
|
GFP_KERNEL); |
|
if (!dw->chan) { |
|
err = -ENOMEM; |
|
goto err_pdata; |
|
} |
|
|
|
/* Calculate all channel mask before DMA setup */ |
|
dw->all_chan_mask = (1 << pdata->nr_channels) - 1; |
|
|
|
/* Force dma off, just in case */ |
|
dw->disable(dw); |
|
|
|
/* Device and instance ID for IRQ and DMA pool */ |
|
dw->set_device_name(dw, chip->id); |
|
|
|
/* Create a pool of consistent memory blocks for hardware descriptors */ |
|
dw->desc_pool = dmam_pool_create(dw->name, chip->dev, |
|
sizeof(struct dw_desc), 4, 0); |
|
if (!dw->desc_pool) { |
|
dev_err(chip->dev, "No memory for descriptors dma pool\n"); |
|
err = -ENOMEM; |
|
goto err_pdata; |
|
} |
|
|
|
tasklet_setup(&dw->tasklet, dw_dma_tasklet); |
|
|
|
err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, |
|
dw->name, dw); |
|
if (err) |
|
goto err_pdata; |
|
|
|
INIT_LIST_HEAD(&dw->dma.channels); |
|
for (i = 0; i < pdata->nr_channels; i++) { |
|
struct dw_dma_chan *dwc = &dw->chan[i]; |
|
|
|
dwc->chan.device = &dw->dma; |
|
dma_cookie_init(&dwc->chan); |
|
if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) |
|
list_add_tail(&dwc->chan.device_node, |
|
&dw->dma.channels); |
|
else |
|
list_add(&dwc->chan.device_node, &dw->dma.channels); |
|
|
|
/* 7 is highest priority & 0 is lowest. */ |
|
if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) |
|
dwc->priority = pdata->nr_channels - i - 1; |
|
else |
|
dwc->priority = i; |
|
|
|
dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; |
|
spin_lock_init(&dwc->lock); |
|
dwc->mask = 1 << i; |
|
|
|
INIT_LIST_HEAD(&dwc->active_list); |
|
INIT_LIST_HEAD(&dwc->queue); |
|
|
|
channel_clear_bit(dw, CH_EN, dwc->mask); |
|
|
|
dwc->direction = DMA_TRANS_NONE; |
|
|
|
/* Hardware configuration */ |
|
if (autocfg) { |
|
unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; |
|
void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r]; |
|
unsigned int dwc_params = readl(addr); |
|
|
|
dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, |
|
dwc_params); |
|
|
|
/* |
|
* Decode maximum block size for given channel. The |
|
* stored 4 bit value represents blocks from 0x00 for 3 |
|
* up to 0x0a for 4095. |
|
*/ |
|
dwc->block_size = |
|
(4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1; |
|
|
|
/* |
|
* According to the DW DMA databook the true scatter- |
|
* gether LLPs aren't available if either multi-block |
|
* config is disabled (CHx_MULTI_BLK_EN == 0) or the |
|
* LLP register is hard-coded to zeros |
|
* (CHx_HC_LLP == 1). |
|
*/ |
|
dwc->nollp = |
|
(dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0 || |
|
(dwc_params >> DWC_PARAMS_HC_LLP & 0x1) == 1; |
|
dwc->max_burst = |
|
(0x4 << (dwc_params >> DWC_PARAMS_MSIZE & 0x7)); |
|
} else { |
|
dwc->block_size = pdata->block_size; |
|
dwc->nollp = !pdata->multi_block[i]; |
|
dwc->max_burst = pdata->max_burst[i] ?: DW_DMA_MAX_BURST; |
|
} |
|
} |
|
|
|
/* Clear all interrupts on all channels. */ |
|
dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); |
|
dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); |
|
dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); |
|
dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); |
|
dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); |
|
|
|
/* Set capabilities */ |
|
dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); |
|
dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); |
|
dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); |
|
|
|
dw->dma.dev = chip->dev; |
|
dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; |
|
dw->dma.device_free_chan_resources = dwc_free_chan_resources; |
|
|
|
dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; |
|
dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; |
|
|
|
dw->dma.device_caps = dwc_caps; |
|
dw->dma.device_config = dwc_config; |
|
dw->dma.device_pause = dwc_pause; |
|
dw->dma.device_resume = dwc_resume; |
|
dw->dma.device_terminate_all = dwc_terminate_all; |
|
|
|
dw->dma.device_tx_status = dwc_tx_status; |
|
dw->dma.device_issue_pending = dwc_issue_pending; |
|
|
|
/* DMA capabilities */ |
|
dw->dma.min_burst = DW_DMA_MIN_BURST; |
|
dw->dma.max_burst = DW_DMA_MAX_BURST; |
|
dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; |
|
dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; |
|
dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | |
|
BIT(DMA_MEM_TO_MEM); |
|
dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
|
|
|
/* |
|
* For now there is no hardware with non uniform maximum block size |
|
* across all of the device channels, so we set the maximum segment |
|
* size as the block size found for the very first channel. |
|
*/ |
|
dma_set_max_seg_size(dw->dma.dev, dw->chan[0].block_size); |
|
|
|
err = dma_async_device_register(&dw->dma); |
|
if (err) |
|
goto err_dma_register; |
|
|
|
dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", |
|
pdata->nr_channels); |
|
|
|
pm_runtime_put_sync_suspend(chip->dev); |
|
|
|
return 0; |
|
|
|
err_dma_register: |
|
free_irq(chip->irq, dw); |
|
err_pdata: |
|
pm_runtime_put_sync_suspend(chip->dev); |
|
return err; |
|
} |
|
|
|
int do_dma_remove(struct dw_dma_chip *chip) |
|
{ |
|
struct dw_dma *dw = chip->dw; |
|
struct dw_dma_chan *dwc, *_dwc; |
|
|
|
pm_runtime_get_sync(chip->dev); |
|
|
|
do_dw_dma_off(dw); |
|
dma_async_device_unregister(&dw->dma); |
|
|
|
free_irq(chip->irq, dw); |
|
tasklet_kill(&dw->tasklet); |
|
|
|
list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, |
|
chan.device_node) { |
|
list_del(&dwc->chan.device_node); |
|
channel_clear_bit(dw, CH_EN, dwc->mask); |
|
} |
|
|
|
pm_runtime_put_sync_suspend(chip->dev); |
|
return 0; |
|
} |
|
|
|
int do_dw_dma_disable(struct dw_dma_chip *chip) |
|
{ |
|
struct dw_dma *dw = chip->dw; |
|
|
|
dw->disable(dw); |
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(do_dw_dma_disable); |
|
|
|
int do_dw_dma_enable(struct dw_dma_chip *chip) |
|
{ |
|
struct dw_dma *dw = chip->dw; |
|
|
|
dw->enable(dw); |
|
return 0; |
|
} |
|
EXPORT_SYMBOL_GPL(do_dw_dma_enable); |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); |
|
MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); |
|
MODULE_AUTHOR("Viresh Kumar <[email protected]>");
|
|
|