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438 lines
10 KiB
438 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* Copyright(c) 2021 Intel Corporation. All rights reserved. */ |
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#include <linux/platform_device.h> |
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#include <linux/module.h> |
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#include <linux/device.h> |
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#include <linux/kernel.h> |
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#include <linux/acpi.h> |
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#include <linux/pci.h> |
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#include "cxl.h" |
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static struct acpi_table_header *acpi_cedt; |
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/* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */ |
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#define CFMWS_INTERLEAVE_WAYS(x) (1 << (x)->interleave_ways) |
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#define CFMWS_INTERLEAVE_GRANULARITY(x) ((x)->granularity + 8) |
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static unsigned long cfmws_to_decoder_flags(int restrictions) |
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{ |
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unsigned long flags = 0; |
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE2) |
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flags |= CXL_DECODER_F_TYPE2; |
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_TYPE3) |
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flags |= CXL_DECODER_F_TYPE3; |
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_VOLATILE) |
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flags |= CXL_DECODER_F_RAM; |
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_PMEM) |
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flags |= CXL_DECODER_F_PMEM; |
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if (restrictions & ACPI_CEDT_CFMWS_RESTRICT_FIXED) |
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flags |= CXL_DECODER_F_LOCK; |
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return flags; |
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} |
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static int cxl_acpi_cfmws_verify(struct device *dev, |
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struct acpi_cedt_cfmws *cfmws) |
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{ |
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int expected_len; |
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if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) { |
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dev_err(dev, "CFMWS Unsupported Interleave Arithmetic\n"); |
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return -EINVAL; |
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} |
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if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) { |
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dev_err(dev, "CFMWS Base HPA not 256MB aligned\n"); |
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return -EINVAL; |
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} |
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if (!IS_ALIGNED(cfmws->window_size, SZ_256M)) { |
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dev_err(dev, "CFMWS Window Size not 256MB aligned\n"); |
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return -EINVAL; |
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} |
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expected_len = struct_size((cfmws), interleave_targets, |
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CFMWS_INTERLEAVE_WAYS(cfmws)); |
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if (cfmws->header.length < expected_len) { |
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dev_err(dev, "CFMWS length %d less than expected %d\n", |
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cfmws->header.length, expected_len); |
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return -EINVAL; |
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} |
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if (cfmws->header.length > expected_len) |
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dev_dbg(dev, "CFMWS length %d greater than expected %d\n", |
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cfmws->header.length, expected_len); |
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return 0; |
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} |
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static void cxl_add_cfmws_decoders(struct device *dev, |
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struct cxl_port *root_port) |
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{ |
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struct acpi_cedt_cfmws *cfmws; |
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struct cxl_decoder *cxld; |
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acpi_size len, cur = 0; |
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void *cedt_subtable; |
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unsigned long flags; |
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int rc; |
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len = acpi_cedt->length - sizeof(*acpi_cedt); |
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cedt_subtable = acpi_cedt + 1; |
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while (cur < len) { |
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struct acpi_cedt_header *c = cedt_subtable + cur; |
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if (c->type != ACPI_CEDT_TYPE_CFMWS) { |
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cur += c->length; |
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continue; |
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} |
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cfmws = cedt_subtable + cur; |
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if (cfmws->header.length < sizeof(*cfmws)) { |
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dev_warn_once(dev, |
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"CFMWS entry skipped:invalid length:%u\n", |
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cfmws->header.length); |
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cur += c->length; |
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continue; |
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} |
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rc = cxl_acpi_cfmws_verify(dev, cfmws); |
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if (rc) { |
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dev_err(dev, "CFMWS range %#llx-%#llx not registered\n", |
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cfmws->base_hpa, cfmws->base_hpa + |
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cfmws->window_size - 1); |
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cur += c->length; |
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continue; |
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} |
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flags = cfmws_to_decoder_flags(cfmws->restrictions); |
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cxld = devm_cxl_add_decoder(dev, root_port, |
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CFMWS_INTERLEAVE_WAYS(cfmws), |
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cfmws->base_hpa, cfmws->window_size, |
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CFMWS_INTERLEAVE_WAYS(cfmws), |
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CFMWS_INTERLEAVE_GRANULARITY(cfmws), |
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CXL_DECODER_EXPANDER, |
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flags); |
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if (IS_ERR(cxld)) { |
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dev_err(dev, "Failed to add decoder for %#llx-%#llx\n", |
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cfmws->base_hpa, cfmws->base_hpa + |
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cfmws->window_size - 1); |
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} else { |
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dev_dbg(dev, "add: %s range %#llx-%#llx\n", |
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dev_name(&cxld->dev), cfmws->base_hpa, |
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cfmws->base_hpa + cfmws->window_size - 1); |
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} |
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cur += c->length; |
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} |
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} |
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static struct acpi_cedt_chbs *cxl_acpi_match_chbs(struct device *dev, u32 uid) |
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{ |
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struct acpi_cedt_chbs *chbs, *chbs_match = NULL; |
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acpi_size len, cur = 0; |
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void *cedt_subtable; |
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len = acpi_cedt->length - sizeof(*acpi_cedt); |
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cedt_subtable = acpi_cedt + 1; |
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while (cur < len) { |
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struct acpi_cedt_header *c = cedt_subtable + cur; |
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if (c->type != ACPI_CEDT_TYPE_CHBS) { |
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cur += c->length; |
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continue; |
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} |
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chbs = cedt_subtable + cur; |
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if (chbs->header.length < sizeof(*chbs)) { |
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dev_warn_once(dev, |
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"CHBS entry skipped: invalid length:%u\n", |
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chbs->header.length); |
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cur += c->length; |
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continue; |
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} |
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if (chbs->uid != uid) { |
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cur += c->length; |
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continue; |
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} |
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if (chbs_match) { |
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dev_warn_once(dev, |
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"CHBS entry skipped: duplicate UID:%u\n", |
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uid); |
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cur += c->length; |
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continue; |
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} |
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chbs_match = chbs; |
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cur += c->length; |
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} |
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return chbs_match ? chbs_match : ERR_PTR(-ENODEV); |
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} |
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static resource_size_t get_chbcr(struct acpi_cedt_chbs *chbs) |
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{ |
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return IS_ERR(chbs) ? CXL_RESOURCE_NONE : chbs->base; |
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} |
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struct cxl_walk_context { |
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struct device *dev; |
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struct pci_bus *root; |
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struct cxl_port *port; |
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int error; |
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int count; |
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}; |
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static int match_add_root_ports(struct pci_dev *pdev, void *data) |
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{ |
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struct cxl_walk_context *ctx = data; |
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struct pci_bus *root_bus = ctx->root; |
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struct cxl_port *port = ctx->port; |
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int type = pci_pcie_type(pdev); |
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struct device *dev = ctx->dev; |
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u32 lnkcap, port_num; |
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int rc; |
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if (pdev->bus != root_bus) |
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return 0; |
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if (!pci_is_pcie(pdev)) |
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return 0; |
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if (type != PCI_EXP_TYPE_ROOT_PORT) |
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return 0; |
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if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP, |
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&lnkcap) != PCIBIOS_SUCCESSFUL) |
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return 0; |
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/* TODO walk DVSEC to find component register base */ |
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port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap); |
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rc = cxl_add_dport(port, &pdev->dev, port_num, CXL_RESOURCE_NONE); |
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if (rc) { |
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ctx->error = rc; |
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return rc; |
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} |
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ctx->count++; |
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dev_dbg(dev, "add dport%d: %s\n", port_num, dev_name(&pdev->dev)); |
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return 0; |
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} |
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static struct cxl_dport *find_dport_by_dev(struct cxl_port *port, struct device *dev) |
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{ |
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struct cxl_dport *dport; |
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device_lock(&port->dev); |
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list_for_each_entry(dport, &port->dports, list) |
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if (dport->dport == dev) { |
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device_unlock(&port->dev); |
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return dport; |
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} |
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device_unlock(&port->dev); |
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return NULL; |
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} |
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static struct acpi_device *to_cxl_host_bridge(struct device *dev) |
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{ |
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struct acpi_device *adev = to_acpi_device(dev); |
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if (!acpi_pci_find_root(adev->handle)) |
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return NULL; |
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if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0) |
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return adev; |
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return NULL; |
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} |
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/* |
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* A host bridge is a dport to a CFMWS decode and it is a uport to the |
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* dport (PCIe Root Ports) in the host bridge. |
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*/ |
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static int add_host_bridge_uport(struct device *match, void *arg) |
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{ |
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struct acpi_device *bridge = to_cxl_host_bridge(match); |
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struct cxl_port *root_port = arg; |
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struct device *host = root_port->dev.parent; |
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struct acpi_pci_root *pci_root; |
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struct cxl_walk_context ctx; |
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struct cxl_decoder *cxld; |
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struct cxl_dport *dport; |
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struct cxl_port *port; |
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if (!bridge) |
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return 0; |
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dport = find_dport_by_dev(root_port, match); |
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if (!dport) { |
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dev_dbg(host, "host bridge expected and not found\n"); |
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return -ENODEV; |
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} |
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port = devm_cxl_add_port(host, match, dport->component_reg_phys, |
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root_port); |
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if (IS_ERR(port)) |
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return PTR_ERR(port); |
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dev_dbg(host, "%s: add: %s\n", dev_name(match), dev_name(&port->dev)); |
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/* |
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* Note that this lookup already succeeded in |
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* to_cxl_host_bridge(), so no need to check for failure here |
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*/ |
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pci_root = acpi_pci_find_root(bridge->handle); |
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ctx = (struct cxl_walk_context){ |
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.dev = host, |
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.root = pci_root->bus, |
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.port = port, |
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}; |
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pci_walk_bus(pci_root->bus, match_add_root_ports, &ctx); |
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if (ctx.count == 0) |
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return -ENODEV; |
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if (ctx.error) |
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return ctx.error; |
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/* TODO: Scan CHBCR for HDM Decoder resources */ |
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/* |
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* In the single-port host-bridge case there are no HDM decoders |
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* in the CHBCR and a 1:1 passthrough decode is implied. |
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*/ |
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if (ctx.count == 1) { |
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cxld = devm_cxl_add_passthrough_decoder(host, port); |
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if (IS_ERR(cxld)) |
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return PTR_ERR(cxld); |
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dev_dbg(host, "add: %s\n", dev_name(&cxld->dev)); |
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} |
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return 0; |
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} |
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static int add_host_bridge_dport(struct device *match, void *arg) |
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{ |
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int rc; |
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acpi_status status; |
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unsigned long long uid; |
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struct acpi_cedt_chbs *chbs; |
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struct cxl_port *root_port = arg; |
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struct device *host = root_port->dev.parent; |
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struct acpi_device *bridge = to_cxl_host_bridge(match); |
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if (!bridge) |
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return 0; |
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status = acpi_evaluate_integer(bridge->handle, METHOD_NAME__UID, NULL, |
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&uid); |
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if (status != AE_OK) { |
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dev_err(host, "unable to retrieve _UID of %s\n", |
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dev_name(match)); |
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return -ENODEV; |
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} |
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chbs = cxl_acpi_match_chbs(host, uid); |
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if (IS_ERR(chbs)) |
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dev_dbg(host, "No CHBS found for Host Bridge: %s\n", |
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dev_name(match)); |
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rc = cxl_add_dport(root_port, match, uid, get_chbcr(chbs)); |
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if (rc) { |
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dev_err(host, "failed to add downstream port: %s\n", |
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dev_name(match)); |
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return rc; |
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} |
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dev_dbg(host, "add dport%llu: %s\n", uid, dev_name(match)); |
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return 0; |
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} |
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static int add_root_nvdimm_bridge(struct device *match, void *data) |
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{ |
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struct cxl_decoder *cxld; |
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struct cxl_port *root_port = data; |
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struct cxl_nvdimm_bridge *cxl_nvb; |
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struct device *host = root_port->dev.parent; |
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if (!is_root_decoder(match)) |
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return 0; |
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cxld = to_cxl_decoder(match); |
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if (!(cxld->flags & CXL_DECODER_F_PMEM)) |
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return 0; |
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cxl_nvb = devm_cxl_add_nvdimm_bridge(host, root_port); |
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if (IS_ERR(cxl_nvb)) { |
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dev_dbg(host, "failed to register pmem\n"); |
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return PTR_ERR(cxl_nvb); |
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} |
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dev_dbg(host, "%s: add: %s\n", dev_name(&root_port->dev), |
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dev_name(&cxl_nvb->dev)); |
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return 1; |
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} |
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static int cxl_acpi_probe(struct platform_device *pdev) |
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{ |
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int rc; |
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acpi_status status; |
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struct cxl_port *root_port; |
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struct device *host = &pdev->dev; |
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struct acpi_device *adev = ACPI_COMPANION(host); |
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root_port = devm_cxl_add_port(host, host, CXL_RESOURCE_NONE, NULL); |
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if (IS_ERR(root_port)) |
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return PTR_ERR(root_port); |
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dev_dbg(host, "add: %s\n", dev_name(&root_port->dev)); |
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status = acpi_get_table(ACPI_SIG_CEDT, 0, &acpi_cedt); |
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if (ACPI_FAILURE(status)) |
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return -ENXIO; |
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rc = bus_for_each_dev(adev->dev.bus, NULL, root_port, |
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add_host_bridge_dport); |
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if (rc) |
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goto out; |
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cxl_add_cfmws_decoders(host, root_port); |
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/* |
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* Root level scanned with host-bridge as dports, now scan host-bridges |
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* for their role as CXL uports to their CXL-capable PCIe Root Ports. |
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*/ |
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rc = bus_for_each_dev(adev->dev.bus, NULL, root_port, |
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add_host_bridge_uport); |
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if (rc) |
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goto out; |
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if (IS_ENABLED(CONFIG_CXL_PMEM)) |
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rc = device_for_each_child(&root_port->dev, root_port, |
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add_root_nvdimm_bridge); |
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out: |
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acpi_put_table(acpi_cedt); |
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if (rc < 0) |
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return rc; |
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return 0; |
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} |
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static const struct acpi_device_id cxl_acpi_ids[] = { |
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{ "ACPI0017", 0 }, |
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{ "", 0 }, |
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}; |
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MODULE_DEVICE_TABLE(acpi, cxl_acpi_ids); |
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static struct platform_driver cxl_acpi_driver = { |
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.probe = cxl_acpi_probe, |
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.driver = { |
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.name = KBUILD_MODNAME, |
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.acpi_match_table = cxl_acpi_ids, |
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}, |
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}; |
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module_platform_driver(cxl_acpi_driver); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_IMPORT_NS(CXL);
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