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457 lines
16 KiB
457 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2007-2009 ST-Ericsson AB |
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* Timer COH 901 328, runs the OS timer interrupt. |
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* Author: Linus Walleij <[email protected]> |
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*/ |
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#include <linux/interrupt.h> |
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#include <linux/time.h> |
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#include <linux/timex.h> |
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#include <linux/clockchips.h> |
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#include <linux/clocksource.h> |
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#include <linux/types.h> |
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#include <linux/io.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/irq.h> |
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#include <linux/delay.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/sched_clock.h> |
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/* Generic stuff */ |
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#include <asm/mach/map.h> |
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#include <asm/mach/time.h> |
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/* |
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* APP side special timer registers |
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* This timer contains four timers which can fire an interrupt each. |
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* OS (operating system) timer @ 32768 Hz |
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* DD (device driver) timer @ 1 kHz |
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* GP1 (general purpose 1) timer @ 1MHz |
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* GP2 (general purpose 2) timer @ 1MHz |
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*/ |
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/* Reset OS Timer 32bit (-/W) */ |
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#define U300_TIMER_APP_ROST (0x0000) |
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#define U300_TIMER_APP_ROST_TIMER_RESET (0x00000000) |
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/* Enable OS Timer 32bit (-/W) */ |
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#define U300_TIMER_APP_EOST (0x0004) |
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#define U300_TIMER_APP_EOST_TIMER_ENABLE (0x00000000) |
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/* Disable OS Timer 32bit (-/W) */ |
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#define U300_TIMER_APP_DOST (0x0008) |
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#define U300_TIMER_APP_DOST_TIMER_DISABLE (0x00000000) |
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/* OS Timer Mode Register 32bit (-/W) */ |
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#define U300_TIMER_APP_SOSTM (0x000c) |
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#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS (0x00000000) |
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#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT (0x00000001) |
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/* OS Timer Status Register 32bit (R/-) */ |
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#define U300_TIMER_APP_OSTS (0x0010) |
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#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK (0x0000000F) |
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#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE (0x00000001) |
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#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE (0x00000002) |
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#define U300_TIMER_APP_OSTS_ENABLE_IND (0x00000010) |
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#define U300_TIMER_APP_OSTS_MODE_MASK (0x00000020) |
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#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS (0x00000000) |
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#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT (0x00000020) |
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#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND (0x00000040) |
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#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND (0x00000080) |
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/* OS Timer Current Count Register 32bit (R/-) */ |
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#define U300_TIMER_APP_OSTCC (0x0014) |
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/* OS Timer Terminal Count Register 32bit (R/W) */ |
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#define U300_TIMER_APP_OSTTC (0x0018) |
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/* OS Timer Interrupt Enable Register 32bit (-/W) */ |
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#define U300_TIMER_APP_OSTIE (0x001c) |
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#define U300_TIMER_APP_OSTIE_IRQ_DISABLE (0x00000000) |
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#define U300_TIMER_APP_OSTIE_IRQ_ENABLE (0x00000001) |
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/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */ |
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#define U300_TIMER_APP_OSTIA (0x0020) |
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#define U300_TIMER_APP_OSTIA_IRQ_ACK (0x00000080) |
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/* Reset DD Timer 32bit (-/W) */ |
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#define U300_TIMER_APP_RDDT (0x0040) |
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#define U300_TIMER_APP_RDDT_TIMER_RESET (0x00000000) |
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/* Enable DD Timer 32bit (-/W) */ |
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#define U300_TIMER_APP_EDDT (0x0044) |
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#define U300_TIMER_APP_EDDT_TIMER_ENABLE (0x00000000) |
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/* Disable DD Timer 32bit (-/W) */ |
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#define U300_TIMER_APP_DDDT (0x0048) |
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#define U300_TIMER_APP_DDDT_TIMER_DISABLE (0x00000000) |
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/* DD Timer Mode Register 32bit (-/W) */ |
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#define U300_TIMER_APP_SDDTM (0x004c) |
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#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS (0x00000000) |
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#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT (0x00000001) |
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/* DD Timer Status Register 32bit (R/-) */ |
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#define U300_TIMER_APP_DDTS (0x0050) |
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#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK (0x0000000F) |
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#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE (0x00000001) |
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#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE (0x00000002) |
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#define U300_TIMER_APP_DDTS_ENABLE_IND (0x00000010) |
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#define U300_TIMER_APP_DDTS_MODE_MASK (0x00000020) |
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#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS (0x00000000) |
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#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT (0x00000020) |
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#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND (0x00000040) |
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#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND (0x00000080) |
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/* DD Timer Current Count Register 32bit (R/-) */ |
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#define U300_TIMER_APP_DDTCC (0x0054) |
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/* DD Timer Terminal Count Register 32bit (R/W) */ |
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#define U300_TIMER_APP_DDTTC (0x0058) |
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/* DD Timer Interrupt Enable Register 32bit (-/W) */ |
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#define U300_TIMER_APP_DDTIE (0x005c) |
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#define U300_TIMER_APP_DDTIE_IRQ_DISABLE (0x00000000) |
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#define U300_TIMER_APP_DDTIE_IRQ_ENABLE (0x00000001) |
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/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */ |
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#define U300_TIMER_APP_DDTIA (0x0060) |
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#define U300_TIMER_APP_DDTIA_IRQ_ACK (0x00000080) |
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/* Reset GP1 Timer 32bit (-/W) */ |
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#define U300_TIMER_APP_RGPT1 (0x0080) |
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#define U300_TIMER_APP_RGPT1_TIMER_RESET (0x00000000) |
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/* Enable GP1 Timer 32bit (-/W) */ |
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#define U300_TIMER_APP_EGPT1 (0x0084) |
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#define U300_TIMER_APP_EGPT1_TIMER_ENABLE (0x00000000) |
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/* Disable GP1 Timer 32bit (-/W) */ |
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#define U300_TIMER_APP_DGPT1 (0x0088) |
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#define U300_TIMER_APP_DGPT1_TIMER_DISABLE (0x00000000) |
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/* GP1 Timer Mode Register 32bit (-/W) */ |
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#define U300_TIMER_APP_SGPT1M (0x008c) |
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#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS (0x00000000) |
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#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT (0x00000001) |
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/* GP1 Timer Status Register 32bit (R/-) */ |
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#define U300_TIMER_APP_GPT1S (0x0090) |
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#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK (0x0000000F) |
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#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE (0x00000001) |
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#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE (0x00000002) |
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#define U300_TIMER_APP_GPT1S_ENABLE_IND (0x00000010) |
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#define U300_TIMER_APP_GPT1S_MODE_MASK (0x00000020) |
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#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS (0x00000000) |
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#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT (0x00000020) |
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#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND (0x00000040) |
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#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND (0x00000080) |
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/* GP1 Timer Current Count Register 32bit (R/-) */ |
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#define U300_TIMER_APP_GPT1CC (0x0094) |
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/* GP1 Timer Terminal Count Register 32bit (R/W) */ |
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#define U300_TIMER_APP_GPT1TC (0x0098) |
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/* GP1 Timer Interrupt Enable Register 32bit (-/W) */ |
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#define U300_TIMER_APP_GPT1IE (0x009c) |
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#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE (0x00000000) |
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#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE (0x00000001) |
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/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */ |
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#define U300_TIMER_APP_GPT1IA (0x00a0) |
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#define U300_TIMER_APP_GPT1IA_IRQ_ACK (0x00000080) |
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/* Reset GP2 Timer 32bit (-/W) */ |
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#define U300_TIMER_APP_RGPT2 (0x00c0) |
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#define U300_TIMER_APP_RGPT2_TIMER_RESET (0x00000000) |
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/* Enable GP2 Timer 32bit (-/W) */ |
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#define U300_TIMER_APP_EGPT2 (0x00c4) |
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#define U300_TIMER_APP_EGPT2_TIMER_ENABLE (0x00000000) |
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/* Disable GP2 Timer 32bit (-/W) */ |
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#define U300_TIMER_APP_DGPT2 (0x00c8) |
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#define U300_TIMER_APP_DGPT2_TIMER_DISABLE (0x00000000) |
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/* GP2 Timer Mode Register 32bit (-/W) */ |
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#define U300_TIMER_APP_SGPT2M (0x00cc) |
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#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS (0x00000000) |
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#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT (0x00000001) |
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/* GP2 Timer Status Register 32bit (R/-) */ |
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#define U300_TIMER_APP_GPT2S (0x00d0) |
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#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK (0x0000000F) |
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#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE (0x00000001) |
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#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE (0x00000002) |
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#define U300_TIMER_APP_GPT2S_ENABLE_IND (0x00000010) |
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#define U300_TIMER_APP_GPT2S_MODE_MASK (0x00000020) |
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#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS (0x00000000) |
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#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT (0x00000020) |
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#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND (0x00000040) |
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#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND (0x00000080) |
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/* GP2 Timer Current Count Register 32bit (R/-) */ |
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#define U300_TIMER_APP_GPT2CC (0x00d4) |
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/* GP2 Timer Terminal Count Register 32bit (R/W) */ |
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#define U300_TIMER_APP_GPT2TC (0x00d8) |
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/* GP2 Timer Interrupt Enable Register 32bit (-/W) */ |
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#define U300_TIMER_APP_GPT2IE (0x00dc) |
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#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE (0x00000000) |
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#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE (0x00000001) |
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/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */ |
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#define U300_TIMER_APP_GPT2IA (0x00e0) |
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#define U300_TIMER_APP_GPT2IA_IRQ_ACK (0x00000080) |
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/* Clock request control register - all four timers */ |
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#define U300_TIMER_APP_CRC (0x100) |
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#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001) |
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static void __iomem *u300_timer_base; |
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struct u300_clockevent_data { |
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struct clock_event_device cevd; |
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unsigned ticks_per_jiffy; |
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}; |
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static int u300_shutdown(struct clock_event_device *evt) |
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{ |
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/* Disable interrupts on GP1 */ |
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writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, |
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u300_timer_base + U300_TIMER_APP_GPT1IE); |
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/* Disable GP1 */ |
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writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, |
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u300_timer_base + U300_TIMER_APP_DGPT1); |
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return 0; |
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} |
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/* |
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* If we have oneshot timer active, the oneshot scheduling function |
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* u300_set_next_event() is called immediately after. |
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*/ |
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static int u300_set_oneshot(struct clock_event_device *evt) |
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{ |
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/* Just return; here? */ |
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/* |
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* The actual event will be programmed by the next event hook, |
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* so we just set a dummy value somewhere at the end of the |
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* universe here. |
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*/ |
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/* Disable interrupts on GPT1 */ |
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writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, |
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u300_timer_base + U300_TIMER_APP_GPT1IE); |
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/* Disable GP1 while we're reprogramming it. */ |
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writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, |
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u300_timer_base + U300_TIMER_APP_DGPT1); |
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/* |
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* Expire far in the future, u300_set_next_event() will be |
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* called soon... |
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*/ |
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writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC); |
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/* We run one shot per tick here! */ |
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writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, |
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u300_timer_base + U300_TIMER_APP_SGPT1M); |
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/* Enable interrupts for this timer */ |
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writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, |
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u300_timer_base + U300_TIMER_APP_GPT1IE); |
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/* Enable timer */ |
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writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, |
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u300_timer_base + U300_TIMER_APP_EGPT1); |
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return 0; |
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} |
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static int u300_set_periodic(struct clock_event_device *evt) |
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{ |
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struct u300_clockevent_data *cevdata = |
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container_of(evt, struct u300_clockevent_data, cevd); |
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/* Disable interrupts on GPT1 */ |
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writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, |
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u300_timer_base + U300_TIMER_APP_GPT1IE); |
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/* Disable GP1 while we're reprogramming it. */ |
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writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, |
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u300_timer_base + U300_TIMER_APP_DGPT1); |
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/* |
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* Set the periodic mode to a certain number of ticks per |
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* jiffy. |
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*/ |
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writel(cevdata->ticks_per_jiffy, |
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u300_timer_base + U300_TIMER_APP_GPT1TC); |
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/* |
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* Set continuous mode, so the timer keeps triggering |
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* interrupts. |
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*/ |
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writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS, |
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u300_timer_base + U300_TIMER_APP_SGPT1M); |
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/* Enable timer interrupts */ |
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writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, |
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u300_timer_base + U300_TIMER_APP_GPT1IE); |
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/* Then enable the OS timer again */ |
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writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, |
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u300_timer_base + U300_TIMER_APP_EGPT1); |
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return 0; |
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} |
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/* |
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* The app timer in one shot mode obviously has to be reprogrammed |
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* in EXACTLY this sequence to work properly. Do NOT try to e.g. replace |
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* the interrupt disable + timer disable commands with a reset command, |
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* it will fail miserably. Apparently (and I found this the hard way) |
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* the timer is very sensitive to the instruction order, though you don't |
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* get that impression from the data sheet. |
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*/ |
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static int u300_set_next_event(unsigned long cycles, |
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struct clock_event_device *evt) |
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{ |
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/* Disable interrupts on GPT1 */ |
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writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, |
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u300_timer_base + U300_TIMER_APP_GPT1IE); |
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/* Disable GP1 while we're reprogramming it. */ |
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writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, |
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u300_timer_base + U300_TIMER_APP_DGPT1); |
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/* Reset the General Purpose timer 1. */ |
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writel(U300_TIMER_APP_RGPT1_TIMER_RESET, |
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u300_timer_base + U300_TIMER_APP_RGPT1); |
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/* IRQ in n * cycles */ |
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writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC); |
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/* |
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* We run one shot per tick here! (This is necessary to reconfigure, |
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* the timer will tilt if you don't!) |
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*/ |
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writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, |
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u300_timer_base + U300_TIMER_APP_SGPT1M); |
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/* Enable timer interrupts */ |
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writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, |
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u300_timer_base + U300_TIMER_APP_GPT1IE); |
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/* Then enable the OS timer again */ |
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writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, |
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u300_timer_base + U300_TIMER_APP_EGPT1); |
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return 0; |
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} |
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static struct u300_clockevent_data u300_clockevent_data = { |
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/* Use general purpose timer 1 as clock event */ |
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.cevd = { |
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.name = "GPT1", |
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/* Reasonably fast and accurate clock event */ |
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.rating = 300, |
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.features = CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_ONESHOT, |
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.set_next_event = u300_set_next_event, |
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.set_state_shutdown = u300_shutdown, |
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.set_state_periodic = u300_set_periodic, |
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.set_state_oneshot = u300_set_oneshot, |
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}, |
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}; |
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/* Clock event timer interrupt handler */ |
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static irqreturn_t u300_timer_interrupt(int irq, void *dev_id) |
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{ |
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struct clock_event_device *evt = &u300_clockevent_data.cevd; |
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/* ACK/Clear timer IRQ for the APP GPT1 Timer */ |
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writel(U300_TIMER_APP_GPT1IA_IRQ_ACK, |
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u300_timer_base + U300_TIMER_APP_GPT1IA); |
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evt->event_handler(evt); |
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return IRQ_HANDLED; |
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} |
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/* |
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* Override the global weak sched_clock symbol with this |
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* local implementation which uses the clocksource to get some |
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* better resolution when scheduling the kernel. We accept that |
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* this wraps around for now, since it is just a relative time |
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* stamp. (Inspired by OMAP implementation.) |
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*/ |
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static u64 notrace u300_read_sched_clock(void) |
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{ |
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return readl(u300_timer_base + U300_TIMER_APP_GPT2CC); |
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} |
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static unsigned long u300_read_current_timer(void) |
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{ |
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return readl(u300_timer_base + U300_TIMER_APP_GPT2CC); |
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} |
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static struct delay_timer u300_delay_timer; |
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/* |
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* This sets up the system timers, clock source and clock event. |
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*/ |
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static int __init u300_timer_init_of(struct device_node *np) |
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{ |
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unsigned int irq; |
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struct clk *clk; |
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unsigned long rate; |
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int ret; |
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u300_timer_base = of_iomap(np, 0); |
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if (!u300_timer_base) { |
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pr_err("could not ioremap system timer\n"); |
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return -ENXIO; |
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} |
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/* Get the IRQ for the GP1 timer */ |
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irq = irq_of_parse_and_map(np, 2); |
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if (!irq) { |
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pr_err("no IRQ for system timer\n"); |
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return -EINVAL; |
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} |
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pr_info("U300 GP1 timer @ base: %p, IRQ: %u\n", u300_timer_base, irq); |
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/* Clock the interrupt controller */ |
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clk = of_clk_get(np, 0); |
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if (IS_ERR(clk)) |
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return PTR_ERR(clk); |
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ret = clk_prepare_enable(clk); |
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if (ret) |
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return ret; |
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rate = clk_get_rate(clk); |
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u300_clockevent_data.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ); |
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sched_clock_register(u300_read_sched_clock, 32, rate); |
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u300_delay_timer.read_current_timer = &u300_read_current_timer; |
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u300_delay_timer.freq = rate; |
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register_current_timer_delay(&u300_delay_timer); |
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/* |
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* Disable the "OS" and "DD" timers - these are designed for Symbian! |
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* Example usage in cnh1601578 cpu subsystem pd_timer_app.c |
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*/ |
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writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE, |
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u300_timer_base + U300_TIMER_APP_CRC); |
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writel(U300_TIMER_APP_ROST_TIMER_RESET, |
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u300_timer_base + U300_TIMER_APP_ROST); |
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writel(U300_TIMER_APP_DOST_TIMER_DISABLE, |
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u300_timer_base + U300_TIMER_APP_DOST); |
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writel(U300_TIMER_APP_RDDT_TIMER_RESET, |
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u300_timer_base + U300_TIMER_APP_RDDT); |
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writel(U300_TIMER_APP_DDDT_TIMER_DISABLE, |
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u300_timer_base + U300_TIMER_APP_DDDT); |
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/* Reset the General Purpose timer 1. */ |
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writel(U300_TIMER_APP_RGPT1_TIMER_RESET, |
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u300_timer_base + U300_TIMER_APP_RGPT1); |
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|
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/* Set up the IRQ handler */ |
|
ret = request_irq(irq, u300_timer_interrupt, |
|
IRQF_TIMER | IRQF_IRQPOLL, "U300 Timer Tick", NULL); |
|
if (ret) |
|
return ret; |
|
|
|
/* Reset the General Purpose timer 2 */ |
|
writel(U300_TIMER_APP_RGPT2_TIMER_RESET, |
|
u300_timer_base + U300_TIMER_APP_RGPT2); |
|
/* Set this timer to run around forever */ |
|
writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC); |
|
/* Set continuous mode so it wraps around */ |
|
writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS, |
|
u300_timer_base + U300_TIMER_APP_SGPT2M); |
|
/* Disable timer interrupts */ |
|
writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE, |
|
u300_timer_base + U300_TIMER_APP_GPT2IE); |
|
/* Then enable the GP2 timer to use as a free running us counter */ |
|
writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, |
|
u300_timer_base + U300_TIMER_APP_EGPT2); |
|
|
|
/* Use general purpose timer 2 as clock source */ |
|
ret = clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC, |
|
"GPT2", rate, 300, 32, clocksource_mmio_readl_up); |
|
if (ret) { |
|
pr_err("timer: failed to initialize U300 clock source\n"); |
|
return ret; |
|
} |
|
|
|
/* Configure and register the clockevent */ |
|
clockevents_config_and_register(&u300_clockevent_data.cevd, rate, |
|
1, 0xffffffff); |
|
|
|
/* |
|
* TODO: init and register the rest of the timers too, they can be |
|
* used by hrtimers! |
|
*/ |
|
return 0; |
|
} |
|
|
|
TIMER_OF_DECLARE(u300_timer, "stericsson,u300-apptimer", |
|
u300_timer_init_of);
|
|
|