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971 lines
23 KiB
971 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0+ |
|
/* |
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* linux/arch/arm/plat-omap/dmtimer.c |
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* |
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* OMAP Dual-Mode Timers |
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* |
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* Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ |
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* Tarun Kanti DebBarma <[email protected]> |
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* Thara Gopinath <[email protected]> |
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* |
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* dmtimer adaptation to platform_driver. |
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* |
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* Copyright (C) 2005 Nokia Corporation |
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* OMAP2 support by Juha Yrjola |
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* API improvements and OMAP2 clock framework support by Timo Teras |
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* |
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* Copyright (C) 2009 Texas Instruments |
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* Added OMAP4 support - Santosh Shilimkar <[email protected]> |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/cpu_pm.h> |
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#include <linux/module.h> |
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#include <linux/io.h> |
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#include <linux/device.h> |
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#include <linux/err.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/platform_data/dmtimer-omap.h> |
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|
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#include <clocksource/timer-ti-dm.h> |
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|
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static u32 omap_reserved_systimers; |
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static LIST_HEAD(omap_timer_list); |
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static DEFINE_SPINLOCK(dm_timer_lock); |
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|
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enum { |
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REQUEST_ANY = 0, |
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REQUEST_BY_ID, |
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REQUEST_BY_CAP, |
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REQUEST_BY_NODE, |
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}; |
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|
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/** |
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* omap_dm_timer_read_reg - read timer registers in posted and non-posted mode |
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* @timer: timer pointer over which read operation to perform |
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* @reg: lowest byte holds the register offset |
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* |
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* The posted mode bit is encoded in reg. Note that in posted mode write |
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* pending bit must be checked. Otherwise a read of a non completed write |
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* will produce an error. |
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*/ |
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static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) |
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{ |
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WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
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return __omap_dm_timer_read(timer, reg, timer->posted); |
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} |
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|
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/** |
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* omap_dm_timer_write_reg - write timer registers in posted and non-posted mode |
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* @timer: timer pointer over which write operation is to perform |
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* @reg: lowest byte holds the register offset |
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* @value: data to write into the register |
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* |
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* The posted mode bit is encoded in reg. Note that in posted mode the write |
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* pending bit must be checked. Otherwise a write on a register which has a |
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* pending write will be lost. |
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*/ |
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static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, |
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u32 value) |
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{ |
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WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
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__omap_dm_timer_write(timer, reg, value, timer->posted); |
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} |
|
|
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static void omap_timer_restore_context(struct omap_dm_timer *timer) |
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{ |
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__omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, |
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timer->context.ocp_cfg, 0); |
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|
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omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, |
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timer->context.twer); |
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omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, |
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timer->context.tcrr); |
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omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, |
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timer->context.tldr); |
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omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, |
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timer->context.tmar); |
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, |
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timer->context.tsicr); |
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writel_relaxed(timer->context.tier, timer->irq_ena); |
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, |
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timer->context.tclr); |
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} |
|
|
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static void omap_timer_save_context(struct omap_dm_timer *timer) |
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{ |
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timer->context.ocp_cfg = |
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__omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); |
|
|
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timer->context.tclr = |
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omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
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timer->context.twer = |
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omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG); |
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timer->context.tldr = |
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omap_dm_timer_read_reg(timer, OMAP_TIMER_LOAD_REG); |
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timer->context.tmar = |
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omap_dm_timer_read_reg(timer, OMAP_TIMER_MATCH_REG); |
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timer->context.tier = readl_relaxed(timer->irq_ena); |
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timer->context.tsicr = |
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omap_dm_timer_read_reg(timer, OMAP_TIMER_IF_CTRL_REG); |
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} |
|
|
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static int omap_timer_context_notifier(struct notifier_block *nb, |
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unsigned long cmd, void *v) |
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{ |
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struct omap_dm_timer *timer; |
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|
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timer = container_of(nb, struct omap_dm_timer, nb); |
|
|
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switch (cmd) { |
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case CPU_CLUSTER_PM_ENTER: |
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if ((timer->capability & OMAP_TIMER_ALWON) || |
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!atomic_read(&timer->enabled)) |
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break; |
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omap_timer_save_context(timer); |
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break; |
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case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ |
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break; |
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case CPU_CLUSTER_PM_EXIT: |
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if ((timer->capability & OMAP_TIMER_ALWON) || |
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!atomic_read(&timer->enabled)) |
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break; |
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omap_timer_restore_context(timer); |
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break; |
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} |
|
|
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return NOTIFY_OK; |
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} |
|
|
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static int omap_dm_timer_reset(struct omap_dm_timer *timer) |
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{ |
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u32 l, timeout = 100000; |
|
|
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if (timer->revision != 1) |
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return -EINVAL; |
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|
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
|
|
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do { |
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l = __omap_dm_timer_read(timer, |
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OMAP_TIMER_V1_SYS_STAT_OFFSET, 0); |
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} while (!l && timeout--); |
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|
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if (!timeout) { |
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dev_err(&timer->pdev->dev, "Timer failed to reset\n"); |
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return -ETIMEDOUT; |
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} |
|
|
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/* Configure timer for smart-idle mode */ |
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l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); |
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l |= 0x2 << 0x3; |
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__omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); |
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|
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timer->posted = 0; |
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|
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return 0; |
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} |
|
|
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static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
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{ |
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int ret; |
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const char *parent_name; |
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struct clk *parent; |
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struct dmtimer_platform_data *pdata; |
|
|
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if (unlikely(!timer) || IS_ERR(timer->fclk)) |
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return -EINVAL; |
|
|
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switch (source) { |
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case OMAP_TIMER_SRC_SYS_CLK: |
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parent_name = "timer_sys_ck"; |
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break; |
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case OMAP_TIMER_SRC_32_KHZ: |
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parent_name = "timer_32k_ck"; |
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break; |
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case OMAP_TIMER_SRC_EXT_CLK: |
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parent_name = "timer_ext_ck"; |
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break; |
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default: |
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return -EINVAL; |
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} |
|
|
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pdata = timer->pdev->dev.platform_data; |
|
|
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/* |
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* FIXME: Used for OMAP1 devices only because they do not currently |
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* use the clock framework to set the parent clock. To be removed |
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* once OMAP1 migrated to using clock framework for dmtimers |
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*/ |
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if (pdata && pdata->set_timer_src) |
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return pdata->set_timer_src(timer->pdev, source); |
|
|
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#if defined(CONFIG_COMMON_CLK) |
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/* Check if the clock has configurable parents */ |
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if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) |
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return 0; |
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#endif |
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|
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parent = clk_get(&timer->pdev->dev, parent_name); |
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if (IS_ERR(parent)) { |
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pr_err("%s: %s not found\n", __func__, parent_name); |
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return -EINVAL; |
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} |
|
|
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ret = clk_set_parent(timer->fclk, parent); |
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if (ret < 0) |
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pr_err("%s: failed to set %s as parent\n", __func__, |
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parent_name); |
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|
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clk_put(parent); |
|
|
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return ret; |
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} |
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|
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static void omap_dm_timer_enable(struct omap_dm_timer *timer) |
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{ |
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pm_runtime_get_sync(&timer->pdev->dev); |
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} |
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|
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static void omap_dm_timer_disable(struct omap_dm_timer *timer) |
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{ |
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pm_runtime_put_sync(&timer->pdev->dev); |
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} |
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|
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static int omap_dm_timer_prepare(struct omap_dm_timer *timer) |
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{ |
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int rc; |
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|
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/* |
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* FIXME: OMAP1 devices do not use the clock framework for dmtimers so |
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* do not call clk_get() for these devices. |
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*/ |
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if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { |
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timer->fclk = clk_get(&timer->pdev->dev, "fck"); |
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if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { |
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dev_err(&timer->pdev->dev, ": No fclk handle.\n"); |
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return -EINVAL; |
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} |
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} |
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|
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omap_dm_timer_enable(timer); |
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|
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if (timer->capability & OMAP_TIMER_NEEDS_RESET) { |
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rc = omap_dm_timer_reset(timer); |
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if (rc) { |
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omap_dm_timer_disable(timer); |
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return rc; |
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} |
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} |
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|
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__omap_dm_timer_enable_posted(timer); |
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omap_dm_timer_disable(timer); |
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|
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return 0; |
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} |
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|
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static inline u32 omap_dm_timer_reserved_systimer(int id) |
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{ |
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return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; |
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} |
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|
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int omap_dm_timer_reserve_systimer(int id) |
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{ |
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if (omap_dm_timer_reserved_systimer(id)) |
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return -ENODEV; |
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|
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omap_reserved_systimers |= (1 << (id - 1)); |
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|
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return 0; |
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} |
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static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data) |
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{ |
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struct omap_dm_timer *timer = NULL, *t; |
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struct device_node *np = NULL; |
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unsigned long flags; |
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u32 cap = 0; |
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int id = 0; |
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|
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switch (req_type) { |
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case REQUEST_BY_ID: |
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id = *(int *)data; |
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break; |
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case REQUEST_BY_CAP: |
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cap = *(u32 *)data; |
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break; |
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case REQUEST_BY_NODE: |
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np = (struct device_node *)data; |
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break; |
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default: |
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/* REQUEST_ANY */ |
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break; |
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} |
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spin_lock_irqsave(&dm_timer_lock, flags); |
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list_for_each_entry(t, &omap_timer_list, node) { |
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if (t->reserved) |
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continue; |
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|
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switch (req_type) { |
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case REQUEST_BY_ID: |
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if (id == t->pdev->id) { |
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timer = t; |
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timer->reserved = 1; |
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goto found; |
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} |
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break; |
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case REQUEST_BY_CAP: |
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if (cap == (t->capability & cap)) { |
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/* |
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* If timer is not NULL, we have already found |
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* one timer. But it was not an exact match |
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* because it had more capabilities than what |
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* was required. Therefore, unreserve the last |
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* timer found and see if this one is a better |
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* match. |
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*/ |
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if (timer) |
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timer->reserved = 0; |
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timer = t; |
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timer->reserved = 1; |
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|
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/* Exit loop early if we find an exact match */ |
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if (t->capability == cap) |
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goto found; |
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} |
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break; |
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case REQUEST_BY_NODE: |
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if (np == t->pdev->dev.of_node) { |
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timer = t; |
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timer->reserved = 1; |
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goto found; |
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} |
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break; |
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default: |
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/* REQUEST_ANY */ |
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timer = t; |
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timer->reserved = 1; |
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goto found; |
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} |
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} |
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found: |
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spin_unlock_irqrestore(&dm_timer_lock, flags); |
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|
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if (timer && omap_dm_timer_prepare(timer)) { |
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timer->reserved = 0; |
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timer = NULL; |
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} |
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|
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if (!timer) |
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pr_debug("%s: timer request failed!\n", __func__); |
|
|
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return timer; |
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} |
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|
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static struct omap_dm_timer *omap_dm_timer_request(void) |
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{ |
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return _omap_dm_timer_request(REQUEST_ANY, NULL); |
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} |
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|
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static struct omap_dm_timer *omap_dm_timer_request_specific(int id) |
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{ |
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/* Requesting timer by ID is not supported when device tree is used */ |
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if (of_have_populated_dt()) { |
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pr_warn("%s: Please use omap_dm_timer_request_by_node()\n", |
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__func__); |
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return NULL; |
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} |
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|
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return _omap_dm_timer_request(REQUEST_BY_ID, &id); |
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} |
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|
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/** |
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* omap_dm_timer_request_by_cap - Request a timer by capability |
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* @cap: Bit mask of capabilities to match |
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* |
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* Find a timer based upon capabilities bit mask. Callers of this function |
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* should use the definitions found in the plat/dmtimer.h file under the |
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* comment "timer capabilities used in hwmod database". Returns pointer to |
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* timer handle on success and a NULL pointer on failure. |
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*/ |
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struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) |
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{ |
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return _omap_dm_timer_request(REQUEST_BY_CAP, &cap); |
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} |
|
|
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/** |
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* omap_dm_timer_request_by_node - Request a timer by device-tree node |
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* @np: Pointer to device-tree timer node |
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* |
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* Request a timer based upon a device node pointer. Returns pointer to |
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* timer handle on success and a NULL pointer on failure. |
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*/ |
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static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np) |
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{ |
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if (!np) |
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return NULL; |
|
|
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return _omap_dm_timer_request(REQUEST_BY_NODE, np); |
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} |
|
|
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static int omap_dm_timer_free(struct omap_dm_timer *timer) |
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{ |
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if (unlikely(!timer)) |
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return -EINVAL; |
|
|
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clk_put(timer->fclk); |
|
|
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WARN_ON(!timer->reserved); |
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timer->reserved = 0; |
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return 0; |
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} |
|
|
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int omap_dm_timer_get_irq(struct omap_dm_timer *timer) |
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{ |
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if (timer) |
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return timer->irq; |
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return -EINVAL; |
|
} |
|
|
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#if defined(CONFIG_ARCH_OMAP1) |
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#include <mach/hardware.h> |
|
|
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static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
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{ |
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return NULL; |
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} |
|
|
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/** |
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* omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR |
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* @inputmask: current value of idlect mask |
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*/ |
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__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
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{ |
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int i = 0; |
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struct omap_dm_timer *timer = NULL; |
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unsigned long flags; |
|
|
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/* If ARMXOR cannot be idled this function call is unnecessary */ |
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if (!(inputmask & (1 << 1))) |
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return inputmask; |
|
|
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/* If any active timer is using ARMXOR return modified mask */ |
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spin_lock_irqsave(&dm_timer_lock, flags); |
|
list_for_each_entry(timer, &omap_timer_list, node) { |
|
u32 l; |
|
|
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
|
if (l & OMAP_TIMER_CTRL_ST) { |
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if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) |
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inputmask &= ~(1 << 1); |
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else |
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inputmask &= ~(1 << 2); |
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} |
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i++; |
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} |
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spin_unlock_irqrestore(&dm_timer_lock, flags); |
|
|
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return inputmask; |
|
} |
|
|
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#else |
|
|
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static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
|
{ |
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if (timer && !IS_ERR(timer->fclk)) |
|
return timer->fclk; |
|
return NULL; |
|
} |
|
|
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__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
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{ |
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BUG(); |
|
|
|
return 0; |
|
} |
|
|
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#endif |
|
|
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int omap_dm_timer_trigger(struct omap_dm_timer *timer) |
|
{ |
|
if (unlikely(!timer || !atomic_read(&timer->enabled))) { |
|
pr_err("%s: timer not available or enabled.\n", __func__); |
|
return -EINVAL; |
|
} |
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
|
return 0; |
|
} |
|
|
|
static int omap_dm_timer_start(struct omap_dm_timer *timer) |
|
{ |
|
u32 l; |
|
|
|
if (unlikely(!timer)) |
|
return -EINVAL; |
|
|
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omap_dm_timer_enable(timer); |
|
|
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
|
if (!(l & OMAP_TIMER_CTRL_ST)) { |
|
l |= OMAP_TIMER_CTRL_ST; |
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omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int omap_dm_timer_stop(struct omap_dm_timer *timer) |
|
{ |
|
unsigned long rate = 0; |
|
|
|
if (unlikely(!timer)) |
|
return -EINVAL; |
|
|
|
if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) |
|
rate = clk_get_rate(timer->fclk); |
|
|
|
__omap_dm_timer_stop(timer, timer->posted, rate); |
|
|
|
omap_dm_timer_disable(timer); |
|
return 0; |
|
} |
|
|
|
static int omap_dm_timer_set_load(struct omap_dm_timer *timer, |
|
unsigned int load) |
|
{ |
|
if (unlikely(!timer)) |
|
return -EINVAL; |
|
|
|
omap_dm_timer_enable(timer); |
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
|
|
|
omap_dm_timer_disable(timer); |
|
return 0; |
|
} |
|
|
|
static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
|
unsigned int match) |
|
{ |
|
u32 l; |
|
|
|
if (unlikely(!timer)) |
|
return -EINVAL; |
|
|
|
omap_dm_timer_enable(timer); |
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
|
if (enable) |
|
l |= OMAP_TIMER_CTRL_CE; |
|
else |
|
l &= ~OMAP_TIMER_CTRL_CE; |
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
|
|
|
omap_dm_timer_disable(timer); |
|
return 0; |
|
} |
|
|
|
static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
|
int toggle, int trigger, int autoreload) |
|
{ |
|
u32 l; |
|
|
|
if (unlikely(!timer)) |
|
return -EINVAL; |
|
|
|
omap_dm_timer_enable(timer); |
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
|
l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | |
|
OMAP_TIMER_CTRL_PT | (0x03 << 10) | OMAP_TIMER_CTRL_AR); |
|
if (def_on) |
|
l |= OMAP_TIMER_CTRL_SCPWM; |
|
if (toggle) |
|
l |= OMAP_TIMER_CTRL_PT; |
|
l |= trigger << 10; |
|
if (autoreload) |
|
l |= OMAP_TIMER_CTRL_AR; |
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
|
|
|
omap_dm_timer_disable(timer); |
|
return 0; |
|
} |
|
|
|
static int omap_dm_timer_get_pwm_status(struct omap_dm_timer *timer) |
|
{ |
|
u32 l; |
|
|
|
if (unlikely(!timer)) |
|
return -EINVAL; |
|
|
|
omap_dm_timer_enable(timer); |
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
|
omap_dm_timer_disable(timer); |
|
|
|
return l; |
|
} |
|
|
|
static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, |
|
int prescaler) |
|
{ |
|
u32 l; |
|
|
|
if (unlikely(!timer) || prescaler < -1 || prescaler > 7) |
|
return -EINVAL; |
|
|
|
omap_dm_timer_enable(timer); |
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
|
l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); |
|
if (prescaler >= 0) { |
|
l |= OMAP_TIMER_CTRL_PRE; |
|
l |= prescaler << 2; |
|
} |
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
|
|
|
omap_dm_timer_disable(timer); |
|
return 0; |
|
} |
|
|
|
static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
|
unsigned int value) |
|
{ |
|
if (unlikely(!timer)) |
|
return -EINVAL; |
|
|
|
omap_dm_timer_enable(timer); |
|
__omap_dm_timer_int_enable(timer, value); |
|
|
|
omap_dm_timer_disable(timer); |
|
return 0; |
|
} |
|
|
|
/** |
|
* omap_dm_timer_set_int_disable - disable timer interrupts |
|
* @timer: pointer to timer handle |
|
* @mask: bit mask of interrupts to be disabled |
|
* |
|
* Disables the specified timer interrupts for a timer. |
|
*/ |
|
static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) |
|
{ |
|
u32 l = mask; |
|
|
|
if (unlikely(!timer)) |
|
return -EINVAL; |
|
|
|
omap_dm_timer_enable(timer); |
|
|
|
if (timer->revision == 1) |
|
l = readl_relaxed(timer->irq_ena) & ~mask; |
|
|
|
writel_relaxed(l, timer->irq_dis); |
|
l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; |
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); |
|
|
|
omap_dm_timer_disable(timer); |
|
return 0; |
|
} |
|
|
|
static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
|
{ |
|
unsigned int l; |
|
|
|
if (unlikely(!timer || !atomic_read(&timer->enabled))) { |
|
pr_err("%s: timer not available or enabled.\n", __func__); |
|
return 0; |
|
} |
|
|
|
l = readl_relaxed(timer->irq_stat); |
|
|
|
return l; |
|
} |
|
|
|
static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
|
{ |
|
if (unlikely(!timer || !atomic_read(&timer->enabled))) |
|
return -EINVAL; |
|
|
|
__omap_dm_timer_write_status(timer, value); |
|
|
|
return 0; |
|
} |
|
|
|
static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
|
{ |
|
if (unlikely(!timer || !atomic_read(&timer->enabled))) { |
|
pr_err("%s: timer not iavailable or enabled.\n", __func__); |
|
return 0; |
|
} |
|
|
|
return __omap_dm_timer_read_counter(timer, timer->posted); |
|
} |
|
|
|
static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
|
{ |
|
if (unlikely(!timer || !atomic_read(&timer->enabled))) { |
|
pr_err("%s: timer not available or enabled.\n", __func__); |
|
return -EINVAL; |
|
} |
|
|
|
omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
|
|
|
/* Save the context */ |
|
timer->context.tcrr = value; |
|
return 0; |
|
} |
|
|
|
int omap_dm_timers_active(void) |
|
{ |
|
struct omap_dm_timer *timer; |
|
|
|
list_for_each_entry(timer, &omap_timer_list, node) { |
|
if (!timer->reserved) |
|
continue; |
|
|
|
if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & |
|
OMAP_TIMER_CTRL_ST) { |
|
return 1; |
|
} |
|
} |
|
return 0; |
|
} |
|
|
|
static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev) |
|
{ |
|
struct omap_dm_timer *timer = dev_get_drvdata(dev); |
|
|
|
atomic_set(&timer->enabled, 0); |
|
|
|
if (timer->capability & OMAP_TIMER_ALWON || !timer->func_base) |
|
return 0; |
|
|
|
omap_timer_save_context(timer); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused omap_dm_timer_runtime_resume(struct device *dev) |
|
{ |
|
struct omap_dm_timer *timer = dev_get_drvdata(dev); |
|
|
|
if (!(timer->capability & OMAP_TIMER_ALWON) && timer->func_base) |
|
omap_timer_restore_context(timer); |
|
|
|
atomic_set(&timer->enabled, 1); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct dev_pm_ops omap_dm_timer_pm_ops = { |
|
SET_RUNTIME_PM_OPS(omap_dm_timer_runtime_suspend, |
|
omap_dm_timer_runtime_resume, NULL) |
|
}; |
|
|
|
static const struct of_device_id omap_timer_match[]; |
|
|
|
/** |
|
* omap_dm_timer_probe - probe function called for every registered device |
|
* @pdev: pointer to current timer platform device |
|
* |
|
* Called by driver framework at the end of device registration for all |
|
* timer devices. |
|
*/ |
|
static int omap_dm_timer_probe(struct platform_device *pdev) |
|
{ |
|
unsigned long flags; |
|
struct omap_dm_timer *timer; |
|
struct device *dev = &pdev->dev; |
|
const struct dmtimer_platform_data *pdata; |
|
int ret; |
|
|
|
pdata = of_device_get_match_data(dev); |
|
if (!pdata) |
|
pdata = dev_get_platdata(dev); |
|
else |
|
dev->platform_data = (void *)pdata; |
|
|
|
if (!pdata) { |
|
dev_err(dev, "%s: no platform data.\n", __func__); |
|
return -ENODEV; |
|
} |
|
|
|
timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL); |
|
if (!timer) |
|
return -ENOMEM; |
|
|
|
timer->irq = platform_get_irq(pdev, 0); |
|
if (timer->irq < 0) |
|
return timer->irq; |
|
|
|
timer->fclk = ERR_PTR(-ENODEV); |
|
timer->io_base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(timer->io_base)) |
|
return PTR_ERR(timer->io_base); |
|
|
|
platform_set_drvdata(pdev, timer); |
|
|
|
if (dev->of_node) { |
|
if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) |
|
timer->capability |= OMAP_TIMER_ALWON; |
|
if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) |
|
timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; |
|
if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) |
|
timer->capability |= OMAP_TIMER_HAS_PWM; |
|
if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) |
|
timer->capability |= OMAP_TIMER_SECURE; |
|
} else { |
|
timer->id = pdev->id; |
|
timer->capability = pdata->timer_capability; |
|
timer->reserved = omap_dm_timer_reserved_systimer(timer->id); |
|
} |
|
|
|
if (!(timer->capability & OMAP_TIMER_ALWON)) { |
|
timer->nb.notifier_call = omap_timer_context_notifier; |
|
cpu_pm_register_notifier(&timer->nb); |
|
} |
|
|
|
if (pdata) |
|
timer->errata = pdata->timer_errata; |
|
|
|
timer->pdev = pdev; |
|
|
|
pm_runtime_enable(dev); |
|
|
|
if (!timer->reserved) { |
|
ret = pm_runtime_get_sync(dev); |
|
if (ret < 0) { |
|
dev_err(dev, "%s: pm_runtime_get_sync failed!\n", |
|
__func__); |
|
goto err_get_sync; |
|
} |
|
__omap_dm_timer_init_regs(timer); |
|
pm_runtime_put(dev); |
|
} |
|
|
|
/* add the timer element to the list */ |
|
spin_lock_irqsave(&dm_timer_lock, flags); |
|
list_add_tail(&timer->node, &omap_timer_list); |
|
spin_unlock_irqrestore(&dm_timer_lock, flags); |
|
|
|
dev_dbg(dev, "Device Probed.\n"); |
|
|
|
return 0; |
|
|
|
err_get_sync: |
|
pm_runtime_put_noidle(dev); |
|
pm_runtime_disable(dev); |
|
return ret; |
|
} |
|
|
|
/** |
|
* omap_dm_timer_remove - cleanup a registered timer device |
|
* @pdev: pointer to current timer platform device |
|
* |
|
* Called by driver framework whenever a timer device is unregistered. |
|
* In addition to freeing platform resources it also deletes the timer |
|
* entry from the local list. |
|
*/ |
|
static int omap_dm_timer_remove(struct platform_device *pdev) |
|
{ |
|
struct omap_dm_timer *timer; |
|
unsigned long flags; |
|
int ret = -EINVAL; |
|
|
|
spin_lock_irqsave(&dm_timer_lock, flags); |
|
list_for_each_entry(timer, &omap_timer_list, node) |
|
if (!strcmp(dev_name(&timer->pdev->dev), |
|
dev_name(&pdev->dev))) { |
|
if (!(timer->capability & OMAP_TIMER_ALWON)) |
|
cpu_pm_unregister_notifier(&timer->nb); |
|
list_del(&timer->node); |
|
ret = 0; |
|
break; |
|
} |
|
spin_unlock_irqrestore(&dm_timer_lock, flags); |
|
|
|
pm_runtime_disable(&pdev->dev); |
|
|
|
return ret; |
|
} |
|
|
|
static const struct omap_dm_timer_ops dmtimer_ops = { |
|
.request_by_node = omap_dm_timer_request_by_node, |
|
.request_specific = omap_dm_timer_request_specific, |
|
.request = omap_dm_timer_request, |
|
.set_source = omap_dm_timer_set_source, |
|
.get_irq = omap_dm_timer_get_irq, |
|
.set_int_enable = omap_dm_timer_set_int_enable, |
|
.set_int_disable = omap_dm_timer_set_int_disable, |
|
.free = omap_dm_timer_free, |
|
.enable = omap_dm_timer_enable, |
|
.disable = omap_dm_timer_disable, |
|
.get_fclk = omap_dm_timer_get_fclk, |
|
.start = omap_dm_timer_start, |
|
.stop = omap_dm_timer_stop, |
|
.set_load = omap_dm_timer_set_load, |
|
.set_match = omap_dm_timer_set_match, |
|
.set_pwm = omap_dm_timer_set_pwm, |
|
.get_pwm_status = omap_dm_timer_get_pwm_status, |
|
.set_prescaler = omap_dm_timer_set_prescaler, |
|
.read_counter = omap_dm_timer_read_counter, |
|
.write_counter = omap_dm_timer_write_counter, |
|
.read_status = omap_dm_timer_read_status, |
|
.write_status = omap_dm_timer_write_status, |
|
}; |
|
|
|
static const struct dmtimer_platform_data omap3plus_pdata = { |
|
.timer_errata = OMAP_TIMER_ERRATA_I103_I767, |
|
.timer_ops = &dmtimer_ops, |
|
}; |
|
|
|
static const struct of_device_id omap_timer_match[] = { |
|
{ |
|
.compatible = "ti,omap2420-timer", |
|
}, |
|
{ |
|
.compatible = "ti,omap3430-timer", |
|
.data = &omap3plus_pdata, |
|
}, |
|
{ |
|
.compatible = "ti,omap4430-timer", |
|
.data = &omap3plus_pdata, |
|
}, |
|
{ |
|
.compatible = "ti,omap5430-timer", |
|
.data = &omap3plus_pdata, |
|
}, |
|
{ |
|
.compatible = "ti,am335x-timer", |
|
.data = &omap3plus_pdata, |
|
}, |
|
{ |
|
.compatible = "ti,am335x-timer-1ms", |
|
.data = &omap3plus_pdata, |
|
}, |
|
{ |
|
.compatible = "ti,dm816-timer", |
|
.data = &omap3plus_pdata, |
|
}, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, omap_timer_match); |
|
|
|
static struct platform_driver omap_dm_timer_driver = { |
|
.probe = omap_dm_timer_probe, |
|
.remove = omap_dm_timer_remove, |
|
.driver = { |
|
.name = "omap_timer", |
|
.of_match_table = of_match_ptr(omap_timer_match), |
|
.pm = &omap_dm_timer_pm_ops, |
|
}, |
|
}; |
|
|
|
module_platform_driver(omap_dm_timer_driver); |
|
|
|
MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_AUTHOR("Texas Instruments Inc");
|
|
|