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416 lines
10 KiB
416 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2010 Google, Inc. |
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* |
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* Author: |
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* Colin Cross <[email protected]> |
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*/ |
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#define pr_fmt(fmt) "tegra-timer: " fmt |
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#include <linux/clk.h> |
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#include <linux/clockchips.h> |
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#include <linux/cpu.h> |
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#include <linux/cpumask.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/interrupt.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/percpu.h> |
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#include <linux/sched_clock.h> |
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#include <linux/time.h> |
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#include "timer-of.h" |
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#define RTC_SECONDS 0x08 |
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#define RTC_SHADOW_SECONDS 0x0c |
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#define RTC_MILLISECONDS 0x10 |
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#define TIMERUS_CNTR_1US 0x10 |
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#define TIMERUS_USEC_CFG 0x14 |
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#define TIMERUS_CNTR_FREEZE 0x4c |
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#define TIMER_PTV 0x0 |
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#define TIMER_PTV_EN BIT(31) |
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#define TIMER_PTV_PER BIT(30) |
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#define TIMER_PCR 0x4 |
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#define TIMER_PCR_INTR_CLR BIT(30) |
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#define TIMER1_BASE 0x00 |
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#define TIMER2_BASE 0x08 |
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#define TIMER3_BASE 0x50 |
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#define TIMER4_BASE 0x58 |
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#define TIMER10_BASE 0x90 |
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#define TIMER1_IRQ_IDX 0 |
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#define TIMER10_IRQ_IDX 10 |
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#define TIMER_1MHz 1000000 |
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static u32 usec_config; |
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static void __iomem *timer_reg_base; |
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static int tegra_timer_set_next_event(unsigned long cycles, |
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struct clock_event_device *evt) |
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{ |
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void __iomem *reg_base = timer_of_base(to_timer_of(evt)); |
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/* |
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* Tegra's timer uses n+1 scheme for the counter, i.e. timer will |
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* fire after one tick if 0 is loaded. |
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* |
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* The minimum and maximum numbers of oneshot ticks are defined |
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* by clockevents_config_and_register(1, 0x1fffffff + 1) invocation |
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* below in the code. Hence the cycles (ticks) can't be outside of |
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* a range supportable by hardware. |
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*/ |
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writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV); |
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return 0; |
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} |
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static int tegra_timer_shutdown(struct clock_event_device *evt) |
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{ |
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void __iomem *reg_base = timer_of_base(to_timer_of(evt)); |
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writel_relaxed(0, reg_base + TIMER_PTV); |
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return 0; |
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} |
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static int tegra_timer_set_periodic(struct clock_event_device *evt) |
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{ |
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void __iomem *reg_base = timer_of_base(to_timer_of(evt)); |
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unsigned long period = timer_of_period(to_timer_of(evt)); |
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writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1), |
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reg_base + TIMER_PTV); |
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return 0; |
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} |
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static irqreturn_t tegra_timer_isr(int irq, void *dev_id) |
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{ |
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struct clock_event_device *evt = dev_id; |
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void __iomem *reg_base = timer_of_base(to_timer_of(evt)); |
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writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); |
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evt->event_handler(evt); |
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return IRQ_HANDLED; |
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} |
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static void tegra_timer_suspend(struct clock_event_device *evt) |
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{ |
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void __iomem *reg_base = timer_of_base(to_timer_of(evt)); |
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writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); |
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} |
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static void tegra_timer_resume(struct clock_event_device *evt) |
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{ |
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writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); |
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} |
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static DEFINE_PER_CPU(struct timer_of, tegra_to) = { |
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.flags = TIMER_OF_CLOCK | TIMER_OF_BASE, |
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.clkevt = { |
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.name = "tegra_timer", |
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, |
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.set_next_event = tegra_timer_set_next_event, |
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.set_state_shutdown = tegra_timer_shutdown, |
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.set_state_periodic = tegra_timer_set_periodic, |
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.set_state_oneshot = tegra_timer_shutdown, |
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.tick_resume = tegra_timer_shutdown, |
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.suspend = tegra_timer_suspend, |
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.resume = tegra_timer_resume, |
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}, |
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}; |
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static int tegra_timer_setup(unsigned int cpu) |
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{ |
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struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); |
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writel_relaxed(0, timer_of_base(to) + TIMER_PTV); |
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writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); |
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irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); |
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enable_irq(to->clkevt.irq); |
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/* |
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* Tegra's timer uses n+1 scheme for the counter, i.e. timer will |
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* fire after one tick if 0 is loaded and thus minimum number of |
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* ticks is 1. In result both of the clocksource's tick limits are |
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* higher than a minimum and maximum that hardware register can |
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* take by 1, this is then taken into account by set_next_event |
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* callback. |
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*/ |
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clockevents_config_and_register(&to->clkevt, timer_of_rate(to), |
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1, /* min */ |
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0x1fffffff + 1); /* max 29 bits + 1 */ |
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return 0; |
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} |
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static int tegra_timer_stop(unsigned int cpu) |
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{ |
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struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); |
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to->clkevt.set_state_shutdown(&to->clkevt); |
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disable_irq_nosync(to->clkevt.irq); |
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return 0; |
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} |
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static u64 notrace tegra_read_sched_clock(void) |
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{ |
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return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US); |
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} |
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#ifdef CONFIG_ARM |
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static unsigned long tegra_delay_timer_read_counter_long(void) |
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{ |
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return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US); |
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} |
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static struct delay_timer tegra_delay_timer = { |
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.read_current_timer = tegra_delay_timer_read_counter_long, |
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.freq = TIMER_1MHz, |
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}; |
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#endif |
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static struct timer_of suspend_rtc_to = { |
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.flags = TIMER_OF_BASE | TIMER_OF_CLOCK, |
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}; |
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/* |
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* tegra_rtc_read - Reads the Tegra RTC registers |
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* Care must be taken that this function is not called while the |
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* tegra_rtc driver could be executing to avoid race conditions |
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* on the RTC shadow register |
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*/ |
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static u64 tegra_rtc_read_ms(struct clocksource *cs) |
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{ |
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void __iomem *reg_base = timer_of_base(&suspend_rtc_to); |
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u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS); |
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u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS); |
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return (u64)s * MSEC_PER_SEC + ms; |
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} |
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static struct clocksource suspend_rtc_clocksource = { |
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.name = "tegra_suspend_timer", |
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.rating = 200, |
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.read = tegra_rtc_read_ms, |
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.mask = CLOCKSOURCE_MASK(32), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, |
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}; |
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static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20) |
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{ |
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if (tegra20) { |
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switch (cpu) { |
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case 0: |
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return TIMER1_BASE; |
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case 1: |
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return TIMER2_BASE; |
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case 2: |
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return TIMER3_BASE; |
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default: |
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return TIMER4_BASE; |
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} |
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} |
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return TIMER10_BASE + cpu * 8; |
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} |
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static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20) |
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{ |
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if (tegra20) |
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return TIMER1_IRQ_IDX + cpu; |
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return TIMER10_IRQ_IDX + cpu; |
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} |
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static inline unsigned long tegra_rate_for_timer(struct timer_of *to, |
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bool tegra20) |
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{ |
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/* |
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* TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the |
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* parent clock. |
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*/ |
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if (tegra20) |
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return TIMER_1MHz; |
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return timer_of_rate(to); |
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} |
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static int __init tegra_init_timer(struct device_node *np, bool tegra20, |
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int rating) |
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{ |
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struct timer_of *to; |
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int cpu, ret; |
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to = this_cpu_ptr(&tegra_to); |
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ret = timer_of_init(np, to); |
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if (ret) |
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goto out; |
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timer_reg_base = timer_of_base(to); |
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/* |
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* Configure microsecond timers to have 1MHz clock |
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* Config register is 0xqqww, where qq is "dividend", ww is "divisor" |
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* Uses n+1 scheme |
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*/ |
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switch (timer_of_rate(to)) { |
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case 12000000: |
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usec_config = 0x000b; /* (11+1)/(0+1) */ |
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break; |
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case 12800000: |
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usec_config = 0x043f; /* (63+1)/(4+1) */ |
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break; |
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case 13000000: |
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usec_config = 0x000c; /* (12+1)/(0+1) */ |
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break; |
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case 16800000: |
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usec_config = 0x0453; /* (83+1)/(4+1) */ |
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break; |
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case 19200000: |
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usec_config = 0x045f; /* (95+1)/(4+1) */ |
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break; |
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case 26000000: |
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usec_config = 0x0019; /* (25+1)/(0+1) */ |
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break; |
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case 38400000: |
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usec_config = 0x04bf; /* (191+1)/(4+1) */ |
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break; |
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case 48000000: |
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usec_config = 0x002f; /* (47+1)/(0+1) */ |
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break; |
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default: |
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ret = -EINVAL; |
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goto out; |
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} |
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writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); |
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for_each_possible_cpu(cpu) { |
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struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); |
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unsigned long flags = IRQF_TIMER | IRQF_NOBALANCING; |
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unsigned long rate = tegra_rate_for_timer(to, tegra20); |
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unsigned int base = tegra_base_for_cpu(cpu, tegra20); |
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unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20); |
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unsigned int irq = irq_of_parse_and_map(np, idx); |
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if (!irq) { |
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pr_err("failed to map irq for cpu%d\n", cpu); |
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ret = -EINVAL; |
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goto out_irq; |
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} |
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cpu_to->clkevt.irq = irq; |
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cpu_to->clkevt.rating = rating; |
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cpu_to->clkevt.cpumask = cpumask_of(cpu); |
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cpu_to->of_base.base = timer_reg_base + base; |
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cpu_to->of_clk.period = rate / HZ; |
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cpu_to->of_clk.rate = rate; |
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irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); |
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ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, flags, |
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cpu_to->clkevt.name, &cpu_to->clkevt); |
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if (ret) { |
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pr_err("failed to set up irq for cpu%d: %d\n", |
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cpu, ret); |
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irq_dispose_mapping(cpu_to->clkevt.irq); |
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cpu_to->clkevt.irq = 0; |
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goto out_irq; |
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} |
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} |
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sched_clock_register(tegra_read_sched_clock, 32, TIMER_1MHz); |
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ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, |
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"timer_us", TIMER_1MHz, 300, 32, |
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clocksource_mmio_readl_up); |
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if (ret) |
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pr_err("failed to register clocksource: %d\n", ret); |
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#ifdef CONFIG_ARM |
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register_current_timer_delay(&tegra_delay_timer); |
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#endif |
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ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, |
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"AP_TEGRA_TIMER_STARTING", tegra_timer_setup, |
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tegra_timer_stop); |
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if (ret) |
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pr_err("failed to set up cpu hp state: %d\n", ret); |
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return ret; |
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out_irq: |
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for_each_possible_cpu(cpu) { |
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struct timer_of *cpu_to; |
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cpu_to = per_cpu_ptr(&tegra_to, cpu); |
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if (cpu_to->clkevt.irq) { |
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free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt); |
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irq_dispose_mapping(cpu_to->clkevt.irq); |
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} |
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} |
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to->of_base.base = timer_reg_base; |
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out: |
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timer_of_cleanup(to); |
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return ret; |
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} |
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static int __init tegra210_init_timer(struct device_node *np) |
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{ |
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/* |
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* Arch-timer can't survive across power cycle of CPU core and |
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* after CPUPORESET signal due to a system design shortcoming, |
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* hence tegra-timer is more preferable on Tegra210. |
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*/ |
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return tegra_init_timer(np, false, 460); |
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} |
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TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); |
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static int __init tegra20_init_timer(struct device_node *np) |
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{ |
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int rating; |
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/* |
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* Tegra20 and Tegra30 have Cortex A9 CPU that has a TWD timer, |
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* that timer runs off the CPU clock and hence is subjected to |
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* a jitter caused by DVFS clock rate changes. Tegra-timer is |
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* more preferable for older Tegra's, while later SoC generations |
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* have arch-timer as a main per-CPU timer and it is not affected |
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* by DVFS changes. |
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*/ |
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if (of_machine_is_compatible("nvidia,tegra20") || |
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of_machine_is_compatible("nvidia,tegra30")) |
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rating = 460; |
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else |
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rating = 330; |
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return tegra_init_timer(np, true, rating); |
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} |
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TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); |
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static int __init tegra20_init_rtc(struct device_node *np) |
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{ |
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int ret; |
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ret = timer_of_init(np, &suspend_rtc_to); |
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if (ret) |
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return ret; |
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return clocksource_register_hz(&suspend_rtc_clocksource, 1000); |
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} |
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TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
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