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390 lines
8.7 KiB
390 lines
8.7 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* linux/drivers/clocksource/timer-sp.c |
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* |
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* Copyright (C) 1999 - 2003 ARM Limited |
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* Copyright (C) 2000 Deep Blue Solutions Ltd |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/clk.h> |
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#include <linux/clocksource.h> |
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#include <linux/clockchips.h> |
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#include <linux/err.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_clk.h> |
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#include <linux/of_irq.h> |
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#include <linux/sched_clock.h> |
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#include "timer-sp.h" |
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/* Hisilicon 64-bit timer(a variant of ARM SP804) */ |
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#define HISI_TIMER_1_BASE 0x00 |
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#define HISI_TIMER_2_BASE 0x40 |
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#define HISI_TIMER_LOAD 0x00 |
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#define HISI_TIMER_LOAD_H 0x04 |
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#define HISI_TIMER_VALUE 0x08 |
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#define HISI_TIMER_VALUE_H 0x0c |
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#define HISI_TIMER_CTRL 0x10 |
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#define HISI_TIMER_INTCLR 0x14 |
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#define HISI_TIMER_RIS 0x18 |
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#define HISI_TIMER_MIS 0x1c |
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#define HISI_TIMER_BGLOAD 0x20 |
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#define HISI_TIMER_BGLOAD_H 0x24 |
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static struct sp804_timer arm_sp804_timer __initdata = { |
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.load = TIMER_LOAD, |
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.value = TIMER_VALUE, |
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.ctrl = TIMER_CTRL, |
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.intclr = TIMER_INTCLR, |
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.timer_base = {TIMER_1_BASE, TIMER_2_BASE}, |
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.width = 32, |
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}; |
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static struct sp804_timer hisi_sp804_timer __initdata = { |
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.load = HISI_TIMER_LOAD, |
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.load_h = HISI_TIMER_LOAD_H, |
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.value = HISI_TIMER_VALUE, |
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.value_h = HISI_TIMER_VALUE_H, |
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.ctrl = HISI_TIMER_CTRL, |
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.intclr = HISI_TIMER_INTCLR, |
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.timer_base = {HISI_TIMER_1_BASE, HISI_TIMER_2_BASE}, |
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.width = 64, |
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}; |
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static struct sp804_clkevt sp804_clkevt[NR_TIMERS]; |
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static long __init sp804_get_clock_rate(struct clk *clk, const char *name) |
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{ |
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int err; |
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if (!clk) |
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clk = clk_get_sys("sp804", name); |
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if (IS_ERR(clk)) { |
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pr_err("%s clock not found: %ld\n", name, PTR_ERR(clk)); |
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return PTR_ERR(clk); |
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} |
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err = clk_prepare_enable(clk); |
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if (err) { |
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pr_err("clock failed to enable: %d\n", err); |
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clk_put(clk); |
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return err; |
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} |
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return clk_get_rate(clk); |
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} |
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static struct sp804_clkevt * __init sp804_clkevt_get(void __iomem *base) |
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{ |
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int i; |
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for (i = 0; i < NR_TIMERS; i++) { |
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if (sp804_clkevt[i].base == base) |
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return &sp804_clkevt[i]; |
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} |
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/* It's impossible to reach here */ |
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WARN_ON(1); |
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return NULL; |
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} |
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static struct sp804_clkevt *sched_clkevt; |
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static u64 notrace sp804_read(void) |
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{ |
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return ~readl_relaxed(sched_clkevt->value); |
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} |
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static int __init sp804_clocksource_and_sched_clock_init(void __iomem *base, |
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const char *name, |
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struct clk *clk, |
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int use_sched_clock) |
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{ |
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long rate; |
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struct sp804_clkevt *clkevt; |
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rate = sp804_get_clock_rate(clk, name); |
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if (rate < 0) |
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return -EINVAL; |
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clkevt = sp804_clkevt_get(base); |
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writel(0, clkevt->ctrl); |
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writel(0xffffffff, clkevt->load); |
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writel(0xffffffff, clkevt->value); |
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if (clkevt->width == 64) { |
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writel(0xffffffff, clkevt->load_h); |
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writel(0xffffffff, clkevt->value_h); |
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} |
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writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, |
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clkevt->ctrl); |
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clocksource_mmio_init(clkevt->value, name, |
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rate, 200, 32, clocksource_mmio_readl_down); |
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if (use_sched_clock) { |
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sched_clkevt = clkevt; |
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sched_clock_register(sp804_read, 32, rate); |
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} |
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return 0; |
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} |
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static struct sp804_clkevt *common_clkevt; |
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/* |
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* IRQ handler for the timer |
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*/ |
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static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id) |
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{ |
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struct clock_event_device *evt = dev_id; |
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/* clear the interrupt */ |
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writel(1, common_clkevt->intclr); |
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evt->event_handler(evt); |
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return IRQ_HANDLED; |
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} |
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static inline void timer_shutdown(struct clock_event_device *evt) |
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{ |
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writel(0, common_clkevt->ctrl); |
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} |
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static int sp804_shutdown(struct clock_event_device *evt) |
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{ |
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timer_shutdown(evt); |
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return 0; |
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} |
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static int sp804_set_periodic(struct clock_event_device *evt) |
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{ |
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unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE | |
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TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; |
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timer_shutdown(evt); |
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writel(common_clkevt->reload, common_clkevt->load); |
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writel(ctrl, common_clkevt->ctrl); |
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return 0; |
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} |
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static int sp804_set_next_event(unsigned long next, |
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struct clock_event_device *evt) |
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{ |
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unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE | |
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TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE; |
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writel(next, common_clkevt->load); |
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writel(ctrl, common_clkevt->ctrl); |
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return 0; |
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} |
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static struct clock_event_device sp804_clockevent = { |
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.features = CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_ONESHOT | |
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CLOCK_EVT_FEAT_DYNIRQ, |
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.set_state_shutdown = sp804_shutdown, |
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.set_state_periodic = sp804_set_periodic, |
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.set_state_oneshot = sp804_shutdown, |
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.tick_resume = sp804_shutdown, |
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.set_next_event = sp804_set_next_event, |
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.rating = 300, |
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}; |
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static int __init sp804_clockevents_init(void __iomem *base, unsigned int irq, |
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struct clk *clk, const char *name) |
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{ |
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struct clock_event_device *evt = &sp804_clockevent; |
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long rate; |
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rate = sp804_get_clock_rate(clk, name); |
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if (rate < 0) |
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return -EINVAL; |
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common_clkevt = sp804_clkevt_get(base); |
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common_clkevt->reload = DIV_ROUND_CLOSEST(rate, HZ); |
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evt->name = name; |
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evt->irq = irq; |
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evt->cpumask = cpu_possible_mask; |
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writel(0, common_clkevt->ctrl); |
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if (request_irq(irq, sp804_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, |
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"timer", &sp804_clockevent)) |
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pr_err("request_irq() failed\n"); |
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clockevents_config_and_register(evt, rate, 0xf, 0xffffffff); |
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return 0; |
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} |
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static void __init sp804_clkevt_init(struct sp804_timer *timer, void __iomem *base) |
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{ |
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int i; |
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for (i = 0; i < NR_TIMERS; i++) { |
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void __iomem *timer_base; |
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struct sp804_clkevt *clkevt; |
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timer_base = base + timer->timer_base[i]; |
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clkevt = &sp804_clkevt[i]; |
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clkevt->base = timer_base; |
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clkevt->load = timer_base + timer->load; |
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clkevt->load_h = timer_base + timer->load_h; |
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clkevt->value = timer_base + timer->value; |
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clkevt->value_h = timer_base + timer->value_h; |
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clkevt->ctrl = timer_base + timer->ctrl; |
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clkevt->intclr = timer_base + timer->intclr; |
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clkevt->width = timer->width; |
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} |
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} |
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static int __init sp804_of_init(struct device_node *np, struct sp804_timer *timer) |
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{ |
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static bool initialized = false; |
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void __iomem *base; |
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void __iomem *timer1_base; |
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void __iomem *timer2_base; |
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int irq, ret = -EINVAL; |
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u32 irq_num = 0; |
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struct clk *clk1, *clk2; |
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const char *name = of_get_property(np, "compatible", NULL); |
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base = of_iomap(np, 0); |
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if (!base) |
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return -ENXIO; |
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timer1_base = base + timer->timer_base[0]; |
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timer2_base = base + timer->timer_base[1]; |
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/* Ensure timers are disabled */ |
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writel(0, timer1_base + timer->ctrl); |
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writel(0, timer2_base + timer->ctrl); |
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if (initialized || !of_device_is_available(np)) { |
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ret = -EINVAL; |
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goto err; |
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} |
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clk1 = of_clk_get(np, 0); |
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if (IS_ERR(clk1)) |
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clk1 = NULL; |
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/* Get the 2nd clock if the timer has 3 timer clocks */ |
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if (of_clk_get_parent_count(np) == 3) { |
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clk2 = of_clk_get(np, 1); |
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if (IS_ERR(clk2)) { |
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pr_err("%pOFn clock not found: %d\n", np, |
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(int)PTR_ERR(clk2)); |
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clk2 = NULL; |
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} |
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} else |
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clk2 = clk1; |
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irq = irq_of_parse_and_map(np, 0); |
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if (irq <= 0) |
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goto err; |
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sp804_clkevt_init(timer, base); |
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of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); |
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if (irq_num == 2) { |
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ret = sp804_clockevents_init(timer2_base, irq, clk2, name); |
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if (ret) |
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goto err; |
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ret = sp804_clocksource_and_sched_clock_init(timer1_base, |
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name, clk1, 1); |
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if (ret) |
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goto err; |
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} else { |
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ret = sp804_clockevents_init(timer1_base, irq, clk1, name); |
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if (ret) |
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goto err; |
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ret = sp804_clocksource_and_sched_clock_init(timer2_base, |
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name, clk2, 1); |
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if (ret) |
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goto err; |
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} |
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initialized = true; |
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return 0; |
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err: |
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iounmap(base); |
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return ret; |
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} |
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static int __init arm_sp804_of_init(struct device_node *np) |
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{ |
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return sp804_of_init(np, &arm_sp804_timer); |
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} |
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TIMER_OF_DECLARE(sp804, "arm,sp804", arm_sp804_of_init); |
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static int __init hisi_sp804_of_init(struct device_node *np) |
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{ |
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return sp804_of_init(np, &hisi_sp804_timer); |
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} |
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TIMER_OF_DECLARE(hisi_sp804, "hisilicon,sp804", hisi_sp804_of_init); |
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static int __init integrator_cp_of_init(struct device_node *np) |
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{ |
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static int init_count = 0; |
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void __iomem *base; |
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int irq, ret = -EINVAL; |
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const char *name = of_get_property(np, "compatible", NULL); |
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struct clk *clk; |
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base = of_iomap(np, 0); |
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if (!base) { |
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pr_err("Failed to iomap\n"); |
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return -ENXIO; |
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} |
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clk = of_clk_get(np, 0); |
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if (IS_ERR(clk)) { |
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pr_err("Failed to get clock\n"); |
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return PTR_ERR(clk); |
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} |
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/* Ensure timer is disabled */ |
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writel(0, base + arm_sp804_timer.ctrl); |
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if (init_count == 2 || !of_device_is_available(np)) |
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goto err; |
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sp804_clkevt_init(&arm_sp804_timer, base); |
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if (!init_count) { |
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ret = sp804_clocksource_and_sched_clock_init(base, |
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name, clk, 0); |
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if (ret) |
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goto err; |
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} else { |
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irq = irq_of_parse_and_map(np, 0); |
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if (irq <= 0) |
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goto err; |
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ret = sp804_clockevents_init(base, irq, clk, name); |
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if (ret) |
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goto err; |
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} |
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init_count++; |
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return 0; |
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err: |
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iounmap(base); |
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return ret; |
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} |
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TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);
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