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284 lines
7.4 KiB
284 lines
7.4 KiB
/* |
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* Copyright (c) 2016, Mellanox Technologies. All rights reserved. |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the |
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* OpenIB.org BSD license below: |
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* |
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* Redistribution and use in source and binary forms, with or |
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* without modification, are permitted provided that the following |
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* conditions are met: |
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* |
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* - Redistributions of source code must retain the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer. |
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* |
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* - Redistributions in binary form must reproduce the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer in the documentation and/or other materials |
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* provided with the distribution. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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* SOFTWARE. |
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*/ |
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#include <linux/interrupt.h> |
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#include <linux/clocksource.h> |
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#include <linux/clockchips.h> |
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#include <linux/clk.h> |
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#include <linux/of.h> |
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#include <linux/of_irq.h> |
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#include <linux/cpu.h> |
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#include <soc/nps/common.h> |
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#define NPS_MSU_TICK_LOW 0xC8 |
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#define NPS_CLUSTER_OFFSET 8 |
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#define NPS_CLUSTER_NUM 16 |
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/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */ |
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static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly; |
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static int __init nps_get_timer_clk(struct device_node *node, |
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unsigned long *timer_freq, |
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struct clk **clk) |
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{ |
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int ret; |
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*clk = of_clk_get(node, 0); |
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ret = PTR_ERR_OR_ZERO(*clk); |
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if (ret) { |
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pr_err("timer missing clk\n"); |
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return ret; |
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} |
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ret = clk_prepare_enable(*clk); |
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if (ret) { |
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pr_err("Couldn't enable parent clk\n"); |
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clk_put(*clk); |
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return ret; |
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} |
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*timer_freq = clk_get_rate(*clk); |
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if (!(*timer_freq)) { |
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pr_err("Couldn't get clk rate\n"); |
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clk_disable_unprepare(*clk); |
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clk_put(*clk); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static u64 nps_clksrc_read(struct clocksource *clksrc) |
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{ |
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int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET; |
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return (u64)ioread32be(nps_msu_reg_low_addr[cluster]); |
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} |
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static int __init nps_setup_clocksource(struct device_node *node) |
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{ |
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int ret, cluster; |
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struct clk *clk; |
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unsigned long nps_timer1_freq; |
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for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++) |
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nps_msu_reg_low_addr[cluster] = |
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nps_host_reg((cluster << NPS_CLUSTER_OFFSET), |
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NPS_MSU_BLKID, NPS_MSU_TICK_LOW); |
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ret = nps_get_timer_clk(node, &nps_timer1_freq, &clk); |
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if (ret) |
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return ret; |
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ret = clocksource_mmio_init(nps_msu_reg_low_addr, "nps-tick", |
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nps_timer1_freq, 300, 32, nps_clksrc_read); |
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if (ret) { |
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pr_err("Couldn't register clock source.\n"); |
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clk_disable_unprepare(clk); |
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} |
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return ret; |
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} |
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TIMER_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer", |
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nps_setup_clocksource); |
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TIMER_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1", |
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nps_setup_clocksource); |
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#ifdef CONFIG_EZNPS_MTM_EXT |
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#include <soc/nps/mtm.h> |
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/* Timer related Aux registers */ |
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#define NPS_REG_TIMER0_TSI 0xFFFFF850 |
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#define NPS_REG_TIMER0_LIMIT 0x23 |
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#define NPS_REG_TIMER0_CTRL 0x22 |
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#define NPS_REG_TIMER0_CNT 0x21 |
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/* |
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* Interrupt Enabled (IE) - re-arm the timer |
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* Not Halted (NH) - is cleared when working with JTAG (for debug) |
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*/ |
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#define TIMER0_CTRL_IE BIT(0) |
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#define TIMER0_CTRL_NH BIT(1) |
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static unsigned long nps_timer0_freq; |
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static unsigned long nps_timer0_irq; |
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static void nps_clkevent_rm_thread(void) |
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{ |
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int thread; |
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unsigned int cflags, enabled_threads; |
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hw_schd_save(&cflags); |
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enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI); |
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/* remove thread from TSI1 */ |
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thread = read_aux_reg(CTOP_AUX_THREAD_ID); |
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enabled_threads &= ~(1 << thread); |
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write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads); |
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/* Acknowledge and if needed re-arm the timer */ |
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if (!enabled_threads) |
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write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_NH); |
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else |
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write_aux_reg(NPS_REG_TIMER0_CTRL, |
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TIMER0_CTRL_IE | TIMER0_CTRL_NH); |
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hw_schd_restore(cflags); |
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} |
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static void nps_clkevent_add_thread(unsigned long delta) |
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{ |
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int thread; |
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unsigned int cflags, enabled_threads; |
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hw_schd_save(&cflags); |
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/* add thread to TSI1 */ |
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thread = read_aux_reg(CTOP_AUX_THREAD_ID); |
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enabled_threads = read_aux_reg(NPS_REG_TIMER0_TSI); |
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enabled_threads |= (1 << thread); |
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write_aux_reg(NPS_REG_TIMER0_TSI, enabled_threads); |
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/* set next timer event */ |
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write_aux_reg(NPS_REG_TIMER0_LIMIT, delta); |
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write_aux_reg(NPS_REG_TIMER0_CNT, 0); |
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write_aux_reg(NPS_REG_TIMER0_CTRL, |
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TIMER0_CTRL_IE | TIMER0_CTRL_NH); |
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hw_schd_restore(cflags); |
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} |
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/* |
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* Whenever anyone tries to change modes, we just mask interrupts |
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* and wait for the next event to get set. |
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*/ |
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static int nps_clkevent_set_state(struct clock_event_device *dev) |
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{ |
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nps_clkevent_rm_thread(); |
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disable_percpu_irq(nps_timer0_irq); |
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return 0; |
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} |
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static int nps_clkevent_set_next_event(unsigned long delta, |
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struct clock_event_device *dev) |
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{ |
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nps_clkevent_add_thread(delta); |
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enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE); |
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return 0; |
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} |
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static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = { |
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.name = "NPS Timer0", |
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.features = CLOCK_EVT_FEAT_ONESHOT, |
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.rating = 300, |
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.set_next_event = nps_clkevent_set_next_event, |
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.set_state_oneshot = nps_clkevent_set_state, |
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.set_state_oneshot_stopped = nps_clkevent_set_state, |
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.set_state_shutdown = nps_clkevent_set_state, |
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.tick_resume = nps_clkevent_set_state, |
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}; |
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static irqreturn_t timer_irq_handler(int irq, void *dev_id) |
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{ |
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struct clock_event_device *evt = dev_id; |
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nps_clkevent_rm_thread(); |
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evt->event_handler(evt); |
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return IRQ_HANDLED; |
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} |
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static int nps_timer_starting_cpu(unsigned int cpu) |
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{ |
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struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device); |
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evt->cpumask = cpumask_of(smp_processor_id()); |
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clockevents_config_and_register(evt, nps_timer0_freq, 0, ULONG_MAX); |
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enable_percpu_irq(nps_timer0_irq, IRQ_TYPE_NONE); |
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return 0; |
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} |
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static int nps_timer_dying_cpu(unsigned int cpu) |
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{ |
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disable_percpu_irq(nps_timer0_irq); |
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return 0; |
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} |
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static int __init nps_setup_clockevent(struct device_node *node) |
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{ |
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struct clk *clk; |
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int ret; |
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nps_timer0_irq = irq_of_parse_and_map(node, 0); |
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if (nps_timer0_irq <= 0) { |
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pr_err("clockevent: missing irq\n"); |
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return -EINVAL; |
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} |
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ret = nps_get_timer_clk(node, &nps_timer0_freq, &clk); |
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if (ret) |
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return ret; |
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/* Needs apriori irq_set_percpu_devid() done in intc map function */ |
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ret = request_percpu_irq(nps_timer0_irq, timer_irq_handler, |
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"Timer0 (per-cpu-tick)", |
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&nps_clockevent_device); |
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if (ret) { |
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pr_err("Couldn't request irq\n"); |
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clk_disable_unprepare(clk); |
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return ret; |
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} |
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ret = cpuhp_setup_state(CPUHP_AP_ARC_TIMER_STARTING, |
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"clockevents/nps:starting", |
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nps_timer_starting_cpu, |
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nps_timer_dying_cpu); |
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if (ret) { |
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pr_err("Failed to setup hotplug state\n"); |
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clk_disable_unprepare(clk); |
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free_percpu_irq(nps_timer0_irq, &nps_clockevent_device); |
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return ret; |
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} |
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return 0; |
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} |
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TIMER_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0", |
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nps_setup_clockevent); |
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#endif /* CONFIG_EZNPS_MTM_EXT */
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