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510 lines
13 KiB
510 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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#include <linux/init.h> |
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#include <linux/clocksource.h> |
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#include <linux/clockchips.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/ioport.h> |
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#include <linux/io.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/sched_clock.h> |
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#include <linux/syscore_ops.h> |
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#include <soc/at91/atmel_tcb.h> |
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/* |
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* We're configured to use a specific TC block, one that's not hooked |
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* up to external hardware, to provide a time solution: |
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* |
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* - Two channels combine to create a free-running 32 bit counter |
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* with a base rate of 5+ MHz, packaged as a clocksource (with |
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* resolution better than 200 nsec). |
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* - Some chips support 32 bit counter. A single channel is used for |
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* this 32 bit free-running counter. the second channel is not used. |
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* |
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* - The third channel may be used to provide a clockevent source, used in |
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* either periodic or oneshot mode. For 16-bit counter its runs at 32 KiHZ, |
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* and can handle delays of up to two seconds. For 32-bit counters, it runs at |
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* the same rate as the clocksource |
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* |
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* REVISIT behavior during system suspend states... we should disable |
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* all clocks and save the power. Easily done for clockevent devices, |
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* but clocksources won't necessarily get the needed notifications. |
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* For deeper system sleep states, this will be mandatory... |
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*/ |
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static void __iomem *tcaddr; |
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static struct |
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{ |
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u32 cmr; |
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u32 imr; |
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u32 rc; |
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bool clken; |
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} tcb_cache[3]; |
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static u32 bmr_cache; |
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static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128 }; |
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static u64 tc_get_cycles(struct clocksource *cs) |
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{ |
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unsigned long flags; |
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u32 lower, upper; |
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raw_local_irq_save(flags); |
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do { |
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upper = readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV)); |
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lower = readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV)); |
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} while (upper != readl_relaxed(tcaddr + ATMEL_TC_REG(1, CV))); |
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raw_local_irq_restore(flags); |
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return (upper << 16) | lower; |
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} |
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static u64 tc_get_cycles32(struct clocksource *cs) |
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{ |
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return readl_relaxed(tcaddr + ATMEL_TC_REG(0, CV)); |
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} |
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static void tc_clksrc_suspend(struct clocksource *cs) |
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{ |
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int i; |
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for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) { |
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tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR)); |
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tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR)); |
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tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC)); |
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tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) & |
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ATMEL_TC_CLKSTA); |
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} |
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bmr_cache = readl(tcaddr + ATMEL_TC_BMR); |
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} |
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static void tc_clksrc_resume(struct clocksource *cs) |
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{ |
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int i; |
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for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) { |
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/* Restore registers for the channel, RA and RB are not used */ |
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writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR)); |
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writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC)); |
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writel(0, tcaddr + ATMEL_TC_REG(i, RA)); |
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writel(0, tcaddr + ATMEL_TC_REG(i, RB)); |
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/* Disable all the interrupts */ |
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writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR)); |
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/* Reenable interrupts that were enabled before suspending */ |
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writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER)); |
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/* Start the clock if it was used */ |
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if (tcb_cache[i].clken) |
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writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR)); |
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} |
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/* Dual channel, chain channels */ |
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writel(bmr_cache, tcaddr + ATMEL_TC_BMR); |
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/* Finally, trigger all the channels*/ |
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writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); |
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} |
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static struct clocksource clksrc = { |
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.rating = 200, |
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.read = tc_get_cycles, |
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.mask = CLOCKSOURCE_MASK(32), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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.suspend = tc_clksrc_suspend, |
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.resume = tc_clksrc_resume, |
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}; |
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static u64 notrace tc_sched_clock_read(void) |
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{ |
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return tc_get_cycles(&clksrc); |
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} |
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static u64 notrace tc_sched_clock_read32(void) |
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{ |
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return tc_get_cycles32(&clksrc); |
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} |
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static struct delay_timer tc_delay_timer; |
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static unsigned long tc_delay_timer_read(void) |
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{ |
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return tc_get_cycles(&clksrc); |
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} |
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static unsigned long notrace tc_delay_timer_read32(void) |
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{ |
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return tc_get_cycles32(&clksrc); |
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} |
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#ifdef CONFIG_GENERIC_CLOCKEVENTS |
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struct tc_clkevt_device { |
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struct clock_event_device clkevt; |
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struct clk *clk; |
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u32 rate; |
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void __iomem *regs; |
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}; |
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static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt) |
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{ |
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return container_of(clkevt, struct tc_clkevt_device, clkevt); |
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} |
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static u32 timer_clock; |
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static int tc_shutdown(struct clock_event_device *d) |
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{ |
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struct tc_clkevt_device *tcd = to_tc_clkevt(d); |
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void __iomem *regs = tcd->regs; |
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writel(0xff, regs + ATMEL_TC_REG(2, IDR)); |
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writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); |
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if (!clockevent_state_detached(d)) |
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clk_disable(tcd->clk); |
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return 0; |
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} |
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static int tc_set_oneshot(struct clock_event_device *d) |
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{ |
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struct tc_clkevt_device *tcd = to_tc_clkevt(d); |
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void __iomem *regs = tcd->regs; |
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if (clockevent_state_oneshot(d) || clockevent_state_periodic(d)) |
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tc_shutdown(d); |
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clk_enable(tcd->clk); |
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/* count up to RC, then irq and stop */ |
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writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE | |
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ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR)); |
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writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); |
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/* set_next_event() configures and starts the timer */ |
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return 0; |
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} |
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static int tc_set_periodic(struct clock_event_device *d) |
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{ |
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struct tc_clkevt_device *tcd = to_tc_clkevt(d); |
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void __iomem *regs = tcd->regs; |
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if (clockevent_state_oneshot(d) || clockevent_state_periodic(d)) |
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tc_shutdown(d); |
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/* By not making the gentime core emulate periodic mode on top |
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* of oneshot, we get lower overhead and improved accuracy. |
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*/ |
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clk_enable(tcd->clk); |
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/* count up to RC, then irq and restart */ |
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writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO, |
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regs + ATMEL_TC_REG(2, CMR)); |
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writel((tcd->rate + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC)); |
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/* Enable clock and interrupts on RC compare */ |
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writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); |
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/* go go gadget! */ |
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writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, regs + |
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ATMEL_TC_REG(2, CCR)); |
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return 0; |
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} |
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static int tc_next_event(unsigned long delta, struct clock_event_device *d) |
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{ |
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writel_relaxed(delta, tcaddr + ATMEL_TC_REG(2, RC)); |
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/* go go gadget! */ |
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writel_relaxed(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, |
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tcaddr + ATMEL_TC_REG(2, CCR)); |
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return 0; |
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} |
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static struct tc_clkevt_device clkevt = { |
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.clkevt = { |
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.features = CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_ONESHOT, |
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/* Should be lower than at91rm9200's system timer */ |
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.rating = 125, |
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.set_next_event = tc_next_event, |
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.set_state_shutdown = tc_shutdown, |
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.set_state_periodic = tc_set_periodic, |
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.set_state_oneshot = tc_set_oneshot, |
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}, |
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}; |
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static irqreturn_t ch2_irq(int irq, void *handle) |
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{ |
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struct tc_clkevt_device *dev = handle; |
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unsigned int sr; |
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sr = readl_relaxed(dev->regs + ATMEL_TC_REG(2, SR)); |
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if (sr & ATMEL_TC_CPCS) { |
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dev->clkevt.event_handler(&dev->clkevt); |
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return IRQ_HANDLED; |
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} |
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return IRQ_NONE; |
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} |
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static int __init setup_clkevents(struct atmel_tc *tc, int divisor_idx) |
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{ |
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int ret; |
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struct clk *t2_clk = tc->clk[2]; |
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int irq = tc->irq[2]; |
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int bits = tc->tcb_config->counter_width; |
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/* try to enable t2 clk to avoid future errors in mode change */ |
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ret = clk_prepare_enable(t2_clk); |
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if (ret) |
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return ret; |
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clkevt.regs = tc->regs; |
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clkevt.clk = t2_clk; |
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if (bits == 32) { |
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timer_clock = divisor_idx; |
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clkevt.rate = clk_get_rate(t2_clk) / atmel_tcb_divisors[divisor_idx]; |
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} else { |
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ret = clk_prepare_enable(tc->slow_clk); |
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if (ret) { |
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clk_disable_unprepare(t2_clk); |
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return ret; |
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} |
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clkevt.rate = clk_get_rate(tc->slow_clk); |
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timer_clock = ATMEL_TC_TIMER_CLOCK5; |
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} |
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clk_disable(t2_clk); |
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clkevt.clkevt.cpumask = cpumask_of(0); |
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ret = request_irq(irq, ch2_irq, IRQF_TIMER, "tc_clkevt", &clkevt); |
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if (ret) { |
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clk_unprepare(t2_clk); |
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if (bits != 32) |
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clk_disable_unprepare(tc->slow_clk); |
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return ret; |
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} |
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clockevents_config_and_register(&clkevt.clkevt, clkevt.rate, 1, BIT(bits) - 1); |
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return ret; |
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} |
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#else /* !CONFIG_GENERIC_CLOCKEVENTS */ |
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static int __init setup_clkevents(struct atmel_tc *tc, int divisor_idx) |
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{ |
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/* NOTHING */ |
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return 0; |
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} |
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#endif |
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static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx) |
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{ |
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/* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */ |
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writel(mck_divisor_idx /* likely divide-by-8 */ |
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| ATMEL_TC_WAVE |
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| ATMEL_TC_WAVESEL_UP /* free-run */ |
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| ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */ |
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| ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */ |
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tcaddr + ATMEL_TC_REG(0, CMR)); |
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writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA)); |
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writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC)); |
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writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ |
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writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); |
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/* channel 1: waveform mode, input TIOA0 */ |
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writel(ATMEL_TC_XC1 /* input: TIOA0 */ |
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| ATMEL_TC_WAVE |
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| ATMEL_TC_WAVESEL_UP, /* free-run */ |
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tcaddr + ATMEL_TC_REG(1, CMR)); |
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writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */ |
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writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR)); |
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/* chain channel 0 to channel 1*/ |
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writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR); |
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/* then reset all the timers */ |
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writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); |
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} |
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static void __init tcb_setup_single_chan(struct atmel_tc *tc, int mck_divisor_idx) |
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{ |
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/* channel 0: waveform mode, input mclk/8 */ |
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writel(mck_divisor_idx /* likely divide-by-8 */ |
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| ATMEL_TC_WAVE |
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| ATMEL_TC_WAVESEL_UP, /* free-run */ |
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tcaddr + ATMEL_TC_REG(0, CMR)); |
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writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */ |
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writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR)); |
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/* then reset all the timers */ |
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writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR); |
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} |
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static struct atmel_tcb_config tcb_rm9200_config = { |
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.counter_width = 16, |
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}; |
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static struct atmel_tcb_config tcb_sam9x5_config = { |
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.counter_width = 32, |
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}; |
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static struct atmel_tcb_config tcb_sama5d2_config = { |
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.counter_width = 32, |
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.has_gclk = 1, |
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}; |
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static const struct of_device_id atmel_tcb_of_match[] = { |
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{ .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, }, |
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{ .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, }, |
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{ .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, }, |
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{ /* sentinel */ } |
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}; |
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static int __init tcb_clksrc_init(struct device_node *node) |
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{ |
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struct atmel_tc tc; |
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struct clk *t0_clk; |
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const struct of_device_id *match; |
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u64 (*tc_sched_clock)(void); |
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u32 rate, divided_rate = 0; |
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int best_divisor_idx = -1; |
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int bits; |
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int i; |
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int ret; |
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/* Protect against multiple calls */ |
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if (tcaddr) |
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return 0; |
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tc.regs = of_iomap(node->parent, 0); |
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if (!tc.regs) |
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return -ENXIO; |
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t0_clk = of_clk_get_by_name(node->parent, "t0_clk"); |
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if (IS_ERR(t0_clk)) |
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return PTR_ERR(t0_clk); |
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tc.slow_clk = of_clk_get_by_name(node->parent, "slow_clk"); |
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if (IS_ERR(tc.slow_clk)) |
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return PTR_ERR(tc.slow_clk); |
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tc.clk[0] = t0_clk; |
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tc.clk[1] = of_clk_get_by_name(node->parent, "t1_clk"); |
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if (IS_ERR(tc.clk[1])) |
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tc.clk[1] = t0_clk; |
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tc.clk[2] = of_clk_get_by_name(node->parent, "t2_clk"); |
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if (IS_ERR(tc.clk[2])) |
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tc.clk[2] = t0_clk; |
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tc.irq[2] = of_irq_get(node->parent, 2); |
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if (tc.irq[2] <= 0) { |
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tc.irq[2] = of_irq_get(node->parent, 0); |
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if (tc.irq[2] <= 0) |
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return -EINVAL; |
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} |
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match = of_match_node(atmel_tcb_of_match, node->parent); |
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if (!match) |
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return -ENODEV; |
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tc.tcb_config = match->data; |
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bits = tc.tcb_config->counter_width; |
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for (i = 0; i < ARRAY_SIZE(tc.irq); i++) |
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writel(ATMEL_TC_ALL_IRQ, tc.regs + ATMEL_TC_REG(i, IDR)); |
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ret = clk_prepare_enable(t0_clk); |
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if (ret) { |
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pr_debug("can't enable T0 clk\n"); |
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return ret; |
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} |
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/* How fast will we be counting? Pick something over 5 MHz. */ |
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rate = (u32) clk_get_rate(t0_clk); |
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i = 0; |
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if (tc.tcb_config->has_gclk) |
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i = 1; |
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for (; i < ARRAY_SIZE(atmel_tcb_divisors); i++) { |
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unsigned divisor = atmel_tcb_divisors[i]; |
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unsigned tmp; |
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tmp = rate / divisor; |
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pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp); |
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if ((best_divisor_idx >= 0) && (tmp < 5 * 1000 * 1000)) |
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break; |
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divided_rate = tmp; |
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best_divisor_idx = i; |
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} |
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clksrc.name = kbasename(node->parent->full_name); |
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clkevt.clkevt.name = kbasename(node->parent->full_name); |
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pr_debug("%s at %d.%03d MHz\n", clksrc.name, divided_rate / 1000000, |
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((divided_rate % 1000000) + 500) / 1000); |
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tcaddr = tc.regs; |
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if (bits == 32) { |
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/* use appropriate function to read 32 bit counter */ |
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clksrc.read = tc_get_cycles32; |
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/* setup only channel 0 */ |
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tcb_setup_single_chan(&tc, best_divisor_idx); |
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tc_sched_clock = tc_sched_clock_read32; |
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tc_delay_timer.read_current_timer = tc_delay_timer_read32; |
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} else { |
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/* we have three clocks no matter what the |
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* underlying platform supports. |
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*/ |
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ret = clk_prepare_enable(tc.clk[1]); |
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if (ret) { |
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pr_debug("can't enable T1 clk\n"); |
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goto err_disable_t0; |
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} |
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/* setup both channel 0 & 1 */ |
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tcb_setup_dual_chan(&tc, best_divisor_idx); |
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tc_sched_clock = tc_sched_clock_read; |
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tc_delay_timer.read_current_timer = tc_delay_timer_read; |
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} |
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/* and away we go! */ |
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ret = clocksource_register_hz(&clksrc, divided_rate); |
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if (ret) |
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goto err_disable_t1; |
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/* channel 2: periodic and oneshot timer support */ |
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ret = setup_clkevents(&tc, best_divisor_idx); |
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if (ret) |
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goto err_unregister_clksrc; |
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sched_clock_register(tc_sched_clock, 32, divided_rate); |
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tc_delay_timer.freq = divided_rate; |
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register_current_timer_delay(&tc_delay_timer); |
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return 0; |
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err_unregister_clksrc: |
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clocksource_unregister(&clksrc); |
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err_disable_t1: |
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if (bits != 32) |
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clk_disable_unprepare(tc.clk[1]); |
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err_disable_t0: |
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clk_disable_unprepare(t0_clk); |
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tcaddr = NULL; |
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return ret; |
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} |
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TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init);
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