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738 lines
21 KiB
738 lines
21 KiB
/* |
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* |
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* 3780i.c -- helper routines for the 3780i DSP |
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* |
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* |
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* Written By: Mike Sullivan IBM Corporation |
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* |
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* Copyright (C) 1999 IBM Corporation |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* NO WARRANTY |
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* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR |
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* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT |
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* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, |
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is |
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* solely responsible for determining the appropriateness of using and |
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* distributing the Program and assumes all risks associated with its |
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* exercise of rights under this Agreement, including but not limited to |
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* the risks and costs of program errors, damage to or loss of data, |
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* programs or equipment, and unavailability or interruption of operations. |
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* |
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* DISCLAIMER OF LIABILITY |
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* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY |
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND |
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR |
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE |
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* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED |
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* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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* |
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* |
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* 10/23/2000 - Alpha Release |
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* First release to the public |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/unistd.h> |
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#include <linux/delay.h> |
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#include <linux/ioport.h> |
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#include <linux/bitops.h> |
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#include <linux/sched.h> /* cond_resched() */ |
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#include <asm/io.h> |
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#include <linux/uaccess.h> |
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#include <asm/irq.h> |
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#include "smapi.h" |
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#include "mwavedd.h" |
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#include "3780i.h" |
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static DEFINE_SPINLOCK(dsp_lock); |
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static void PaceMsaAccess(unsigned short usDspBaseIO) |
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{ |
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cond_resched(); |
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udelay(100); |
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cond_resched(); |
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} |
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unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO, |
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unsigned long ulMsaAddr) |
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{ |
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unsigned long flags; |
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unsigned short val; |
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PRINTK_3(TRACE_3780I, |
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"3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx\n", |
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usDspBaseIO, ulMsaAddr); |
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spin_lock_irqsave(&dsp_lock, flags); |
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OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr); |
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OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16)); |
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val = InWordDsp(DSP_MsaDataDSISHigh); |
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spin_unlock_irqrestore(&dsp_lock, flags); |
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PRINTK_2(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val); |
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return val; |
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} |
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void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO, |
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unsigned long ulMsaAddr, unsigned short usValue) |
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{ |
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unsigned long flags; |
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PRINTK_4(TRACE_3780I, |
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"3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x\n", |
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usDspBaseIO, ulMsaAddr, usValue); |
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spin_lock_irqsave(&dsp_lock, flags); |
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OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr); |
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OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16)); |
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OutWordDsp(DSP_MsaDataDSISHigh, usValue); |
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spin_unlock_irqrestore(&dsp_lock, flags); |
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} |
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static void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex, |
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unsigned char ucValue) |
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{ |
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DSP_ISA_SLAVE_CONTROL rSlaveControl; |
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DSP_ISA_SLAVE_CONTROL rSlaveControl_Save; |
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PRINTK_4(TRACE_3780I, |
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"3780i::dsp3780i_WriteGenCfg entry usDspBaseIO %x uIndex %x ucValue %x\n", |
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usDspBaseIO, uIndex, ucValue); |
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MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl); |
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PRINTK_2(TRACE_3780I, |
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"3780i::dsp3780i_WriteGenCfg rSlaveControl %x\n", |
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MKBYTE(rSlaveControl)); |
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rSlaveControl_Save = rSlaveControl; |
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rSlaveControl.ConfigMode = true; |
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PRINTK_2(TRACE_3780I, |
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"3780i::dsp3780i_WriteGenCfg entry rSlaveControl+ConfigMode %x\n", |
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MKBYTE(rSlaveControl)); |
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OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl)); |
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OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex); |
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OutByteDsp(DSP_ConfigData, ucValue); |
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OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save)); |
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PRINTK_1(TRACE_3780I, "3780i::dsp3780i_WriteGenCfg exit\n"); |
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} |
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#if 0 |
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unsigned char dsp3780I_ReadGenCfg(unsigned short usDspBaseIO, |
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unsigned uIndex) |
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{ |
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DSP_ISA_SLAVE_CONTROL rSlaveControl; |
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DSP_ISA_SLAVE_CONTROL rSlaveControl_Save; |
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unsigned char ucValue; |
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PRINTK_3(TRACE_3780I, |
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"3780i::dsp3780i_ReadGenCfg entry usDspBaseIO %x uIndex %x\n", |
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usDspBaseIO, uIndex); |
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MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl); |
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rSlaveControl_Save = rSlaveControl; |
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rSlaveControl.ConfigMode = true; |
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OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl)); |
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OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex); |
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ucValue = InByteDsp(DSP_ConfigData); |
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OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save)); |
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PRINTK_2(TRACE_3780I, |
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"3780i::dsp3780i_ReadGenCfg exit ucValue %x\n", ucValue); |
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return ucValue; |
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} |
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#endif /* 0 */ |
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int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, |
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unsigned short *pIrqMap, |
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unsigned short *pDmaMap) |
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{ |
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unsigned long flags; |
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unsigned short usDspBaseIO = pSettings->usDspBaseIO; |
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int i; |
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DSP_UART_CFG_1 rUartCfg1; |
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DSP_UART_CFG_2 rUartCfg2; |
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DSP_HBRIDGE_CFG_1 rHBridgeCfg1; |
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DSP_HBRIDGE_CFG_2 rHBridgeCfg2; |
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DSP_BUSMASTER_CFG_1 rBusmasterCfg1; |
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DSP_BUSMASTER_CFG_2 rBusmasterCfg2; |
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DSP_ISA_PROT_CFG rIsaProtCfg; |
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DSP_POWER_MGMT_CFG rPowerMgmtCfg; |
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DSP_HBUS_TIMER_CFG rHBusTimerCfg; |
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DSP_LBUS_TIMEOUT_DISABLE rLBusTimeoutDisable; |
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DSP_CHIP_RESET rChipReset; |
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DSP_CLOCK_CONTROL_1 rClockControl1; |
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DSP_CLOCK_CONTROL_2 rClockControl2; |
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DSP_ISA_SLAVE_CONTROL rSlaveControl; |
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DSP_HBRIDGE_CONTROL rHBridgeControl; |
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unsigned short ChipID = 0; |
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unsigned short tval; |
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PRINTK_2(TRACE_3780I, |
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"3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x\n", |
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pSettings->bDSPEnabled); |
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if (!pSettings->bDSPEnabled) { |
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PRINTK_ERROR( KERN_ERR "3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" ); |
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return -EIO; |
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} |
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PRINTK_2(TRACE_3780I, |
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"3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x\n", |
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pSettings->bModemEnabled); |
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if (pSettings->bModemEnabled) { |
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rUartCfg1.Reserved = rUartCfg2.Reserved = 0; |
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rUartCfg1.IrqActiveLow = pSettings->bUartIrqActiveLow; |
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rUartCfg1.IrqPulse = pSettings->bUartIrqPulse; |
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rUartCfg1.Irq = |
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(unsigned char) pIrqMap[pSettings->usUartIrq]; |
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switch (pSettings->usUartBaseIO) { |
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case 0x03F8: |
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rUartCfg1.BaseIO = 0; |
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break; |
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case 0x02F8: |
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rUartCfg1.BaseIO = 1; |
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break; |
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case 0x03E8: |
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rUartCfg1.BaseIO = 2; |
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break; |
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case 0x02E8: |
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rUartCfg1.BaseIO = 3; |
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break; |
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} |
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rUartCfg2.Enable = true; |
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} |
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rHBridgeCfg1.Reserved = rHBridgeCfg2.Reserved = 0; |
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rHBridgeCfg1.IrqActiveLow = pSettings->bDspIrqActiveLow; |
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rHBridgeCfg1.IrqPulse = pSettings->bDspIrqPulse; |
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rHBridgeCfg1.Irq = (unsigned char) pIrqMap[pSettings->usDspIrq]; |
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rHBridgeCfg1.AccessMode = 1; |
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rHBridgeCfg2.Enable = true; |
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rBusmasterCfg2.Reserved = 0; |
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rBusmasterCfg1.Dma = (unsigned char) pDmaMap[pSettings->usDspDma]; |
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rBusmasterCfg1.NumTransfers = |
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(unsigned char) pSettings->usNumTransfers; |
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rBusmasterCfg1.ReRequest = (unsigned char) pSettings->usReRequest; |
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rBusmasterCfg1.MEMCS16 = pSettings->bEnableMEMCS16; |
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rBusmasterCfg2.IsaMemCmdWidth = |
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(unsigned char) pSettings->usIsaMemCmdWidth; |
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rIsaProtCfg.Reserved = 0; |
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rIsaProtCfg.GateIOCHRDY = pSettings->bGateIOCHRDY; |
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rPowerMgmtCfg.Reserved = 0; |
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rPowerMgmtCfg.Enable = pSettings->bEnablePwrMgmt; |
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rHBusTimerCfg.LoadValue = |
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(unsigned char) pSettings->usHBusTimerLoadValue; |
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rLBusTimeoutDisable.Reserved = 0; |
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rLBusTimeoutDisable.DisableTimeout = |
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pSettings->bDisableLBusTimeout; |
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MKWORD(rChipReset) = ~pSettings->usChipletEnable; |
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rClockControl1.Reserved1 = rClockControl1.Reserved2 = 0; |
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rClockControl1.N_Divisor = pSettings->usN_Divisor; |
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rClockControl1.M_Multiplier = pSettings->usM_Multiplier; |
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rClockControl2.Reserved = 0; |
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rClockControl2.PllBypass = pSettings->bPllBypass; |
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/* Issue a soft reset to the chip */ |
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/* Note: Since we may be coming in with 3780i clocks suspended, we must keep |
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* soft-reset active for 10ms. |
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*/ |
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rSlaveControl.ClockControl = 0; |
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rSlaveControl.SoftReset = true; |
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rSlaveControl.ConfigMode = false; |
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rSlaveControl.Reserved = 0; |
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PRINTK_4(TRACE_3780I, |
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"3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x\n", |
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usDspBaseIO, DSP_IsaSlaveControl, |
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usDspBaseIO + DSP_IsaSlaveControl); |
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PRINTK_2(TRACE_3780I, |
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"3780i::dsp3780i_EnableDSP rSlaveContrl %x\n", |
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MKWORD(rSlaveControl)); |
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spin_lock_irqsave(&dsp_lock, flags); |
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OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); |
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MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl); |
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PRINTK_2(TRACE_3780I, |
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"3780i::dsp3780i_EnableDSP rSlaveControl 2 %x\n", tval); |
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for (i = 0; i < 11; i++) |
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udelay(2000); |
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rSlaveControl.SoftReset = false; |
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OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); |
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MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl); |
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PRINTK_2(TRACE_3780I, |
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"3780i::dsp3780i_EnableDSP rSlaveControl 3 %x\n", tval); |
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/* Program our general configuration registers */ |
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WriteGenCfg(DSP_HBridgeCfg1Index, MKBYTE(rHBridgeCfg1)); |
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WriteGenCfg(DSP_HBridgeCfg2Index, MKBYTE(rHBridgeCfg2)); |
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WriteGenCfg(DSP_BusMasterCfg1Index, MKBYTE(rBusmasterCfg1)); |
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WriteGenCfg(DSP_BusMasterCfg2Index, MKBYTE(rBusmasterCfg2)); |
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WriteGenCfg(DSP_IsaProtCfgIndex, MKBYTE(rIsaProtCfg)); |
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WriteGenCfg(DSP_PowerMgCfgIndex, MKBYTE(rPowerMgmtCfg)); |
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WriteGenCfg(DSP_HBusTimerCfgIndex, MKBYTE(rHBusTimerCfg)); |
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if (pSettings->bModemEnabled) { |
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WriteGenCfg(DSP_UartCfg1Index, MKBYTE(rUartCfg1)); |
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WriteGenCfg(DSP_UartCfg2Index, MKBYTE(rUartCfg2)); |
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} |
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rHBridgeControl.EnableDspInt = false; |
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rHBridgeControl.MemAutoInc = true; |
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rHBridgeControl.IoAutoInc = false; |
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rHBridgeControl.DiagnosticMode = false; |
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PRINTK_3(TRACE_3780I, |
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"3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x\n", |
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DSP_HBridgeControl, MKWORD(rHBridgeControl)); |
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OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); |
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spin_unlock_irqrestore(&dsp_lock, flags); |
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WriteMsaCfg(DSP_LBusTimeoutDisable, MKWORD(rLBusTimeoutDisable)); |
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WriteMsaCfg(DSP_ClockControl_1, MKWORD(rClockControl1)); |
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WriteMsaCfg(DSP_ClockControl_2, MKWORD(rClockControl2)); |
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WriteMsaCfg(DSP_ChipReset, MKWORD(rChipReset)); |
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ChipID = ReadMsaCfg(DSP_ChipID); |
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PRINTK_2(TRACE_3780I, |
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"3780i::dsp3780I_EnableDSP exiting bRC=true, ChipID %x\n", |
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ChipID); |
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return 0; |
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} |
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int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings) |
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{ |
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unsigned long flags; |
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unsigned short usDspBaseIO = pSettings->usDspBaseIO; |
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DSP_ISA_SLAVE_CONTROL rSlaveControl; |
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PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP entry\n"); |
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rSlaveControl.ClockControl = 0; |
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rSlaveControl.SoftReset = true; |
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rSlaveControl.ConfigMode = false; |
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rSlaveControl.Reserved = 0; |
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spin_lock_irqsave(&dsp_lock, flags); |
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OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); |
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udelay(5); |
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rSlaveControl.ClockControl = 1; |
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OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); |
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spin_unlock_irqrestore(&dsp_lock, flags); |
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udelay(5); |
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PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP exit\n"); |
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return 0; |
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} |
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int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings) |
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{ |
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unsigned long flags; |
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unsigned short usDspBaseIO = pSettings->usDspBaseIO; |
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DSP_BOOT_DOMAIN rBootDomain; |
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DSP_HBRIDGE_CONTROL rHBridgeControl; |
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PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset entry\n"); |
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spin_lock_irqsave(&dsp_lock, flags); |
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/* Mask DSP to PC interrupt */ |
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MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); |
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PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rHBridgeControl %x\n", |
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MKWORD(rHBridgeControl)); |
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rHBridgeControl.EnableDspInt = false; |
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OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); |
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spin_unlock_irqrestore(&dsp_lock, flags); |
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/* Reset the core via the boot domain register */ |
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rBootDomain.ResetCore = true; |
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rBootDomain.Halt = true; |
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rBootDomain.NMI = true; |
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rBootDomain.Reserved = 0; |
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PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rBootDomain %x\n", |
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MKWORD(rBootDomain)); |
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WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); |
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/* Reset all the chiplets and then reactivate them */ |
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WriteMsaCfg(DSP_ChipReset, 0xFFFF); |
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udelay(5); |
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WriteMsaCfg(DSP_ChipReset, |
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(unsigned short) (~pSettings->usChipletEnable)); |
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PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset exit bRC=0\n"); |
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return 0; |
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} |
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int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings) |
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{ |
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unsigned long flags; |
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unsigned short usDspBaseIO = pSettings->usDspBaseIO; |
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DSP_BOOT_DOMAIN rBootDomain; |
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DSP_HBRIDGE_CONTROL rHBridgeControl; |
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PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run entry\n"); |
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/* Transition the core to a running state */ |
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rBootDomain.ResetCore = true; |
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rBootDomain.Halt = false; |
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rBootDomain.NMI = true; |
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rBootDomain.Reserved = 0; |
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WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); |
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udelay(5); |
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rBootDomain.ResetCore = false; |
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WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); |
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udelay(5); |
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rBootDomain.NMI = false; |
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WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); |
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udelay(5); |
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/* Enable DSP to PC interrupt */ |
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spin_lock_irqsave(&dsp_lock, flags); |
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MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); |
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rHBridgeControl.EnableDspInt = true; |
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PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Run rHBridgeControl %x\n", |
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MKWORD(rHBridgeControl)); |
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OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); |
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spin_unlock_irqrestore(&dsp_lock, flags); |
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PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run exit bRC=true\n"); |
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return 0; |
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} |
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int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer, |
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unsigned uCount, unsigned long ulDSPAddr) |
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{ |
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unsigned long flags; |
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unsigned short __user *pusBuffer = pvBuffer; |
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unsigned short val; |
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PRINTK_5(TRACE_3780I, |
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"3780i::dsp3780I_ReadDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", |
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usDspBaseIO, pusBuffer, uCount, ulDSPAddr); |
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/* Set the initial MSA address. No adjustments need to be made to data store addresses */ |
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spin_lock_irqsave(&dsp_lock, flags); |
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OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); |
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OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); |
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spin_unlock_irqrestore(&dsp_lock, flags); |
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|
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/* Transfer the memory block */ |
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while (uCount-- != 0) { |
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spin_lock_irqsave(&dsp_lock, flags); |
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val = InWordDsp(DSP_MsaDataDSISHigh); |
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spin_unlock_irqrestore(&dsp_lock, flags); |
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if(put_user(val, pusBuffer++)) |
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return -EFAULT; |
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|
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PRINTK_3(TRACE_3780I, |
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"3780I::dsp3780I_ReadDStore uCount %x val %x\n", |
|
uCount, val); |
|
|
|
PaceMsaAccess(usDspBaseIO); |
|
} |
|
|
|
|
|
PRINTK_1(TRACE_3780I, |
|
"3780I::dsp3780I_ReadDStore exit bRC=true\n"); |
|
|
|
return 0; |
|
} |
|
|
|
int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO, |
|
void __user *pvBuffer, unsigned uCount, |
|
unsigned long ulDSPAddr) |
|
{ |
|
unsigned long flags; |
|
unsigned short __user *pusBuffer = pvBuffer; |
|
unsigned short val; |
|
|
|
|
|
PRINTK_5(TRACE_3780I, |
|
"3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", |
|
usDspBaseIO, pusBuffer, uCount, ulDSPAddr); |
|
|
|
|
|
/* Set the initial MSA address. No adjustments need to be made to data store addresses */ |
|
spin_lock_irqsave(&dsp_lock, flags); |
|
OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); |
|
OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); |
|
spin_unlock_irqrestore(&dsp_lock, flags); |
|
|
|
/* Transfer the memory block */ |
|
while (uCount-- != 0) { |
|
spin_lock_irqsave(&dsp_lock, flags); |
|
val = InWordDsp(DSP_ReadAndClear); |
|
spin_unlock_irqrestore(&dsp_lock, flags); |
|
if(put_user(val, pusBuffer++)) |
|
return -EFAULT; |
|
|
|
PRINTK_3(TRACE_3780I, |
|
"3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x\n", |
|
uCount, val); |
|
|
|
PaceMsaAccess(usDspBaseIO); |
|
} |
|
|
|
|
|
PRINTK_1(TRACE_3780I, |
|
"3780I::dsp3780I_ReadAndClearDStore exit bRC=true\n"); |
|
|
|
return 0; |
|
} |
|
|
|
|
|
int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer, |
|
unsigned uCount, unsigned long ulDSPAddr) |
|
{ |
|
unsigned long flags; |
|
unsigned short __user *pusBuffer = pvBuffer; |
|
|
|
|
|
PRINTK_5(TRACE_3780I, |
|
"3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", |
|
usDspBaseIO, pusBuffer, uCount, ulDSPAddr); |
|
|
|
|
|
/* Set the initial MSA address. No adjustments need to be made to data store addresses */ |
|
spin_lock_irqsave(&dsp_lock, flags); |
|
OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); |
|
OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); |
|
spin_unlock_irqrestore(&dsp_lock, flags); |
|
|
|
/* Transfer the memory block */ |
|
while (uCount-- != 0) { |
|
unsigned short val; |
|
if(get_user(val, pusBuffer++)) |
|
return -EFAULT; |
|
spin_lock_irqsave(&dsp_lock, flags); |
|
OutWordDsp(DSP_MsaDataDSISHigh, val); |
|
spin_unlock_irqrestore(&dsp_lock, flags); |
|
|
|
PRINTK_3(TRACE_3780I, |
|
"3780I::dsp3780I_WriteDStore uCount %x val %x\n", |
|
uCount, val); |
|
|
|
PaceMsaAccess(usDspBaseIO); |
|
} |
|
|
|
|
|
PRINTK_1(TRACE_3780I, |
|
"3780I::dsp3780D_WriteDStore exit bRC=true\n"); |
|
|
|
return 0; |
|
} |
|
|
|
|
|
int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer, |
|
unsigned uCount, unsigned long ulDSPAddr) |
|
{ |
|
unsigned long flags; |
|
unsigned short __user *pusBuffer = pvBuffer; |
|
|
|
PRINTK_5(TRACE_3780I, |
|
"3780i::dsp3780I_ReadIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", |
|
usDspBaseIO, pusBuffer, uCount, ulDSPAddr); |
|
|
|
/* |
|
* Set the initial MSA address. To convert from an instruction store |
|
* address to an MSA address |
|
* shift the address two bits to the left and set bit 22 |
|
*/ |
|
ulDSPAddr = (ulDSPAddr << 2) | (1 << 22); |
|
spin_lock_irqsave(&dsp_lock, flags); |
|
OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); |
|
OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); |
|
spin_unlock_irqrestore(&dsp_lock, flags); |
|
|
|
/* Transfer the memory block */ |
|
while (uCount-- != 0) { |
|
unsigned short val_lo, val_hi; |
|
spin_lock_irqsave(&dsp_lock, flags); |
|
val_lo = InWordDsp(DSP_MsaDataISLow); |
|
val_hi = InWordDsp(DSP_MsaDataDSISHigh); |
|
spin_unlock_irqrestore(&dsp_lock, flags); |
|
if(put_user(val_lo, pusBuffer++)) |
|
return -EFAULT; |
|
if(put_user(val_hi, pusBuffer++)) |
|
return -EFAULT; |
|
|
|
PRINTK_4(TRACE_3780I, |
|
"3780I::dsp3780I_ReadIStore uCount %x val_lo %x val_hi %x\n", |
|
uCount, val_lo, val_hi); |
|
|
|
PaceMsaAccess(usDspBaseIO); |
|
|
|
} |
|
|
|
PRINTK_1(TRACE_3780I, |
|
"3780I::dsp3780I_ReadIStore exit bRC=true\n"); |
|
|
|
return 0; |
|
} |
|
|
|
|
|
int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer, |
|
unsigned uCount, unsigned long ulDSPAddr) |
|
{ |
|
unsigned long flags; |
|
unsigned short __user *pusBuffer = pvBuffer; |
|
|
|
PRINTK_5(TRACE_3780I, |
|
"3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", |
|
usDspBaseIO, pusBuffer, uCount, ulDSPAddr); |
|
|
|
|
|
/* |
|
* Set the initial MSA address. To convert from an instruction store |
|
* address to an MSA address |
|
* shift the address two bits to the left and set bit 22 |
|
*/ |
|
ulDSPAddr = (ulDSPAddr << 2) | (1 << 22); |
|
spin_lock_irqsave(&dsp_lock, flags); |
|
OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); |
|
OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); |
|
spin_unlock_irqrestore(&dsp_lock, flags); |
|
|
|
/* Transfer the memory block */ |
|
while (uCount-- != 0) { |
|
unsigned short val_lo, val_hi; |
|
if(get_user(val_lo, pusBuffer++)) |
|
return -EFAULT; |
|
if(get_user(val_hi, pusBuffer++)) |
|
return -EFAULT; |
|
spin_lock_irqsave(&dsp_lock, flags); |
|
OutWordDsp(DSP_MsaDataISLow, val_lo); |
|
OutWordDsp(DSP_MsaDataDSISHigh, val_hi); |
|
spin_unlock_irqrestore(&dsp_lock, flags); |
|
|
|
PRINTK_4(TRACE_3780I, |
|
"3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n", |
|
uCount, val_lo, val_hi); |
|
|
|
PaceMsaAccess(usDspBaseIO); |
|
|
|
} |
|
|
|
PRINTK_1(TRACE_3780I, |
|
"3780I::dsp3780I_WriteIStore exit bRC=true\n"); |
|
|
|
return 0; |
|
} |
|
|
|
|
|
int dsp3780I_GetIPCSource(unsigned short usDspBaseIO, |
|
unsigned short *pusIPCSource) |
|
{ |
|
unsigned long flags; |
|
DSP_HBRIDGE_CONTROL rHBridgeControl; |
|
unsigned short temp; |
|
|
|
|
|
PRINTK_3(TRACE_3780I, |
|
"3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p\n", |
|
usDspBaseIO, pusIPCSource); |
|
|
|
/* |
|
* Disable DSP to PC interrupts, read the interrupt register, |
|
* clear the pending IPC bits, and reenable DSP to PC interrupts |
|
*/ |
|
spin_lock_irqsave(&dsp_lock, flags); |
|
MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); |
|
rHBridgeControl.EnableDspInt = false; |
|
OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); |
|
|
|
*pusIPCSource = InWordDsp(DSP_Interrupt); |
|
temp = (unsigned short) ~(*pusIPCSource); |
|
|
|
PRINTK_3(TRACE_3780I, |
|
"3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x\n", |
|
*pusIPCSource, temp); |
|
|
|
OutWordDsp(DSP_Interrupt, (unsigned short) ~(*pusIPCSource)); |
|
|
|
rHBridgeControl.EnableDspInt = true; |
|
OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); |
|
spin_unlock_irqrestore(&dsp_lock, flags); |
|
|
|
|
|
PRINTK_2(TRACE_3780I, |
|
"3780i::dsp3780I_GetIPCSource exit usIPCSource %x\n", |
|
*pusIPCSource); |
|
|
|
return 0; |
|
}
|
|
|