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585 lines
16 KiB
585 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* ipmi_smic_sm.c |
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* |
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* The state-machine driver for an IPMI SMIC driver |
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* |
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* It started as a copy of Corey Minyard's driver for the KSC interface |
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* and the kernel patch "mmcdev-patch-245" by HP |
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* |
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* modified by: Hannes Schulz <[email protected]> |
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* [email protected] |
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* |
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* |
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* Corey Minyard's driver for the KSC interface has the following |
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* copyright notice: |
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* Copyright 2002 MontaVista Software Inc. |
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* |
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* the kernel patch "mmcdev-patch-245" by HP has the following |
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* copyright notice: |
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* (c) Copyright 2001 Grant Grundler (c) Copyright |
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* 2001 Hewlett-Packard Company |
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*/ |
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|
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#define DEBUG /* So dev_dbg() is always available. */ |
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|
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#include <linux/kernel.h> /* For printk. */ |
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#include <linux/string.h> |
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#include <linux/module.h> |
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#include <linux/moduleparam.h> |
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#include <linux/ipmi_msgdefs.h> /* for completion codes */ |
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#include "ipmi_si_sm.h" |
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|
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/* smic_debug is a bit-field |
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* SMIC_DEBUG_ENABLE - turned on for now |
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* SMIC_DEBUG_MSG - commands and their responses |
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* SMIC_DEBUG_STATES - state machine |
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*/ |
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#define SMIC_DEBUG_STATES 4 |
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#define SMIC_DEBUG_MSG 2 |
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#define SMIC_DEBUG_ENABLE 1 |
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static int smic_debug = 1; |
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module_param(smic_debug, int, 0644); |
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MODULE_PARM_DESC(smic_debug, "debug bitmask, 1=enable, 2=messages, 4=states"); |
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enum smic_states { |
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SMIC_IDLE, |
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SMIC_START_OP, |
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SMIC_OP_OK, |
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SMIC_WRITE_START, |
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SMIC_WRITE_NEXT, |
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SMIC_WRITE_END, |
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SMIC_WRITE2READ, |
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SMIC_READ_START, |
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SMIC_READ_NEXT, |
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SMIC_READ_END, |
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SMIC_HOSED |
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}; |
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#define MAX_SMIC_READ_SIZE 80 |
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#define MAX_SMIC_WRITE_SIZE 80 |
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#define SMIC_MAX_ERROR_RETRIES 3 |
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|
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/* Timeouts in microseconds. */ |
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#define SMIC_RETRY_TIMEOUT (2*USEC_PER_SEC) |
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|
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/* SMIC Flags Register Bits */ |
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#define SMIC_RX_DATA_READY 0x80 |
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#define SMIC_TX_DATA_READY 0x40 |
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/* |
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* SMIC_SMI and SMIC_EVM_DATA_AVAIL are only used by |
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* a few systems, and then only by Systems Management |
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* Interrupts, not by the OS. Always ignore these bits. |
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* |
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*/ |
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#define SMIC_SMI 0x10 |
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#define SMIC_EVM_DATA_AVAIL 0x08 |
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#define SMIC_SMS_DATA_AVAIL 0x04 |
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#define SMIC_FLAG_BSY 0x01 |
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|
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/* SMIC Error Codes */ |
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#define EC_NO_ERROR 0x00 |
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#define EC_ABORTED 0x01 |
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#define EC_ILLEGAL_CONTROL 0x02 |
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#define EC_NO_RESPONSE 0x03 |
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#define EC_ILLEGAL_COMMAND 0x04 |
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#define EC_BUFFER_FULL 0x05 |
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struct si_sm_data { |
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enum smic_states state; |
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struct si_sm_io *io; |
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unsigned char write_data[MAX_SMIC_WRITE_SIZE]; |
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int write_pos; |
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int write_count; |
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int orig_write_count; |
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unsigned char read_data[MAX_SMIC_READ_SIZE]; |
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int read_pos; |
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int truncated; |
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unsigned int error_retries; |
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long smic_timeout; |
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}; |
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static unsigned int init_smic_data(struct si_sm_data *smic, |
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struct si_sm_io *io) |
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{ |
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smic->state = SMIC_IDLE; |
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smic->io = io; |
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smic->write_pos = 0; |
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smic->write_count = 0; |
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smic->orig_write_count = 0; |
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smic->read_pos = 0; |
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smic->error_retries = 0; |
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smic->truncated = 0; |
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smic->smic_timeout = SMIC_RETRY_TIMEOUT; |
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/* We use 3 bytes of I/O. */ |
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return 3; |
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} |
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static int start_smic_transaction(struct si_sm_data *smic, |
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unsigned char *data, unsigned int size) |
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{ |
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unsigned int i; |
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if (size < 2) |
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return IPMI_REQ_LEN_INVALID_ERR; |
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if (size > MAX_SMIC_WRITE_SIZE) |
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return IPMI_REQ_LEN_EXCEEDED_ERR; |
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if ((smic->state != SMIC_IDLE) && (smic->state != SMIC_HOSED)) { |
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dev_warn(smic->io->dev, |
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"SMIC in invalid state %d\n", smic->state); |
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return IPMI_NOT_IN_MY_STATE_ERR; |
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} |
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if (smic_debug & SMIC_DEBUG_MSG) { |
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dev_dbg(smic->io->dev, "%s -", __func__); |
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for (i = 0; i < size; i++) |
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pr_cont(" %02x", data[i]); |
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pr_cont("\n"); |
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} |
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smic->error_retries = 0; |
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memcpy(smic->write_data, data, size); |
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smic->write_count = size; |
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smic->orig_write_count = size; |
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smic->write_pos = 0; |
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smic->read_pos = 0; |
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smic->state = SMIC_START_OP; |
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smic->smic_timeout = SMIC_RETRY_TIMEOUT; |
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return 0; |
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} |
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static int smic_get_result(struct si_sm_data *smic, |
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unsigned char *data, unsigned int length) |
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{ |
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int i; |
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if (smic_debug & SMIC_DEBUG_MSG) { |
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dev_dbg(smic->io->dev, "smic_get result -"); |
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for (i = 0; i < smic->read_pos; i++) |
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pr_cont(" %02x", smic->read_data[i]); |
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pr_cont("\n"); |
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} |
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if (length < smic->read_pos) { |
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smic->read_pos = length; |
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smic->truncated = 1; |
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} |
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memcpy(data, smic->read_data, smic->read_pos); |
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if ((length >= 3) && (smic->read_pos < 3)) { |
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data[2] = IPMI_ERR_UNSPECIFIED; |
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smic->read_pos = 3; |
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} |
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if (smic->truncated) { |
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data[2] = IPMI_ERR_MSG_TRUNCATED; |
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smic->truncated = 0; |
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} |
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return smic->read_pos; |
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} |
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static inline unsigned char read_smic_flags(struct si_sm_data *smic) |
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{ |
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return smic->io->inputb(smic->io, 2); |
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} |
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static inline unsigned char read_smic_status(struct si_sm_data *smic) |
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{ |
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return smic->io->inputb(smic->io, 1); |
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} |
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static inline unsigned char read_smic_data(struct si_sm_data *smic) |
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{ |
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return smic->io->inputb(smic->io, 0); |
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} |
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static inline void write_smic_flags(struct si_sm_data *smic, |
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unsigned char flags) |
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{ |
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smic->io->outputb(smic->io, 2, flags); |
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} |
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static inline void write_smic_control(struct si_sm_data *smic, |
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unsigned char control) |
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{ |
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smic->io->outputb(smic->io, 1, control); |
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} |
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static inline void write_si_sm_data(struct si_sm_data *smic, |
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unsigned char data) |
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{ |
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smic->io->outputb(smic->io, 0, data); |
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} |
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static inline void start_error_recovery(struct si_sm_data *smic, char *reason) |
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{ |
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(smic->error_retries)++; |
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if (smic->error_retries > SMIC_MAX_ERROR_RETRIES) { |
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if (smic_debug & SMIC_DEBUG_ENABLE) |
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pr_warn("ipmi_smic_drv: smic hosed: %s\n", reason); |
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smic->state = SMIC_HOSED; |
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} else { |
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smic->write_count = smic->orig_write_count; |
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smic->write_pos = 0; |
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smic->read_pos = 0; |
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smic->state = SMIC_START_OP; |
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smic->smic_timeout = SMIC_RETRY_TIMEOUT; |
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} |
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} |
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static inline void write_next_byte(struct si_sm_data *smic) |
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{ |
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write_si_sm_data(smic, smic->write_data[smic->write_pos]); |
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(smic->write_pos)++; |
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(smic->write_count)--; |
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} |
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static inline void read_next_byte(struct si_sm_data *smic) |
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{ |
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if (smic->read_pos >= MAX_SMIC_READ_SIZE) { |
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read_smic_data(smic); |
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smic->truncated = 1; |
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} else { |
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smic->read_data[smic->read_pos] = read_smic_data(smic); |
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smic->read_pos++; |
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} |
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} |
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/* SMIC Control/Status Code Components */ |
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#define SMIC_GET_STATUS 0x00 /* Control form's name */ |
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#define SMIC_READY 0x00 /* Status form's name */ |
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#define SMIC_WR_START 0x01 /* Unified Control/Status names... */ |
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#define SMIC_WR_NEXT 0x02 |
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#define SMIC_WR_END 0x03 |
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#define SMIC_RD_START 0x04 |
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#define SMIC_RD_NEXT 0x05 |
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#define SMIC_RD_END 0x06 |
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#define SMIC_CODE_MASK 0x0f |
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#define SMIC_CONTROL 0x00 |
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#define SMIC_STATUS 0x80 |
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#define SMIC_CS_MASK 0x80 |
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#define SMIC_SMS 0x40 |
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#define SMIC_SMM 0x60 |
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#define SMIC_STREAM_MASK 0x60 |
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|
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/* SMIC Control Codes */ |
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#define SMIC_CC_SMS_GET_STATUS (SMIC_CONTROL|SMIC_SMS|SMIC_GET_STATUS) |
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#define SMIC_CC_SMS_WR_START (SMIC_CONTROL|SMIC_SMS|SMIC_WR_START) |
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#define SMIC_CC_SMS_WR_NEXT (SMIC_CONTROL|SMIC_SMS|SMIC_WR_NEXT) |
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#define SMIC_CC_SMS_WR_END (SMIC_CONTROL|SMIC_SMS|SMIC_WR_END) |
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#define SMIC_CC_SMS_RD_START (SMIC_CONTROL|SMIC_SMS|SMIC_RD_START) |
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#define SMIC_CC_SMS_RD_NEXT (SMIC_CONTROL|SMIC_SMS|SMIC_RD_NEXT) |
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#define SMIC_CC_SMS_RD_END (SMIC_CONTROL|SMIC_SMS|SMIC_RD_END) |
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#define SMIC_CC_SMM_GET_STATUS (SMIC_CONTROL|SMIC_SMM|SMIC_GET_STATUS) |
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#define SMIC_CC_SMM_WR_START (SMIC_CONTROL|SMIC_SMM|SMIC_WR_START) |
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#define SMIC_CC_SMM_WR_NEXT (SMIC_CONTROL|SMIC_SMM|SMIC_WR_NEXT) |
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#define SMIC_CC_SMM_WR_END (SMIC_CONTROL|SMIC_SMM|SMIC_WR_END) |
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#define SMIC_CC_SMM_RD_START (SMIC_CONTROL|SMIC_SMM|SMIC_RD_START) |
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#define SMIC_CC_SMM_RD_NEXT (SMIC_CONTROL|SMIC_SMM|SMIC_RD_NEXT) |
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#define SMIC_CC_SMM_RD_END (SMIC_CONTROL|SMIC_SMM|SMIC_RD_END) |
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|
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/* SMIC Status Codes */ |
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#define SMIC_SC_SMS_READY (SMIC_STATUS|SMIC_SMS|SMIC_READY) |
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#define SMIC_SC_SMS_WR_START (SMIC_STATUS|SMIC_SMS|SMIC_WR_START) |
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#define SMIC_SC_SMS_WR_NEXT (SMIC_STATUS|SMIC_SMS|SMIC_WR_NEXT) |
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#define SMIC_SC_SMS_WR_END (SMIC_STATUS|SMIC_SMS|SMIC_WR_END) |
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#define SMIC_SC_SMS_RD_START (SMIC_STATUS|SMIC_SMS|SMIC_RD_START) |
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#define SMIC_SC_SMS_RD_NEXT (SMIC_STATUS|SMIC_SMS|SMIC_RD_NEXT) |
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#define SMIC_SC_SMS_RD_END (SMIC_STATUS|SMIC_SMS|SMIC_RD_END) |
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#define SMIC_SC_SMM_READY (SMIC_STATUS|SMIC_SMM|SMIC_READY) |
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#define SMIC_SC_SMM_WR_START (SMIC_STATUS|SMIC_SMM|SMIC_WR_START) |
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#define SMIC_SC_SMM_WR_NEXT (SMIC_STATUS|SMIC_SMM|SMIC_WR_NEXT) |
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#define SMIC_SC_SMM_WR_END (SMIC_STATUS|SMIC_SMM|SMIC_WR_END) |
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#define SMIC_SC_SMM_RD_START (SMIC_STATUS|SMIC_SMM|SMIC_RD_START) |
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#define SMIC_SC_SMM_RD_NEXT (SMIC_STATUS|SMIC_SMM|SMIC_RD_NEXT) |
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#define SMIC_SC_SMM_RD_END (SMIC_STATUS|SMIC_SMM|SMIC_RD_END) |
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|
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/* these are the control/status codes we actually use |
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SMIC_CC_SMS_GET_STATUS 0x40 |
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SMIC_CC_SMS_WR_START 0x41 |
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SMIC_CC_SMS_WR_NEXT 0x42 |
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SMIC_CC_SMS_WR_END 0x43 |
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SMIC_CC_SMS_RD_START 0x44 |
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SMIC_CC_SMS_RD_NEXT 0x45 |
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SMIC_CC_SMS_RD_END 0x46 |
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SMIC_SC_SMS_READY 0xC0 |
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SMIC_SC_SMS_WR_START 0xC1 |
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SMIC_SC_SMS_WR_NEXT 0xC2 |
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SMIC_SC_SMS_WR_END 0xC3 |
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SMIC_SC_SMS_RD_START 0xC4 |
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SMIC_SC_SMS_RD_NEXT 0xC5 |
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SMIC_SC_SMS_RD_END 0xC6 |
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*/ |
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static enum si_sm_result smic_event(struct si_sm_data *smic, long time) |
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{ |
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unsigned char status; |
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unsigned char flags; |
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unsigned char data; |
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if (smic->state == SMIC_HOSED) { |
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init_smic_data(smic, smic->io); |
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return SI_SM_HOSED; |
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} |
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if (smic->state != SMIC_IDLE) { |
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if (smic_debug & SMIC_DEBUG_STATES) |
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dev_dbg(smic->io->dev, |
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"%s - smic->smic_timeout = %ld, time = %ld\n", |
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__func__, smic->smic_timeout, time); |
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/* |
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* FIXME: smic_event is sometimes called with time > |
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* SMIC_RETRY_TIMEOUT |
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*/ |
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if (time < SMIC_RETRY_TIMEOUT) { |
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smic->smic_timeout -= time; |
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if (smic->smic_timeout < 0) { |
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start_error_recovery(smic, "smic timed out."); |
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return SI_SM_CALL_WITH_DELAY; |
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} |
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} |
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} |
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flags = read_smic_flags(smic); |
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if (flags & SMIC_FLAG_BSY) |
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return SI_SM_CALL_WITH_DELAY; |
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status = read_smic_status(smic); |
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if (smic_debug & SMIC_DEBUG_STATES) |
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dev_dbg(smic->io->dev, |
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"%s - state = %d, flags = 0x%02x, status = 0x%02x\n", |
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__func__, smic->state, flags, status); |
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switch (smic->state) { |
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case SMIC_IDLE: |
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/* in IDLE we check for available messages */ |
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if (flags & SMIC_SMS_DATA_AVAIL) |
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return SI_SM_ATTN; |
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return SI_SM_IDLE; |
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case SMIC_START_OP: |
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/* sanity check whether smic is really idle */ |
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write_smic_control(smic, SMIC_CC_SMS_GET_STATUS); |
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write_smic_flags(smic, flags | SMIC_FLAG_BSY); |
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smic->state = SMIC_OP_OK; |
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break; |
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case SMIC_OP_OK: |
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if (status != SMIC_SC_SMS_READY) { |
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/* this should not happen */ |
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start_error_recovery(smic, |
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"state = SMIC_OP_OK," |
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" status != SMIC_SC_SMS_READY"); |
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return SI_SM_CALL_WITH_DELAY; |
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} |
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/* OK so far; smic is idle let us start ... */ |
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write_smic_control(smic, SMIC_CC_SMS_WR_START); |
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write_next_byte(smic); |
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write_smic_flags(smic, flags | SMIC_FLAG_BSY); |
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smic->state = SMIC_WRITE_START; |
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break; |
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|
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case SMIC_WRITE_START: |
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if (status != SMIC_SC_SMS_WR_START) { |
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start_error_recovery(smic, |
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"state = SMIC_WRITE_START, " |
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"status != SMIC_SC_SMS_WR_START"); |
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return SI_SM_CALL_WITH_DELAY; |
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} |
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/* |
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* we must not issue WR_(NEXT|END) unless |
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* TX_DATA_READY is set |
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* */ |
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if (flags & SMIC_TX_DATA_READY) { |
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if (smic->write_count == 1) { |
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/* last byte */ |
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write_smic_control(smic, SMIC_CC_SMS_WR_END); |
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smic->state = SMIC_WRITE_END; |
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} else { |
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write_smic_control(smic, SMIC_CC_SMS_WR_NEXT); |
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smic->state = SMIC_WRITE_NEXT; |
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} |
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write_next_byte(smic); |
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write_smic_flags(smic, flags | SMIC_FLAG_BSY); |
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} else |
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return SI_SM_CALL_WITH_DELAY; |
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break; |
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|
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case SMIC_WRITE_NEXT: |
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if (status != SMIC_SC_SMS_WR_NEXT) { |
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start_error_recovery(smic, |
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"state = SMIC_WRITE_NEXT, " |
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"status != SMIC_SC_SMS_WR_NEXT"); |
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return SI_SM_CALL_WITH_DELAY; |
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} |
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/* this is the same code as in SMIC_WRITE_START */ |
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if (flags & SMIC_TX_DATA_READY) { |
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if (smic->write_count == 1) { |
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write_smic_control(smic, SMIC_CC_SMS_WR_END); |
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smic->state = SMIC_WRITE_END; |
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} else { |
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write_smic_control(smic, SMIC_CC_SMS_WR_NEXT); |
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smic->state = SMIC_WRITE_NEXT; |
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} |
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write_next_byte(smic); |
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write_smic_flags(smic, flags | SMIC_FLAG_BSY); |
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} else |
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return SI_SM_CALL_WITH_DELAY; |
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break; |
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|
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case SMIC_WRITE_END: |
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if (status != SMIC_SC_SMS_WR_END) { |
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start_error_recovery(smic, |
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"state = SMIC_WRITE_END, " |
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"status != SMIC_SC_SMS_WR_END"); |
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return SI_SM_CALL_WITH_DELAY; |
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} |
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/* data register holds an error code */ |
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data = read_smic_data(smic); |
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if (data != 0) { |
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if (smic_debug & SMIC_DEBUG_ENABLE) |
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dev_dbg(smic->io->dev, |
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"SMIC_WRITE_END: data = %02x\n", |
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data); |
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start_error_recovery(smic, |
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"state = SMIC_WRITE_END, " |
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"data != SUCCESS"); |
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return SI_SM_CALL_WITH_DELAY; |
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} else |
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smic->state = SMIC_WRITE2READ; |
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break; |
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|
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case SMIC_WRITE2READ: |
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/* |
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* we must wait for RX_DATA_READY to be set before we |
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* can continue |
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*/ |
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if (flags & SMIC_RX_DATA_READY) { |
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write_smic_control(smic, SMIC_CC_SMS_RD_START); |
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write_smic_flags(smic, flags | SMIC_FLAG_BSY); |
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smic->state = SMIC_READ_START; |
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} else |
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return SI_SM_CALL_WITH_DELAY; |
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break; |
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|
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case SMIC_READ_START: |
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if (status != SMIC_SC_SMS_RD_START) { |
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start_error_recovery(smic, |
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"state = SMIC_READ_START, " |
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"status != SMIC_SC_SMS_RD_START"); |
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return SI_SM_CALL_WITH_DELAY; |
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} |
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if (flags & SMIC_RX_DATA_READY) { |
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read_next_byte(smic); |
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write_smic_control(smic, SMIC_CC_SMS_RD_NEXT); |
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write_smic_flags(smic, flags | SMIC_FLAG_BSY); |
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smic->state = SMIC_READ_NEXT; |
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} else |
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return SI_SM_CALL_WITH_DELAY; |
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break; |
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|
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case SMIC_READ_NEXT: |
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switch (status) { |
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/* |
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* smic tells us that this is the last byte to be read |
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* --> clean up |
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*/ |
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case SMIC_SC_SMS_RD_END: |
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read_next_byte(smic); |
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write_smic_control(smic, SMIC_CC_SMS_RD_END); |
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write_smic_flags(smic, flags | SMIC_FLAG_BSY); |
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smic->state = SMIC_READ_END; |
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break; |
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case SMIC_SC_SMS_RD_NEXT: |
|
if (flags & SMIC_RX_DATA_READY) { |
|
read_next_byte(smic); |
|
write_smic_control(smic, SMIC_CC_SMS_RD_NEXT); |
|
write_smic_flags(smic, flags | SMIC_FLAG_BSY); |
|
smic->state = SMIC_READ_NEXT; |
|
} else |
|
return SI_SM_CALL_WITH_DELAY; |
|
break; |
|
default: |
|
start_error_recovery( |
|
smic, |
|
"state = SMIC_READ_NEXT, " |
|
"status != SMIC_SC_SMS_RD_(NEXT|END)"); |
|
return SI_SM_CALL_WITH_DELAY; |
|
} |
|
break; |
|
|
|
case SMIC_READ_END: |
|
if (status != SMIC_SC_SMS_READY) { |
|
start_error_recovery(smic, |
|
"state = SMIC_READ_END, " |
|
"status != SMIC_SC_SMS_READY"); |
|
return SI_SM_CALL_WITH_DELAY; |
|
} |
|
data = read_smic_data(smic); |
|
/* data register holds an error code */ |
|
if (data != 0) { |
|
if (smic_debug & SMIC_DEBUG_ENABLE) |
|
dev_dbg(smic->io->dev, |
|
"SMIC_READ_END: data = %02x\n", |
|
data); |
|
start_error_recovery(smic, |
|
"state = SMIC_READ_END, " |
|
"data != SUCCESS"); |
|
return SI_SM_CALL_WITH_DELAY; |
|
} else { |
|
smic->state = SMIC_IDLE; |
|
return SI_SM_TRANSACTION_COMPLETE; |
|
} |
|
|
|
case SMIC_HOSED: |
|
init_smic_data(smic, smic->io); |
|
return SI_SM_HOSED; |
|
|
|
default: |
|
if (smic_debug & SMIC_DEBUG_ENABLE) { |
|
dev_dbg(smic->io->dev, |
|
"smic->state = %d\n", smic->state); |
|
start_error_recovery(smic, "state = UNKNOWN"); |
|
return SI_SM_CALL_WITH_DELAY; |
|
} |
|
} |
|
smic->smic_timeout = SMIC_RETRY_TIMEOUT; |
|
return SI_SM_CALL_WITHOUT_DELAY; |
|
} |
|
|
|
static int smic_detect(struct si_sm_data *smic) |
|
{ |
|
/* |
|
* It's impossible for the SMIC fnags register to be all 1's, |
|
* (assuming a properly functioning, self-initialized BMC) |
|
* but that's what you get from reading a bogus address, so we |
|
* test that first. |
|
*/ |
|
if (read_smic_flags(smic) == 0xff) |
|
return 1; |
|
|
|
return 0; |
|
} |
|
|
|
static void smic_cleanup(struct si_sm_data *kcs) |
|
{ |
|
} |
|
|
|
static int smic_size(void) |
|
{ |
|
return sizeof(struct si_sm_data); |
|
} |
|
|
|
const struct si_sm_handlers smic_smi_handlers = { |
|
.init_data = init_smic_data, |
|
.start_transaction = start_smic_transaction, |
|
.get_result = smic_get_result, |
|
.event = smic_event, |
|
.detect = smic_detect, |
|
.cleanup = smic_cleanup, |
|
.size = smic_size, |
|
};
|
|
|